JP3171948B2 - Threshold voltage variation correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for correcting variations in threshold voltages of a plurality of MISFETs formed on the same chip.

[0002]

2. Description of the Related Art Semiconductor integrated circuits have achieved high integration, high speed, and low cost with the advance of fine processing technology. 2. Description of the Related Art Conventionally, high integration, that is, integration of a large number of semiconductor elements on a single chip, enables uniform and high-quality electrical characteristics of individual semiconductor elements, and enables stable operation of a large-scale circuit. The advantage has been brought. However, in recent years, ultra-high integration, which integrates a larger number of semiconductor elements beyond the conventional stage, is being realized.

[0003] Although further advances have been made in precision micromachining technology that enables such ultra-high integration, there is a limit in machining accuracy. It is difficult to process all of a very large number of ultrafine elements so as to have uniform electrical characteristics in a region near such a limit. For this reason, in an ultra-high-integrated circuit, an element whose electric characteristics are not uniform with other elements causes a failure in circuit operation. That is, the yield is reduced due to the variation in the electrical characteristics of the elements.

[0004]

As described above, conventionally, there has been a problem that a failure in circuit operation occurs due to variations in threshold voltages of a plurality of MISFETs constituting a semiconductor integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object the purpose of the present invention.
Among the variations in the electrical characteristics of the SFETs, the variation in the threshold voltage is improved, and the MI in a large-scale integrated circuit is improved.
An object of the present invention is to provide a method for correcting a threshold voltage variation that can contribute to improving the uniformity of the electrical characteristics of an SFET.

[0006]

In order to solve the above problems, the present invention employs the following configuration. That is, the present invention provides a method for controlling each MISFET so that the variation of the threshold voltage among a plurality of MISFETs constituting a semiconductor integrated circuit is reduced.
In a threshold voltage variation correction method for correcting a threshold voltage of an FET, a MISF whose threshold voltage is to be corrected is
With the same drain bias and the same source bias of the ET, the same well bias is applied to the MISFET, the same gate bias is applied simultaneously, and each MISFET is applied to the MISFET according to the threshold voltage before correction. A part of the flowing source current or well current is supplied to each MIS.
It is characterized by being implanted into the gate insulating film of the FET.

[0007]

In a MISFET, when a source current is applied while a well bias is applied, a part of the source current is injected into the gate insulating film, and the threshold voltage changes. Here, the source current is source bias, drain bias,
Although it changes depending on the gate bias and the threshold voltage, if other parameters are constant, the higher the threshold voltage is, the smaller the source current is, and the change in the threshold value due to carrier injection is small. Conversely, the lower the threshold voltage, the greater the source current and the greater the change in threshold voltage due to carrier injection.

When a well bias is applied so large that a part of the well current is injected into the gate oxide film,
When the same gate bias is applied, the higher the threshold voltage, the smaller the potential difference between the substrate and the gate oxide film, the smaller the amount of injected carriers, and the smaller the change in threshold. Conversely, the lower the threshold voltage, the greater the potential difference, the greater the amount of injected carriers, and the greater the change in threshold voltage.

Therefore, as in the present invention, the MIS to be corrected
By applying the same well bias and the same gate bias simultaneously with the same source bias and the same drain bias of the FET, the threshold voltage of any MISFET changes. The threshold voltage can be changed more greatly as the MISFET has a lower threshold voltage. Therefore, in the case of a MISFET whose threshold voltage is increased by carrier injection into the gate insulating film, the threshold values of a plurality of MISFETs having different threshold values can be automatically brought closer.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments, the basic principle of the present invention will be described.

FIG. 1 shows the basic characteristics of the method of correcting a variation in threshold voltage according to the present invention in the case where there are two MISFETs. FIG. 2 shows the MISFET used in the method of correcting variation in threshold voltage according to the present invention. Shows the electrical characteristics of Now, the two MISFETs shown in FIGS.
It is assumed that the threshold voltages Vt (1) and Vt (2) of (Tr1, Tr2) vary, and the threshold voltage of Tr1 is lower. Vt (1) <Vt (2) (1)

If the source bias Vs and the drain bias VD of the transistors Tr1 and Tr2 are the same, the dependence of the source current on the gate bias Vg is as shown in FIG. That is, the source currents Is (1) and I (1) when the same gate bias Vg * is applied corresponding to the difference in threshold voltage.
There is a difference in s (2). Tr1 having a lower threshold voltage has a larger source current, and Tr2 having a higher threshold voltage has a smaller source current. Is (1) <Is (2) ... (2)

Therefore, the threshold voltages Vt (1) and Vt (2) change according to the magnitude of the source current, ΔVt (1),
If Vt (2) is generated and the following equation is satisfied, T
The threshold voltages of r1 and Tr2 can be made sufficiently close. Vt (1) + ΔVt (1) = Vt (2) + ΔVt (2) (3)

The fixed charges Q (1) and Q (2) in the gate insulating film caused by injecting a part of the source current into the gate insulating film to cause the change in threshold voltage ΔVt.
Is used, the source current I of Tr1 having a low threshold voltage is
s (1) is larger than the source current Is (2) of Tr2,
(3) The condition of the expression can be realized.

In the method of correcting a threshold voltage variation according to the present invention, the difference in the source current or the well current caused by the variation in the threshold voltage is used. Change of other MIS
The threshold voltage of the FET can be automatically changed more than the change, and the threshold voltages of two or more MISFETs can be automatically made uniform. For this purpose, in the present invention, a well bias is applied to the MISFET to accelerate carrier injection into the gate insulating film. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram showing a first embodiment in which the method of the present invention is applied to a flip-flop transistor in a sense amplifier of a DRAM. This circuit includes Tr10 and Tr20 whose sources are commonly connected, and Tr30 for switching connected to the drain side of Tr10, and Tr40 for switching connected to the drain side of Tr20. The sources of Tr10 and Tr20 are connected to a pad 51, Tr30 is connected to a pad 52, and Tr40 is connected to a pad 53. In this circuit, Tr10,
It is essential that the threshold voltage of Tr20 is sufficiently close,
In this embodiment, the variation in threshold voltage between Tr10 and Tr20 is corrected.

FIG. 4 is a sectional view of the device structure of Tr10 and Tr20.
It is a figure which shows a surface typically. Surface of n-type Si substrate 60
A p-type well 61 is formed on the surface of the well 61.
n⁺ -Type diffusion layers (source / drain) 11, 12, gate
The oxide film (gate insulating film) 13 and the gate electrode 14
Tr10 and n⁺ Diffusion layer (source / drain) 2
1, 22; a gate oxide film (gate insulating film) 23;
And a Tr 20 formed of a gate electrode 24.

In such a configuration, the bias (VS) of the pad 51 is set to 0, and Tr3 connected to CSL1 is
0, Tr40 is turned on, and the same bias Vg * is applied to the pads 52 and 53. By doing so, Tr1
0 and Tr20 have the same source bias, the same drain bias, and the same gate bias.
At this time, the same well bias (for example, 3 Vcc / 2) is applied to each of Tr10 and Tr20.

As the bias Vg * is applied, Tr1
Source currents Is (1) and Is (2) corresponding to the difference between the threshold voltages of Tr0 and Tr20 flow, and MISFE having a low threshold voltage.
More carriers are injected into the T gate insulating film. Further, since the well bias is applied, carrier injection is accelerated. Then, threshold voltage changes ΔVt (1) and ΔVt (2) occur, and Tr10 and Tr2 are changed.
The threshold voltage of 0 approaches.

As a result, the threshold voltages of Tr10 and Tr20 become substantially equal. Note that, when no well bias is applied, there is almost no carrier injection into the gate insulating film, and there is no change in the threshold voltage. Therefore, once the threshold voltage is corrected according to the present embodiment, the threshold voltage does not change in subsequent use, and the MIS with the uniform threshold voltage on the same chip
An FET can be realized.

As described above, according to the present embodiment, the threshold voltages of the MISFETs formed on the same chip can be made uniform only by passing a current once. For this reason, it is possible to improve the operation failure due to the variation of the threshold voltage, and to improve the yield of the large-scale integrated circuit.

FIG. 3 is a view for explaining a second embodiment of the present invention. A floating gate made of polysilicon is provided in the gate insulating films of Tr10 and Tr20,
This is an example using Tr70 and Tr80 having a ROM structure. In this case, the injection of carriers Q (1) and Q (2) into the gate insulating film at the time of correcting the threshold voltage variation is accelerated, and the threshold voltage changes ΔVt (1) and ΔVt (2) are efficiently reduced. And T
The threshold voltages of r70 and Tr80 can be quickly approached.

The present invention is not limited to the above embodiments. In this embodiment, an n-channel MOS transistor is used. However, it is needless to say that the present invention can be applied to a p-channel MOS transistor. Furthermore, MOS
The present invention is not limited to the structure, and can be applied to any MIS structure. Further, the magnitude and time of each bias applied at the time of correcting the threshold voltage may be appropriately determined according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[0024]

As described above in detail, according to the present invention, the same well bias is applied to the MISFETs on the same chip, and the same gate bias is simultaneously applied to the MISFETs to cause a source current to flow. By injecting part of the source current into the gate insulating film, the respective threshold voltages can be made closer. Therefore, among the variations in the electrical characteristics of the MISFET in the integrated circuit, the variations in the threshold voltage can be corrected, and it is possible to contribute to the improvement in the uniformity of the electrical characteristics of the MISFET in the large-scale integrated circuit.

[Brief description of the drawings]

FIG. 1 is for explaining the basic principle of the present invention,
FIG. 3 is a diagram showing a circuit configuration of Trs;

FIG. 2 is for explaining the basic principle of the present invention,
A diagram showing the electrical characteristics of the Tr

FIG. 3 is a diagram showing a first embodiment in which the present invention is applied to a flip-flop Tr;

FIG. 4 is a cross-sectional view of an element structure schematically showing a part of FIG.

FIG. 5 is a diagram showing a second embodiment in which the present invention is applied to a flip-flop EPROM-Tr.

[Explanation of symbols]

10,20,30,40 ... MISFET, 11,12,21,22 ... n ⁺ Diffusion layers (source / drain), 13, 23 gate oxide film (gate insulating film), 14, 24 gate electrode, 51, 52, 53 pad, 60 n-type Si substrate, 61 p-type well, 70, 80... MISFET of EPROM structure.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 27/10 311 H01L 27/06 H01L 27/08

Claims (3)

(57) [Claims] 1. A plurality of MISFs constituting a semiconductor integrated circuit
In the method of correcting the threshold voltage of each MISFET so that the variation of the threshold voltage between ETs is reduced, the same drain bias and the same source bias are applied to the MISFET, and the same is applied to the MISFET. A well bias is applied, and the same gate bias is applied simultaneously.
A part of the carrier current flowing through the ISFET is
A method of correcting a variation in threshold voltage, wherein the method is performed by injecting into a gate insulating film of an FET. 2. Each MISF according to a threshold voltage before correction
The carriers injected into the gate insulating film of the ET are each MI.
Characterized in that it is a part of the source current of the SFET 請
A method for correcting a threshold voltage variation according to claim 1 . 3. Each MISF according to a threshold voltage before correction
The carriers injected into the gate insulating film of the ET are each MI.
Characterized in that it is a part of the well current SFET 請
A method for correcting a threshold voltage variation according to claim 1 .