JPH053295A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To stabilize substrate potential of a semiconductor integrated circuit having an MOSFET and to stabilize operation of the MOSFET. CONSTITUTION:N-channel and P-channel MOSFET are formed on an upper surface of a P-type silicon substrate 1 provided with a P<+>-type diffusion layer 3 whose conductivity is improved by introducing P-type impurities to a lower side, and voltage change due to movement of carrier is restrained by the P<+>-type diffusion layer 3; thereby, substrate potential is stabilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, as shown in FIG. 2, an N-type well 2 is formed on an upper surface of a P-type silicon substrate 1, and an N-type well 2 and a P-type region other than the N-type well 2 are formed. The gate electrode 5 is provided on the surface of the silicon substrate 1 via the gate oxide film 4, and the gate electrode 5 is provided in the N-type source / drain regions 6 and the N-type well 2 provided on the P-type silicon substrate 1 in alignment with the gate electrode 5. An N channel MOSFET and a P channel MOSFET are formed by the P type source / drain region 7. Further, the ground potential GND is applied to the P ⁺ type diffusion layer 8 provided on the P type silicon substrate 1 and the N ⁺ provided on the N type well 2 is applied.
A power supply potential V _cc is applied to the mold diffusion layer 9, and an electrode 10 formed of a metallized layer made of metal such as gold is provided on the back surface of the P-type silicon substrate 1.

Here, in order to stabilize the potential of the P-type silicon substrate 1, it is necessary to form a large number of P ⁺ -type diffusion layers 8 for contacting the substrate in a wide range, and to form the N-type well 2. In order to stabilize the potential, it is necessary to form a large number of N ⁺ type diffusion layers 9 for well contacts in the N type well 2. In addition, after forming all the circuit elements in the electrode 10, it is necessary to polish the lower surface of the P-type silicon substrate 1 on the back surface to make it thin, and then vapor-deposit a metal layer.
Stabilizes the potential of the lower surface of the P-type silicon substrate 1, thereby stabilizing the potential of the P-type silicon substrate 1.

P-type silicon substrate 1 potential, N-type well 2
The potential of the back gate of the field effect transistor is stabilized by the stable potential of the field effect transistor, and the field effect transistor operates stably.

[0005]

In this conventional semiconductor integrated circuit, due to the distribution of the substrate contact layer and the well contact layer, deviation of the substrate potential is likely to occur. Therefore, in the portion where the substrate potential fluctuates, the surface of the substrate is changed. The potential of the back gate of the field effect transistor formed in
There is a problem that the characteristics of the field effect transistor fluctuate due to fluctuations, and in particular, in the portion where the substrate potential fluctuates significantly, the parasitic junction type transistor existing in the substrate forms a thyristor and the power supply current increases significantly, so that the semiconductor integrated circuit There is a problem that not only the function of is damaged but also one of the causes of the destruction of the circuit.

Further, in order to stabilize the substrate potential by the back surface electrode, it is necessary to form all the circuit elements by diffusion and then polish the back surface to thin the film and then evaporate gold or the like. However, since it is weak and expensive metal such as gold is used, it becomes expensive, and in particular, it can be used only for a semiconductor integrated circuit that requires high-speed operation.

[0007]

A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a MOSFET provided on an upper surface of a semiconductor substrate, wherein impurities of the same conductivity type as those of the semiconductor substrate are introduced into the lower surface of the semiconductor substrate. And an impurity diffusion layer whose conductivity is increased.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention.

As shown in FIG. 1, an N-type well 2 provided on the upper surface of a P-type silicon substrate 1 and a P ⁺ -type diffusion layer 3 provided by ion-implanting boron ions on the lower surface of the P-type silicon substrate 1. , The N-type well 2 and the gate electrode 5 provided on the surface of the P-type silicon substrate 1 in the region other than the N-type well 2 via the gate oxide film 4, and the P-type silicon in alignment with each of the gate electrodes 5. The N-type source / drain region 6 provided on the substrate 1, the P-type source / drain region 7 provided on the N-type well 2, and the ground potential GND provided on the P-type silicon substrate 1.
A P ⁺ -type diffusion layer 8 that applies a configured and an N ⁺ -type diffusion layer 9 for applying a power source potential V _cc provided the N-type well 2. The P ⁺ type diffusion layer 3 is formed on the upper surface of the P type silicon substrate before forming the element.

Here, the impurity concentration of the P-type silicon substrate 1 is low, and therefore, the resistance is high and the voltage changes due to the movement of carriers. However, since the impurity concentration of the P ⁺ type diffusion layer 3 provided below the P type silicon substrate 1 is higher than the impurity concentration of the P type silicon substrate 1, the resistance is low, and carriers move through this P ⁺ type diffusion layer 3. Occurs, and voltage fluctuation due to carrier movement is reduced. Therefore, the potential of the P-type silicon substrate 1 becomes stable. Therefore, the potential of the back gate of the field effect transistor becomes stable, and the field effect transistor also operates stably.

[0012]

As described above, according to the present invention, by forming a layer having an impurity concentration higher than that of the substrate by ion implantation on the back surface of the semiconductor substrate, the substrate potential is stabilized and the field effect transistor is stabilized. It has the effect of being operated.

Before forming a circuit element on the upper surface of the substrate,
Since the entire back surface can be ion-implanted, there is an effect that batch processing can be performed regardless of the circuit configuration of the semiconductor integrated circuit and without adversely affecting the characteristics.

Further, since the substrate potential is stabilized without forming the back metallization layer, the step of forming the back metallization layer can be reduced, and expensive metals such as gold are not used, so that the cost is low and general semiconductors are used. It has the effect that it can also be used in integrated circuits.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 P-type silicon substrate 2 N-type well 3,8 P ⁺ type diffusion layer 4 Gate oxide film 5 Gate electrode 6,7 Source / drain region 9 N ⁺ type diffusion layer 10 Electrode

Claims (1)

Claims: 1. A MOSFET provided on the upper surface of a semiconductor substrate.
In the semiconductor integrated circuit having the above-mentioned, there is provided an impurity diffusion layer on the lower surface of the semiconductor substrate, in which an impurity of the same conductivity type as that of the semiconductor substrate is introduced to increase the conductivity.