JPH02122315A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02122315A JPH02122315A JP63276545A JP27654588A JPH02122315A JP H02122315 A JPH02122315 A JP H02122315A JP 63276545 A JP63276545 A JP 63276545A JP 27654588 A JP27654588 A JP 27654588A JP H02122315 A JPH02122315 A JP H02122315A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- oxide film
- gate oxide
- thickness
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、作り込まれた素子に必要な基準電圧を得る基
準電圧源を内蔵した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a built-in reference voltage source for obtaining a reference voltage necessary for a built-in element.
近年、高耐圧出力部と低耐圧ロジック部をオンチップに
て共存する半導体装置が開発されている。In recent years, semiconductor devices have been developed in which a high-voltage output section and a low-voltage logic section coexist on-chip.
このような半導体装置においても、電源電圧、温度等に
対する変動が低い定電圧を得る基準電圧源をオンチップ
化する場合がある。従来、この種の基準電圧源は、第3
図に示すように、外部電源電圧vanと接地間との間に
抵抗4を介して接続されたMOSFET5.6で基準電
圧を作り、これをオペアンプ3に人力し、その増幅出力
が一方のMOSFET5のゲートGに印加されるもので
ある。Even in such a semiconductor device, a reference voltage source that obtains a constant voltage with low fluctuations due to power supply voltage, temperature, etc. may be provided on-chip. Conventionally, this type of reference voltage source
As shown in the figure, a reference voltage is created with a MOSFET 5.6 connected between the external power supply voltage van and the ground via a resistor 4, and this is input to the operational amplifier 3, whose amplified output is output from one MOSFET 5. This is applied to the gate G.
基準電圧を作成するMOSFET5.6の一方6はチャ
ネル領域を選択的なイオン注入によって導電率を異なら
しめたもので、動抵抗値の差で基準電圧が得られる。One of the MOSFETs 5 and 6 for generating the reference voltage has a channel region having different conductivity by selective ion implantation, and the reference voltage can be obtained from the difference in dynamic resistance.
しかしながら、上記従来の半導体装置の基準電圧源にあ
っては、一方のMOSFET6を得るためには選択的な
イオン注入工程が必要であり、その分の工数が増し、製
造コスト高となる。However, in the conventional reference voltage source of the semiconductor device described above, a selective ion implantation step is required to obtain one MOSFET 6, which increases the number of steps and increases the manufacturing cost.
本発明は、上記問題点を解決するものであり、その目的
は、高耐圧部と低耐圧部を同一チップ上に有するものに
おいて、基準電源を得るための一対のMOSFETのだ
めの特別の工程を不要とした半導体装置を提供すること
にある。The present invention solves the above problems, and its purpose is to eliminate the need for a special process for a pair of MOSFETs to obtain a reference power source in a device that has a high withstand voltage section and a low withstand voltage section on the same chip. The object of the present invention is to provide a semiconductor device with a high level of performance.
上記目的を達成するため、本考案に係る半導体装置の構
成は、相異なるしきい値電圧の差を基準電圧として生成
する一対のMOSFETを内蔵するものであって、その
一対のMOSFETのゲート酸化膜が相異なる膜厚とさ
れている。In order to achieve the above object, the configuration of a semiconductor device according to the present invention includes a pair of MOSFETs that generate a difference between different threshold voltages as a reference voltage, and a gate oxide film of the pair of MOSFETs. are said to have different film thicknesses.
かかる構成によれば、一対のMOSFETのうち、膜厚
の厚いものは高耐圧部の製造工程で作ることができ、膜
厚の薄いものは低耐圧部の製造工程で作ることができる
ので、基準電源用の一対のMOSFETのための特別な
工程は不要となる。According to this configuration, of the pair of MOSFETs, the one with the thicker film thickness can be manufactured in the manufacturing process of the high voltage withstanding part, and the one with the thinner film thickness can be manufactured in the manufacturing process of the lower voltage part, so that the standard can be met. No special process is required for the pair of MOSFETs for power supply.
次に、本発明の実施例を添付図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the accompanying drawings.
第1図は本発明に係る半導体装置の第1実施例における
基準電圧源を示す回路図である。なお、第1図において
第3図に示す部分と同一部分には同一参照符号を付しで
ある。FIG. 1 is a circuit diagram showing a reference voltage source in a first embodiment of a semiconductor device according to the present invention. Note that the same parts in FIG. 1 as those shown in FIG. 3 are given the same reference numerals.
1はVooi源と接地間に抵抗4を介して接続されたエ
ンハンストメント型のNチャネルMO3FETで、2は
同様にV!11電源と接地間に抵抗4を介して接続され
たエンハンストメント型のNチャネルMO3FETであ
る。MO3FETIのゲートGはそのソースSとオペア
ンプ3の反転入力に接続されており、MOSFET2の
ゲートGはオペアンプ3の出力に接続されている。MO
SFET1は低耐圧ロジック部を構成する薄いゲート酸
化膜のFETの製造工程で同時に作られ、MOSFET
2は高耐圧出力部を構成する厚いゲート酸化膜のFET
の製造工程で同時に作られる。従って、一方のMO3F
ETIのゲート酸化膜の膜厚は他方のMOSFET2の
それに比して薄く形成される。この膜厚の差によるしき
い値電圧の差ΔVT11は、次式で与えられる。1 is an enhancement type N-channel MO3FET connected between the Vooi source and ground via a resistor 4, and 2 is similarly V! 11 is an enhancement type N-channel MO3FET connected between a power supply and ground via a resistor 4. The gate G of MO3FETI is connected to its source S and to the inverting input of operational amplifier 3, and the gate G of MOSFET2 is connected to the output of operational amplifier 3. M.O.
SFET1 is made at the same time as the FET manufacturing process with a thin gate oxide film that constitutes the low voltage logic section, and is a MOSFET.
2 is an FET with a thick gate oxide film that constitutes a high breakdown voltage output section.
are made at the same time during the manufacturing process. Therefore, one MO3F
The thickness of the gate oxide film of the ETI is formed thinner than that of the other MOSFET 2. The threshold voltage difference ΔVT11 due to this difference in film thickness is given by the following equation.
ot
O2
s s
εSム
εO
:MO3FET1のゲート容量
:MO3FET2のゲート容量
:界面電荷
:Si(シリコン)比誘電率
:誘電率
;単位電荷量
N5ub:基板濃度
φf :フェルミポテンシャル
この差ΔVTHをオペアンプ3にてフィードバックをか
けることにより、MO3FETIのソース電圧をVoと
すると、Vo+ΔVT11の定電圧が出力が得られる。ot O2 s s εS εO: Gate capacitance of MO3FET1: Gate capacitance of MO3FET2: Interface charge: Si (silicon) relative dielectric constant: Dielectric constant; Unit charge N5ub: Substrate concentration φf: Fermi potential This difference ΔVTH is applied to operational amplifier 3 By applying feedback, a constant voltage of Vo+ΔVT11 can be obtained, where Vo is the source voltage of MO3FETI.
第2図は第2実施例を示す回路図で、第1図に示す部分
と同一部分には同一参照符号が付されている。FIG. 2 is a circuit diagram showing a second embodiment, in which the same parts as those shown in FIG. 1 are given the same reference numerals.
この実施例における第1実施例と異なる点は、エンハン
ストメント型のNチャネルMOSFET1に代えて、デ
プレション型のNチャネルMO3FETI’を用い、こ
のデプレション型のMO3FETI’は、低耐圧ロジッ
ク部の工程で同時に作るので、ゲート酸化膜の膜厚はエ
ンハンストメント型のNチャネルMOSFET2のそれ
に比して薄くなり、デプレション型のMOSFET1’
のゲートGとドレインDとが接続されている。かかる構
成においては、しきい値電圧の差ΔVt*カオペアンプ
3から出力される。This embodiment differs from the first embodiment in that a depletion type N-channel MO3FETI' is used instead of the enhancement type N-channel MOSFET1, and this depletion type MO3FETI' is used in the process of the low breakdown voltage logic section. Since the thickness of the gate oxide film is thinner than that of the enhancement type N-channel MOSFET 2, the thickness of the gate oxide film is thinner than that of the enhancement type N-channel MOSFET 1'.
The gate G and drain D of are connected. In this configuration, the threshold voltage difference ΔVt* is output from the operational amplifier 3.
このように、両MO3FETI (1’ )、2のゲ
ート酸化膜厚の差によるしきい値電圧の差を基準電圧と
するものであるから、従来の如くの一方のMOSFET
を形成する際イオン注入工程を付加する必要がな(、低
耐圧ロジック部および高耐圧出力部それぞれの工程で足
りるから、工数の削減、簡素化を図ることができ、低コ
ストの半導体装置が実現される。In this way, since the difference in threshold voltage due to the difference in gate oxide film thickness of both MO3FETI (1') and 2 is used as the reference voltage, one of the MOSFETs as in the conventional
There is no need to add an ion implantation process when forming the low-voltage logic section and the high-voltage output section, so the number of man-hours can be reduced and simplified, resulting in a low-cost semiconductor device. be done.
以上説明したように、本発明に係る半導体装置は基準電
圧源たる一対のMOSFETの一方ゲート酸化膜厚を他
方のそれに比して薄くすることによって異なるしきい値
電圧となし、その差を基準電圧として供給する点に特徴
を有するものであるから、高耐圧部および低耐圧部の工
程を利用可能となり、従来行われていた一方のMO3F
ET形成における単独イオン注入工程が不要となるので
、従来に比して、製造工数を削減でき、製造コスト低廉
化を図り得る。As explained above, in the semiconductor device according to the present invention, the gate oxide film thickness of one of a pair of MOSFETs serving as a reference voltage source is made thinner than that of the other to obtain different threshold voltages, and the difference is converted into a reference voltage. Since it is characterized in that it is supplied as a
Since a single ion implantation step in forming the ET is not required, the number of manufacturing steps can be reduced and the manufacturing cost can be reduced compared to the conventional method.
第1図は、本発明に係る半導体装置の第1実施例におけ
る基準電圧源を示す回路図である。
第2図は、本発明に係る半導体装置の第2実施例におけ
る基準電圧源を示す回路図である。
第3図は、従来の半導体装置における基準電圧源を示す
回路図である。
l ケー)酸([4の薄いエンハンストメント型のN
チャネルMO5FET、1’ ゲート酸化膜の薄いデ
プレション型のNチャネルMO3FET12 ゲート酸
化膜の厚いエンハンストメント型のNチャネルMO3F
ET、3 オペアンプ、4第
図
第
区FIG. 1 is a circuit diagram showing a reference voltage source in a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a circuit diagram showing a reference voltage source in a second embodiment of the semiconductor device according to the present invention. FIG. 3 is a circuit diagram showing a reference voltage source in a conventional semiconductor device. l K) Acid ([4 thin enhancement type N
Channel MO5FET, 1' Depletion type N-channel MO3FET with thin gate oxide film 12 Enhancement type N-channel MO3F with thick gate oxide film
ET, 3 Operational Amplifier, 4 Fig. Section
Claims (1)
する一対のMOSFETを内蔵する半導体装置であって
、該一対のMOSFETのゲート酸化膜が相異なる膜厚
であることを特徴とする半導体装置。(1) A semiconductor device incorporating a pair of MOSFETs that generate a difference between different threshold voltages as a reference voltage, the semiconductor device characterized in that the gate oxide films of the pair of MOSFETs have different thicknesses. Device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63276545A JPH02122315A (en) | 1988-11-01 | 1988-11-01 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63276545A JPH02122315A (en) | 1988-11-01 | 1988-11-01 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02122315A true JPH02122315A (en) | 1990-05-10 |
Family
ID=17570974
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63276545A Pending JPH02122315A (en) | 1988-11-01 | 1988-11-01 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02122315A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0554673A (en) * | 1991-08-26 | 1993-03-05 | Nec Corp | Reference potential generating circuit |
JP2009146021A (en) * | 2007-12-12 | 2009-07-02 | Ricoh Co Ltd | Voltage source circuit and temperature detection circuit using voltage source circuit |
-
1988
- 1988-11-01 JP JP63276545A patent/JPH02122315A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0554673A (en) * | 1991-08-26 | 1993-03-05 | Nec Corp | Reference potential generating circuit |
JP2009146021A (en) * | 2007-12-12 | 2009-07-02 | Ricoh Co Ltd | Voltage source circuit and temperature detection circuit using voltage source circuit |
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