JP2003197764A - Semiconductor device, reference voltage generator circuit and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generator circuit and its manufacturing method which is less dependent on temperature and has no need for a complicated manufacturing process. <P>SOLUTION: Gates and channels of two transistors T1, T2 are made of the same polycrystalline silicons and the impurity concentrations of the gates of the transistors T1, T2 are set to 10<SP>+14</SP>/cm<SP>3</SP>or less and 10<SP>+19</SP>/cm<SP>3</SP>or more, respectively. This results in that the work function of the transistor T1 gate is higher by 0.3-0.6 eV than that of the transistor T2 gate and hence the threshold voltage difference between the transistors T1, T2 is 0.3-0.6 V. The reference voltage generator circuit differentially amplifies the drain voltages of the transistors T1, T2 by an operational amplifier OA and feeds its output back to the gate of the transistor T1, thereby outputting a reference voltage less dependent on temperature from the operational amplifier OA. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a reference voltage generating circuit using a complementary field effect transistor semiconductor integrated circuit and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIGS. 2A and 2B are configuration diagrams of a conventional reference voltage generating circuit. FIG. 2A is a circuit configuration diagram and FIG. 2B is a configuration diagram. Inside transistors M1 and M2
It is a cross-sectional view showing the structure of. This reference voltage generation circuit
The reference voltage is generated based on the difference between the threshold voltages of two transistors. As shown in FIG. 2A, the drain is connected to the power supply terminal E1 through the resistor circuit R1 and the source is connected through the constant current circuit H. It has an insulated gate transistor M1 which is connected to a power supply terminal E2 forming a pair with the power supply terminal E1 and has a gate connected to a drain.

The reference voltage generating circuit has an insulated gate in which the drain is connected to the power supply terminal E1 through the resistance circuit R2 having the same resistance value as the resistance circuit R1 and the source is connected to the power supply terminal E2 through the constant current circuit H. Type transistor M2.

The drains of the insulated gate transistors M1 and M2 are connected to the − input terminal and the + input terminal of the differential amplifier MA whose gain is set to 1, respectively. The output side of the differential amplifier MA is an insulated gate transistor M.
The second gate is connected to the reference voltage output terminal T.

These insulated gate type transistors M1,
As shown in FIG. 2B, M2 is provided in the insulating film 12 provided on the substrate 11. The insulated gate transistor M1 has main surfaces 16a and 16b facing each other,
A p-type channel region 13, an n-type source region 14, and an n-type drain region 15 are formed between the main surfaces 16a and 16b. The main surface 16b is the insulating film 1
The gate electrode 18 is disposed on the channel region 13 of the main surface 16a with the gate insulating film 17 interposed therebetween.

The insulated gate transistor M2 also has main surfaces 26a and 26b facing each other.
A p-type channel region 23, an n-type source region 24, and an n-type drain region 25 are formed between 26b. A gate electrode 28 is provided on the channel region 23 of the main surface 26a with a gate insulating film 27 interposed therebetween.
On the other hand, on the main surface 26b side in contact with the insulating film 12, a second gate electrode 28 'is arranged inside the insulating film 12 via a gate insulating film 27'.

The two insulated gate transistors M1 and M2 thus constructed have different gate capacitances. That is, the gate capacitance of the insulated gate transistor M2 is 2
The gate capacitance of the second gate electrode 28 'is larger than the gate capacitance of the insulated gate transistor M1. For this reason,
The threshold voltage VT2 of the insulated gate transistor M2 becomes higher than the threshold voltage VT1 of the insulated gate transistor M1.

According to the reference voltage circuit of FIG. 2A, a resistor circuit R1 and a first series circuit including an insulated gate transistor M1 and a resistor circuit R2 are provided between the power supply terminals E1 and E2.
And a parallel circuit of the insulated gate transistor M2 and the second series circuit is connected through the constant current circuit H. As a result, the current flowing in the constant current circuit H is shunted into the first and second series circuits, and a potential difference corresponding to the difference between these currents is generated between the + input terminal and the − input terminal of the differential amplifier MA. Given to. Then, the output voltage of the differential amplifier MA is fed back to the gate of the insulated gate transistor M2, and the current flowing through the second series circuit is controlled.

As a result, the reference voltage output terminal T has a threshold voltage VT of the two insulated gate transistors M1 and M2.
The threshold voltage difference (VT1−VT2) between 1 and VT2 is output as a reference voltage based on the power supply terminal E2.

The threshold voltage difference is obtained by the difference in the gate capacitance between the two insulated gate transistors M1 and M2, that is, the difference in the gate structure and the size, and has almost no temperature dependence. Therefore, a reference voltage having no temperature dependence can be obtained as compared with the case where the threshold voltage difference is obtained by the difference in impurity concentration of the channel regions of the two insulated gate transistors.

[0011]

However, the conventional reference voltage generating circuit has the following problems. That is, the insulated gate transistor M2 has, in addition to the gate electrode 28 arranged on the channel region 23 of the main surface 26a,
The second gate electrode 2 is provided inside the insulating film 12 on the main surface 26b side.
It has a structure in which 8'is embedded. Therefore, there is a problem that the manufacturing process becomes extremely complicated.

The present invention provides a semiconductor device, a reference voltage generating circuit and a method of manufacturing the same which solves the problems of the prior art and has little temperature dependence and does not require a complicated manufacturing process. Is.

[0013]

In order to solve the above-mentioned problems, a first invention of the present invention is based on a difference in threshold voltage between field effect type first and second transistors having different threshold voltages. In the reference voltage generation circuit that generates the reference voltage,
The first and second transistors are configured such that the channel portions have the same impurity concentration, the gate electrodes have the same conductivity type, and the gate electrodes have different impurity concentrations.

According to a second aspect of the present invention, in the same reference voltage generating circuit as the first aspect, the first and second transistors have the same impurity concentration in the channel portion as the impurity concentration in the semiconductor substrate and impurities in the gate electrode. Have the same conductivity type and different impurity concentrations in the gate electrode.

A third aspect of the present invention is the same as the first or second aspect, wherein the impurity concentration of the gate electrode of the first transistor is set to 10 ⁺¹⁹ / cm 3 so that the gate electrode has conductivity similar to that of metal. The impurity concentration of the gate electrode of the second transistor is set to ³ or more, and is set to 10 ⁺¹⁶ / cm ³ or less so that the gate electrode has conductivity similar to that of a semiconductor.

According to a fourth aspect of the present invention, in the same reference voltage generating circuit as the first aspect of the present invention, the first and second transistors have the impurity concentration of the channel portion equal to the impurity concentration of the semiconductor substrate and the impurity of the gate electrode. The impurity concentrations are set to 10 ⁺¹⁹ / cm ³ or more so that the gate electrodes have different conductivity types and the gate electrodes have conductivity similar to that of metal.

A fifth aspect of the present invention is a method of manufacturing a reference voltage generating circuit for generating a reference voltage based on a threshold voltage difference between field effect type first and second transistors having different threshold voltages. The gate electrode of is masked with a resist, and the gate electrode of the first transistor is
A step of implanting impurity ions with the same surface density as that of the source region and the drain region is performed.

According to a sixth aspect of the present invention, in the same reference voltage generating circuit manufacturing method as the fifth aspect, a first mask having a width shorter than the gate length of the gate electrode is formed on the gate electrode of the second transistor. And implanting impurity ions into the gate electrode of the first transistor at the same areal density as the source region and the drain region, and an opening having a width shorter than the gate length of the gate electrode of the first transistor. And forming a second mask exposing the upper surface of the gate electrode of the first transistor through the opening, and then forming a second mask on the gate electrode of the second transistor different from the gate electrode of the first transistor. And a step of implanting conductivity type impurity ions.

In a seventh aspect based on the fifth or sixth aspect, a narrow constricted portion is provided between the gate electrode of the second transistor and a contact region for metal wiring on the gate electrode. The resist is formed to have a size smaller than the gate length of the gate electrode of the second transistor by twice the size of the alignment margin of photolithography.

An eighth invention is formed on the semiconductor substrate between the source region and the drain region and the source and drain regions of the second conductivity type formed on the semiconductor substrate of the first conductivity type. A first conductivity type channel region and a gate electrode formed on the channel region.
In a semiconductor device that generates a reference voltage based on a threshold voltage difference between the first and second transistors, the impurity concentrations of channel regions of the first and second transistors are substantially the same, and the impurity concentration of the first and second transistors is the same. Both of the gate electrodes are made of a semiconductor material, are of the second conductivity type, and the impurity concentration of the gate electrode of the first transistor is higher than the impurity concentration of the gate electrode of the second transistor. I am trying.

In a ninth aspect based on the eighth aspect, the impurity concentration of the channel region is set to be substantially the same as the impurity concentration of the semiconductor substrate.

In a tenth aspect based on the eighth aspect, the impurity concentration of the gate electrode of the first transistor is set to such an extent that the gate electrode exhibits substantially the same conductivity as metal.
In addition, the impurity concentration of the gate electrode of the second transistor is
The gate electrode is set to have a conductivity substantially similar to that of the semiconductor.

An eleventh invention is the tenth invention, wherein
The impurity concentration of the gate electrode of the first transistor is set to about 10
The impurity concentration of the gate electrode of the second transistor is set to about 10 ⁺¹⁶ / cm ³ or less, and ⁺¹⁹ / cm ³ or more.

A twelfth invention is formed on the semiconductor substrate between the source region and the drain region, and the source region and the drain region of the second conductivity type formed on the semiconductor substrate of the first conductivity type. A first conductivity type channel region and a gate electrode formed on the channel region.
In a semiconductor device that generates a reference voltage based on a threshold voltage difference between the first and second transistors, the impurity concentrations of channel regions of the first and second transistors are substantially the same, and the impurity concentration of the first and second transistors is the same. The gate electrode is made of a semiconductor material, the gate electrode of the first transistor is of the first conductivity type, the gate electrode of the second transistor is of the second conductivity type, and the gate electrode of the first and second transistors is The gate electrode is characterized by having an impurity concentration that exhibits a conductivity substantially similar to that of metal.

A thirteenth invention is the twelfth invention, wherein
The impurity concentration of the channel region is set to be substantially the same as the impurity concentration of the semiconductor substrate.

A fourteenth invention is the twelfth invention, wherein
The impurity concentration of the gate electrode is approximately 10 ⁺¹⁹/ Cm³more than
It is set.

A fifteenth aspect of the invention is a method of manufacturing a semiconductor device, which comprises preparing a semiconductor substrate having a first conductivity type region and separating the first conductivity type region into first and second regions. And forming a conductive film on the semiconductor substrate,
Forming a first gate electrode on the first region and a second gate electrode on the second region by patterning the conductive film; and forming a mask on the second gate electrode. And the first gate electrode and the first gate electrode using the mask and the first gate electrode as a mask.
A second conductive type impurity is implanted into the second region, the first gate electrode having an impurity concentration higher than that of the second gate electrode, and the source region in the first and second regions; And a step of forming a drain region.

A sixteenth invention is the fifteenth invention, wherein
In the step of forming the mask with a width shorter than the width of the second gate electrode in the gate length direction and patterning the conductive film, the first gate electrode is formed, and the second gate electrode and the second gate electrode are formed. A contact region to which a wiring for applying a potential is connected, and a connection portion that connects the contact region and the second gate electrode and has a width shorter than the width of the mask in the gate length direction are formed. There is.

The 17th invention is the same as the 15th invention,
The impurity implantation into the first gate electrode and the first and second regions is characterized in that the impurity concentration is such that the first gate electrode exhibits substantially the same conductivity as a metal.

The eighteenth invention is the seventeenth invention, wherein
The impurity concentration when implanting impurities into the first gate electrode and the first and second regions is set to approximately 10 ⁺¹⁹ / cm ³ or more.

A nineteenth aspect of the present invention is, in a method of manufacturing a semiconductor device, a step of preparing a semiconductor substrate having a first conductivity type region and separating the first conductivity type region into first and second regions. And forming a conductive film on the semiconductor substrate,
Patterning the conductive film to form a first gate electrode on the first region and a second gate electrode on the second region; and a first mask on the first gate electrode. And a second gate electrode and the first and second regions using the first mask and the second gate electrode as a mask, the second gate electrode having substantially the same conductivity as a metal. A second conductivity type impurity is implanted at an impurity concentration of about 1 to form a source region and a drain region in the first and second regions, respectively.
Forming a second mask on the semiconductor substrate, the second mask having an opening having a width shorter than a width of the gate electrode in the gate length direction and exposing an upper surface of the first gate electrode through the opening; Using the mask as a mask, on the first gate electrode,
And a step of implanting an impurity of the first conductivity type at an impurity concentration such that the first gate electrode exhibits conductivity substantially similar to that of metal.

The twentieth invention is the nineteenth invention, wherein
The impurity concentration at which the first gate electrode exhibits conductivity similar to that of metal is set to approximately 10 ⁺¹⁹ / cm ³ or more.

According to the present invention, since the reference voltage generating circuit and the manufacturing method thereof are configured as described above, the work function of the gate electrode of the first transistor and the work function of the gate electrode of the second transistor are Differently, a threshold voltage difference occurs between the first and second transistors. As a result, the reference voltage generating circuit outputs the reference voltage according to the threshold voltage difference.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) FIG.
(B) is a block diagram of a reference voltage generating circuit showing the first embodiment of the present invention, (a) is a circuit configuration diagram, and (b) is a transistor in the same diagram (a). It is a characteristic view of T1 and T2. This reference voltage generation circuit, like the reference voltage generation circuit of FIG. 2, generates a reference voltage based on the difference between the threshold voltages of two transistors. As shown in FIG. It has two different n-channel field effect transistors T1 and T2.

The drain of the transistor T1 is connected to the power supply potential VCC via the constant current source I1, and the source is connected to the ground potential GND. Also, the transistor T2
Has a drain connected to the power supply potential VCC via the constant current source I2, and a source and a gate connected to the ground potential GND.

The drains of the transistors T1 and T2 are connected to the + input terminal and the-input terminal of the operational amplifier OA, respectively. The output side of the operational amplifier OA is connected to the gate of the transistor T1 and the output terminal T.

FIG. 1B is a characteristic diagram of the transistors T1 and T2, in which the horizontal axis represents the gate-source voltage Vgs, and the vertical axis represents the drain current Id. As shown in FIG. 1B, the threshold voltage VT1 of the transistor T1 is +
It is an enhancement type of about 0.3V. The transistor T2 is a depletion type and has a threshold voltage V
T2 is set to about -0.3V, and the ON state is exhibited even when Vgs = 0V.

FIGS. 3A to 3D are views showing the structures of the transistors T1 and T2 in FIG. 1. FIG. 3A is a plan view and FIGS. 3B to 3D are drawings. , The same figure (a)
It is sectional drawing in AA, BB, and CC in the inside.

As shown in FIGS. 3A to 3D, these transistors T1 and T2 are formed on the silicon substrate 1 by L
The channel portions 31, 41 are formed on the channel portions 31, 41 separated by the element isolation region 2 of OCOS.
The p-type impurity concentration of 1 is 10 ⁺¹⁶ to 10 ⁺¹⁹ / cm ³
Has become.

The transistor T1 is formed on the gate oxide film 32 formed on the channel portion 31 of the silicon substrate 1,
For example, the gate electrode 33 is made of polycrystalline silicon and has a gate length (horizontal direction in the figure) of about 5 μm and a gate width (vertical direction in the figure) of about 20 μm. The gate electrode 33 suppresses the n-type impurities to a low concentration of 10 ⁺¹⁴ / cm ³ or less so as to generate conductivity almost similar to that of a semiconductor. On the source and drain sides of the gate electrode 33, an N + region 33 having a width of about 0.25 to 0.45 μm, in which n-type impurities are implanted at a high concentration of 10 ⁺¹⁹ / cm ³ or more, respectively.
a and 33b are formed.

Further, the constricted portion 3 having a short gate length of about 2 μm is formed at both ends of the gate electrode 33 in the width direction.
Contact regions 35a, 35b via 4a, 34b
Is provided. The contact regions 35a and 35b are
For connecting to metal wiring, high concentration (10 ⁺¹⁹ /
(cm ³ or more) n-type impurities are implanted. And
The N + regions 33a, 3 are formed by the constricted portions 34a, 34b.
3b and the contact regions 35a and 35b are not directly connected, but the low-concentration gate electrode 33 is connected to these contact regions 35a and 35b.

Further, the silicon base on both sides of the gate electrode 33 is used.
Plate 1 has a high concentration (10⁺¹⁹/ Cm ³Above) n-type impurity
The source region 36 and the drain region 37 into which the material is implanted are formed.
Is made.

On the other hand, the transistor T2 is made of polycrystalline silicon on the gate oxide film 42 formed on the channel portion 41 of the silicon substrate 1 and has a gate length of about 5 μm and a gate width of about 20 μm. It has an electrode 43. The gate electrode 43 has an n-type impurity concentration of 10 ⁺¹⁹ / cm 3 so as to have conductivity similar to that of a metal.
^It was injected at a high concentration of ³ or more. Gate electrode 43
Contact regions 45a and 45b are provided at both ends in the width direction of the. Further, on the silicon substrate 1 on both sides of the gate electrode 43, a source region 46 and a drain region 47 in which a high concentration n-type impurity is implanted are formed.

With such a structure, the transistor T1
Then, since the impurity concentration in the gate electrode 33 connected to the contact regions 35a and 35b is low, the bottom of the conduction band is raised from the Fermi level by about half the forbidden band width of polycrystalline silicon. The value depends on the impurity concentration in the gate electrode 33, but is usually 0.3 to 0.6 eV. On the other hand, in the transistor T2, the impurity concentration in the gate electrode 43 is so large that the orbits of the electrons of the impurities are degenerated.
The energy at the bottom of the conduction band almost agrees with the Fermi level. Therefore, the work function of the gate electrode is 0.3 to 0.3 for the transistor T1 compared to the transistor T2.
It is increased by 0.6 eV.

The difference in threshold voltage between the two transistors is substantially equal to the difference in work function of the gate when the impurity concentration in the channel portion and the structure of the gate insulating film are the same. Therefore, the difference between the threshold voltages of the transistors T1 and T2 is about half the forbidden band width of silicon, that is, 0.3 to 0.6V.

FIGS. 4A to 4C show the transitions in FIG.
It is process drawing which shows the manufacturing method of star T1, T2. Less than,
A method of manufacturing these transistors T1 and T2 will be described.
It (I) Step 1 As shown in FIG. 4A, the LOC is formed on the silicon substrate 1.
The element isolation region 2 is formed by the OS, and the
Concentration of p-type impurities such as elemental and aluminum at a concentration of 10 ⁺¹⁶~ 1
0⁺¹⁹/ Cm³Channel part 3
1, 41 are formed.

Next, gate oxide films 32 and 42 are formed on the channel portions 31 and 41, and the gate oxide films 32 and 4 are formed.
Polycrystalline silicon, which is a material for the gate electrodes 33 and 43, is deposited on the surface of 2. In vapor deposition of polycrystalline silicon, a material gas to which impurities are not added is used and the impurity concentration is set to 10 ⁺¹⁴ / cm ³ or less.

Further, by photolithography and etching, gate electrodes 33 and 43 having a gate length of 5 μm and a gate width of about 20 μm, and a contact region 3 connected thereto.
5a, 35b, 45a, 45b are formed. The constricted portion 3 having a short gate length of about 2 μm is formed between the gate electrode 33 and the contact regions 35a and 35b.
4a and 34b are formed.

(Ii) Step 2 As shown in FIG. 4B, a resist 38 for a mask is formed on the gate electrode 33. The resist 38 masks the gate electrode 33 so that the n-type impurity is not injected into the gate electrode 33 when the n-type impurity is injected into the source region 36 and the drain region 37 of the transistor T1.

The source region 36 and the drain region 37 are n-thick to the lower side of the gate electrode 33 through the gate oxide film 32.
It is necessary to form so as to have an LDD (Lightly Doped Drain) in which mold impurities are diffused. Therefore, the resist 38 formed on the gate electrode 33 is
You must keep it from the top of 3. If the resist 38 protrudes from the gate electrode 33, this resist 38 will be formed when n-type impurities are implanted.
This is because there is a risk that the LDD will not be formed below the gate electrode 33 due to the interference with the above.

Therefore, the width of the resist 38 is twice as large as the sum of the mask alignment margin of the photolithography when the gate electrode 33 is formed and the mask alignment margin when the resist 38 is formed (for example, for example). , 0.7 μm)
However, it is necessary to make it shorter than the gate length of the gate electrode 33. Further, the resist 38 is formed in the constricted portions 34 a, 3
4b, but not on the contact regions 35a and 35b. Since it is necessary to implant an n-type impurity into the gate electrode 43 of the transistor T2, no resist is formed on this gate electrode 43.

After forming the resist 38, n-type impurities are ion-implanted at a concentration of 10 ⁺¹⁹ / cm ³ or more. Thereby, the source regions 36 and 46 and the drain regions 37 and 47
LDD reaching the lower side of the gate oxide films 32 and 42 is formed on the gate electrode 43 of the transistor T2.
A high-concentration n-type impurity is implanted into the entire area of. The gate electrode 33 of the transistor T1 is kept at a low impurity concentration except for the N + regions 33a and 33b protruding from the resist 36.

(Iii) Step 3 As shown in FIG. 4C, after implanting n-type impurities, the resist 38 is removed and the source regions 36, 46,
Metal contacts MC are formed in the drain regions 37, 47 and the contact regions 35, 45 connected to the gate electrodes 33, 43. As a result, two transistors T1 and T2 having the same impurity concentration in the channel portions 31 and 41 and different impurity concentrations in the gate electrodes 33 and 43 are formed in the same manufacturing process.

Next, the operation of the reference voltage generating circuit of FIG. 1A will be described. Since the transistor T2 is a depletion type and its gate is connected to the ground potential GND, a current Id flows from the power supply potential VCC to the transistor T2 via the constant current source I2 as shown in FIG. 1B. As a result, the voltage e2 corresponding to the current Id is generated at the drain of the transistor T2. Transistor T
The drain voltage e2 of 2 is applied to the-input terminal of the operational amplifier A and compared with the drain voltage e1 of the transistor T1 applied to the + input terminal of the operational amplifier A.

As a result, the voltage Δe corresponding to the difference between the voltages e1 and e2 is output from the output terminal of the operational amplifier A and applied to the gate of the transistor T1. With such a feedback loop, voltage e1 <voltage e2
If so, the voltage Δe is controlled to increase and the current of the transistor T1 increases. If voltage e1> voltage e2, the voltage Δe decreases and the current of the transistor T1 decreases. Then, when the voltage e1 = the voltage e2, the magnitudes of the currents flowing through the transistors T1 and T2 become equal and stabilized. At this time, the voltage Δe output from the operational amplifier A and applied to the gate of the transistor T1 is equal to the threshold voltage VT of the two transistors T1 and T2.
The voltage (VT1-VT2) corresponds to the difference between 1 and VT2.

Threshold voltage VT of transistors T1 and T2
1 and VT2 depend on the impurity concentration in the gate electrode as described above, and these transistors T1 and T2
In, the impurity concentrations in the respective gate electrodes are set to different values. Thereby, the threshold voltages VT1, VT
The voltage Δe corresponding to the threshold voltage difference of 2 is output from the output terminal T as the reference voltage.

As described above, the reference voltage generating circuit of the first embodiment has the following advantages. (1) Since the two transistors T1 and T2 have been subjected to the same channel ion implantation step, even if the ion implantation amount in this implantation step varies, the relative difference in channel impurity concentration between these transistors T1 and T2. Is scarce.

The two transistors T1 and T2 are
The threshold voltage difference between the threshold voltages VT1 and VT2 is generated by changing the impurity concentration in the gate electrode. Further, the impurity concentration of the gate electrode 33 of the transistor T1 is set to a value that is close to an intrinsic semiconductor at a low concentration, and the impurity concentration of the gate electrode 43 of the transistor T2 is set to a value that is close to a metal at a high concentration. Therefore, the temperature dependence of the threshold voltage difference between the two transistors T1 and T2 can be reduced. As a result, it is possible to obtain a reference voltage having little temperature dependency.

(2) The reference voltage output from the reference voltage generating circuit is in the range from half the forbidden band width of the semiconductor to the forbidden band width, and the power supply potential VCC is limited to the same extent as the semiconductor forbidden band width. In some cases, a reference voltage equal to or lower than the power supply potential VCC can be obtained regardless of process variations.

(3) Two transistors T1 and T2
The process for changing the impurity concentration in the gate electrode is
It is only the step of forming the resist 38 on the gate electrode 33 of the transistor T1, and the manufacturing process can be simplified as compared with the structure of the conventional transistors M1 and M2 illustrated in FIG. 2B.

(4) In step 2, the gate electrode 33
The width of the resist 38 formed on the gate electrode 33 is
The gate length of the gate electrode 33 is shorter than the gate length of the gate electrode 33 by twice the sum of the photolithography mask alignment margin when forming the resist and the mask alignment margin when forming the resist 38. Thereby, the LDD in which the n-type impurity is diffused to the lower side of the gate electrode 33 through the gate oxide film 32 can be reliably formed.

(5) In step 2, the gate electrode 33
The width of the resist 38 formed on the gate electrode 33 is
Since the gate length is smaller than the gate length of
Unnecessary N + regions 33a and 33b are formed above. However, the gate electrode 33 and the contact region 35a,
Since the narrowed constricted portions 34a and 34b are provided between the N + regions 33a and 35b, there is no possibility that the N + regions 33a and 33b are directly connected to these contact regions 35a and 35b. N + area 33
It is not affected by a and 33b.

(Second Embodiment) FIGS. 5A and 5B.
2A and 2B are structural views of a transistor showing a second embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line D-D in FIG. . These Figure 5
In (a) and (b), elements common to those in FIG. 3 are designated by common reference numerals.

Transistor 40 in FIGS. 5A and 5B
Is the same as the transistor T2 in FIG. 3, that is, the transistor T2 in FIG. On the other hand, transistor 5
0 corresponds to the transistor T1 in FIG. 3 and is used in place of the transistor T1 in FIG.

As shown in FIGS. 5 (a) and 5 (b), these transistors 40 and 50 are formed on the silicon substrate 1 at L level.
The channel portions 41 and 51 are formed on the channel portions 41 and 51 separated by the element isolation region 2 of OCOS.
The p-type impurity concentration of 1 is 10 ⁺¹⁶ to 10 ⁺¹⁹ / cm ³
Has become.

The transistor 50 is a chip of the silicon substrate 1.
On the gate oxide film 52 formed on the channel portion 51,
For example, a gate length of about 5 μm made of polycrystalline silicon
And a gate electrode 53 having a gate width of about 20 μm
It The gate electrode 53 contains 10 p-type impurities.⁺¹⁹/ Cm
³It is added at the above concentration. Saw for gate electrode 53
N-type on the drain electrode 57 side and the drain electrode 57 side, respectively.
10 impurities⁺¹⁹/ Cm ³Injected at high concentration above
N + regions 53a, 53 having a width of about 0.25 to 0.45 μm
b is formed. Further, in the width direction of the gate electrode 53
There are 10 p-type impurities on both ends.⁺¹⁹/ Cm³At the above concentration
The added contact regions 55a, 55b are provided
There is. Other structures are the same as in FIG.

With such a structure, the transistor 50
Then, since the p-type impurity concentration in the gate electrode 53 is so high that the impurity level degenerates, the bottom of the valence band almost coincides with the Fermi level. On the other hand, in the transistor 40, since the n-type impurity concentration in the gate electrode 43 is so large that the impurities are degenerated, the energy at the bottom of the conduction band substantially matches the Fermi level. Therefore, the work function of the gate is
The transistor 50 has a higher bandgap value. In the case of silicon, its value is 1.2 eV. The difference between the threshold voltages of the two transistors 40 and 50 is
When the impurity concentrations of 1, 51 and the structures of the gate insulating films 42, 52 are the same, the work functions of the gate electrodes 43, 53 substantially match. Therefore, the difference between the threshold voltages of the transistors 40 and 50 is 1.2 V, which is the same as the band gap of silicon.

FIGS. 6A to 6D are process diagrams showing a method of manufacturing the transistor of FIG. Hereinafter, a method of manufacturing these transistors 40 and 50 will be described.

(I) Step 1 As shown in FIG. 6A, LOC is formed on the silicon substrate 1.
The element isolation region 2 is formed by the OS and p is formed in the element formation region.
Type impurities are ion-implanted at a concentration of about 10 ⁺¹⁶ to 10 ⁺¹⁹ / cm ³ to form the channel portions 41 and 51. Next, the gate oxide films 42 and 5 are formed on the channel portions 41 and 51.
2 is formed, and polycrystalline silicon, which is a material for the gate electrodes 43 and 53, is deposited on the surfaces of the gate oxide films 42 and 52. In vapor deposition of polycrystalline silicon, a material gas containing no impurities is used and the impurity concentration is 10 ⁺¹⁴ / cm ^3.
Below.

Further, by photolithography and etching, gate electrodes 43 and 53 having a gate length of 5 μm and a gate width of about 20 μm, and the contact region 4 connected thereto.
5a, 45b, 55a, 55b are formed.

(Ii) Step 2 As shown in FIG. 6B, a resist 58 is formed on the gate electrode 53. This resist 58 is the transistor 5
This is to prevent the n-type impurity from being injected into the gate electrode 53 when the n-type impurity of LDD is injected into the 0 source region 56 and the drain region 57.

Therefore, the width of the resist 58 is twice as large as the sum of the mask alignment margin of the photolithography when forming the gate electrode 53 and the mask alignment margin when forming the resist 58. It is necessary to set the length shorter than the gate length of the gate electrode 53. The resist 58 is not formed on the contact regions 55a and 55b.

The gate electrode 43 of the transistor 40
Since it is necessary to implant an n-type impurity in the above, a resist is not formed on this gate electrode 43.

After forming the resist 58, n-type impurities are ion-implanted at a concentration of 10 ⁺¹⁹ / cm ³ or more. Thereby, the source regions 46 and 56 and the drain regions 47 and 57
LDD is formed in each of the
A high-concentration n-type impurity is implanted into the entire 0 gate electrode 43. The gate electrode 53 of the transistor 50 is
A low impurity concentration is maintained except for the regions 53a and 53b protruding from the resist 56.

(Iii) Step 3 As shown in FIG. 6C, the resist 58 is removed after the implantation of the n-type impurity. Next, the transistor 50
A resist 59 for injecting p-type impurities into the gate electrode 53 is formed. At this time, the width of the window portion 59a provided in the resist 59 is such that the p-type impurity is not injected into the portion other than the gate electrode 53, and the width of the window 59a provided in the resist 59 and the mask alignment allowance when the gate electrode 53 is formed. It is necessary to set the dimension shorter than the gate length of the gate electrode 53 by a dimension twice as large as the sum of the mask alignment margin at that time.

After forming the resist 59, p-type impurities are ion-implanted at a concentration of 10 ⁺¹⁹ / cm ³ or more. As a result, the p-type impurity is injected into the gate electrode 53.

(Iv) Step 4 As shown in FIG. 6D, after the p-type impurities are implanted, the resist 59 is removed and the source regions 46, 56,
Metal contacts MC are formed in the drain regions 47, 57 and the contact regions 45, 55 connected to the gate electrodes 43, 53. As a result, the channel portions have the same impurity concentration, and the gate electrodes 43 and 53 are n-type and p-type, respectively.
The two transistors 40 and 50 that have become the mold are formed in the same manufacturing process.

The operation of the reference voltage generating circuit using the two transistors 40 and 50 thus formed is as follows.
This is as described in the first embodiment.

As described above, the reference voltage generating circuit using the transistor of the second embodiment has the following advantages. (1) Gate electrodes 4 of two transistors 40 and 50
High concentration (10 ⁺¹⁹ / cm ³ or more) of n-type and p-type impurities are added to ³ , 53, respectively, so that the electron orbits of the impurities are degenerated. As a result, the transistor 4
The difference between the threshold voltages of 0 and 50 matches the forbidden band width of the gate electrode material without being affected by the variation in the impurity concentration of the gate electrode. Therefore, by using these transistors 40 and 50, the temperature dependence of the reference voltage generating circuit can be eliminated.

(2) The difference between the threshold voltages of the transistors 40 and 50 is not easily affected by the variation in the impurity concentration of the gate electrode, so that the impurity concentration can be easily controlled in the manufacturing process.

(3) Gate electrode 5 of transistor 50
Resists 58, 59 for adding p-type impurities to
It is necessary to implant impurities twice using
The gate electrode 53 of the transistor 50 is different from that of the first embodiment.
The shape of can be simplified.

The present invention is not limited to the above embodiment, and various modifications can be made. Examples of this modification include the following. (A) The transistors T1 and T2 in FIG.
^Although it has channel portions 31 and 41 in which p-type impurities are ion-implanted at about ⁺¹⁶ to 10 ⁺¹⁹ / cm ³ , the intrinsic semiconductor channel structure in which the impurity element for controlling the threshold voltage is not ion-implanted A transistor may be used.
In this case, the impurity concentration by the use of 10 ⁺¹⁶ / cm ³ or less of the high-resistance insulating layer separating the silicon substrate, a p-type impurity concentration of the channel portion and 10 ⁺¹⁶ / cm ³ or less. Other structures are the same as those in FIG. 3, and the same effect can be obtained. As a result, the ion implantation process for the channel portions 31 and 41 becomes unnecessary.

(B) The reference voltage generating circuit using the n-channel field effect transistor has been described.
The same structure can be achieved by using a channel field effect transistor. In the case of a p-channel field effect transistor, the channel portion impurity is made n-type, and the gate electrode of the transistor T1 is doped with p-type impurity 10 ⁺¹⁴ / c.
It may be added at a concentration of m ³ or less and the gate electrode of the transistor T2 may be added at a concentration that degenerates the p-type impurity. Further, the gate material does not have to be the same material as the channel portion, and may be a different material from the channel portion as long as the gate materials of the two transistors T1 and T2 are the same.

(C) The circuit configuration of the reference voltage generating circuit is
It is not limited to the example illustrated in FIG. Any circuit configuration can be applied as long as the reference voltage can be generated based on the threshold voltage difference between two transistors having different work functions. For example, in FIG.
In the circuit configuration of (a), the reference voltage generating circuit using the transistors T1 and T2 of FIG. 3 may be configured instead of the transistors M1 and M2.

(D) The material forming the transistor is
It is not limited to the exemplified ones. For example, germanium-silicon alloy or the like may be used as the gate electrode material instead of polycrystalline silicon.

[0086]

As described in detail above, according to the first invention, the first and second transistors have the same impurity concentration in the channel portion, the same conductivity type of the impurities in the gate electrode, and The impurity concentration of the gate electrode is different. As a result, the work functions of the gate electrodes of the first and second transistors differ, and a threshold voltage difference occurs. The work function is different from the impurity concentration in the channel portion and has little temperature dependence, so that a stable reference voltage can be obtained. Further, since the gate structures of the two transistors are the same, no complicated process is required for manufacturing.

According to the second invention, the impurity concentrations of the channel portions of the first and second transistors are made equal to the impurity concentrations of the semiconductor substrate, and the impurity concentrations of the gate electrodes are made different. As a result, a stable reference voltage can be obtained as in the first aspect of the invention. Further, since the step of implanting impurities into the channel portion can be omitted, the manufacturing process can be simplified.

According to the third invention, the first transistor
The impurity concentration of the gate electrode of 10^{+1 9}/ Cm³Set up above
The impurity concentration of the gate electrode of the second transistor
10 ⁺¹⁶/ Cm³It is set below. This will
Work function fluctuation due to variation in pure substance concentration is reduced
Therefore, a more stable reference voltage can be obtained.

[0089] According to the fourth invention, the first and second transistors, with equal and impurity concentration of the semiconductor substrate, the impurity concentration of the channel portion, each gate electrode of impurities of different conductivity types, 10 ⁺ It is injected at a concentration of ¹⁹ / cm ³ or more. As a result, the step of implanting impurities into the channel portion can be omitted, so that the manufacturing process can be simplified. Furthermore, the fluctuation of the work function due to the variation of the impurity concentration is reduced, and a more stable reference voltage can be obtained.

According to the fifth invention, the gate electrode of the second transistor is masked with a resist, and the impurity ions are implanted into the gate electrode of the first transistor at the same surface density as that of the source region and the drain region. ing. Thus, impurity ions having different concentrations can be implanted into the first and second transistors by one impurity ion implantation step.

According to the sixth invention, the gate electrode of the second transistor is masked with a resist, and impurity ions are implanted into the gate electrode of the first transistor at the same areal density as that of the source region and the drain region. Impurity ions of a conductivity type different from that of the gate electrode of the first transistor are implanted into only the gate electrode of the second transistor. Thus, the predetermined impurity can be implanted into the first and second transistors by the two impurity ion implantation steps.

According to the seventh aspect of the invention, a narrowed constriction is provided between the gate electrode of the second transistor and the contact region for metal wiring on the gate electrode, and the resist is the second transistor. The gate electrode is formed to have a size smaller than the gate length of the gate electrode by twice the size of the alignment margin of photolithography. As a result, the resist does not protrude from the gate electrode, and the drain region can be diffused to the lower side of the gate electrode through the gate oxide film. Further, since the resist is smaller than the gate electrode, unnecessary impurity ions are implanted on the gate electrode of the second transistor, but the impurity ion region and the contact region can be reliably separated by the constricted portion. .

According to the eighth to fourteenth inventions, the first and second transistors are configured such that the channel portions have the same impurity concentration, the gate electrodes have the same conductivity type, and the gate electrodes have different impurity concentrations. Is configured. As a result, the work functions of the gate electrodes of the first and second transistors differ, and a threshold voltage difference occurs. The work function is different from the impurity concentration in the channel portion and has little temperature dependence, so that a stable reference voltage can be obtained.

According to the fifteenth to twentieth inventions, a mask is formed on the second gate electrode, and the mask and the first gate electrode are used as a mask to cover the first gate electrode and the first and second regions. It has a step of implanting impurities. Accordingly, the first transistor and the second transistor having different gate electrode impurity concentrations can be easily formed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a reference voltage generation circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional reference voltage generation circuit.

FIG. 3 is a diagram showing a structure of transistors T1 and T2 in FIG.

FIG. 4 is a process drawing showing a manufacturing method of transistors T1 and T2 in FIG.

FIG. 5 is a structural diagram of a transistor showing a second embodiment of the present invention.

FIG. 6 is a process drawing showing the manufacturing method of the transistor of FIG.

[Explanation of symbols]

T1, T2, 40, 50 Transistor 1 Silicon substrate 31, 41, 51 Channel parts 32, 42, 52 Gate oxide films 33, 43, 53 Gate electrodes 33a, 33b, 53a, 53b N + regions 34a, 34b Constricted parts 35a, 35b , 45a, 45b, 55a, 55b
Contact regions 36, 46, 56 Source regions 37, 47, 57 Drain regions 38, 58, 59 Resist

Claims (20)

[Claims] 1. A reference voltage generating circuit for generating a reference voltage based on a threshold voltage difference between field effect type first and second transistors having different threshold voltages, wherein the first and second transistors are channel portions. The reference voltage generating circuit is characterized in that the gate electrodes have the same impurity concentration, the gate electrodes have the same conductivity type, and the gate electrodes have different impurity concentrations. 2. A reference voltage generation circuit for generating a reference voltage based on a threshold voltage difference between field effect type first and second transistors having different threshold voltages, wherein the first and second transistors are channel portions. The reference voltage generating circuit is characterized in that the impurity concentration of is equal to that of the semiconductor substrate, the conductivity types of impurities of the gate electrode are the same, and the impurity concentration of the gate electrode is different. 3. The impurity concentration of the gate electrode of the first transistor is set to 10 ⁺¹⁹ / cm ³ or more so that the gate electrode has conductivity similar to that of a metal, and the impurity concentration of the second transistor is The impurity concentration of the gate electrode is
^3. The reference voltage generating circuit according to claim 1, wherein the gate electrode is set to 10 ⁺¹⁶ / cm ³ or less so that the gate electrode has conductivity similar to that of a semiconductor. 4. A reference voltage generating circuit for generating a reference voltage based on a threshold voltage difference between field effect type first and second transistors having different threshold voltages, wherein the first and second transistors are channel portions. ^{Has an} impurity concentration of 10 ⁺¹⁹ / cm ³ so that the impurity concentration of the semiconductor substrate is equal to that of the semiconductor substrate, the conductivity types of the impurities of the gate electrodes are different, and these gate electrodes have almost the same conductivity as metal. A reference voltage generating circuit characterized by being set as described above. 5. A method of manufacturing a reference voltage generating circuit for generating a reference voltage based on a threshold voltage difference between field effect type first and second transistors having different threshold voltages, wherein a gate electrode of the second transistor is provided. A method of manufacturing a reference voltage generating circuit, comprising the step of masking with a resist and implanting impurity ions into the gate electrode of the first transistor at the same areal density as the source region and the drain region. 6. A method of manufacturing a reference voltage generating circuit, which generates a reference voltage based on a threshold voltage difference between field effect type first and second transistors having different threshold voltages, wherein a gate electrode of the second transistor is provided. And forming a first mask having a width shorter than the gate length of the gate electrode, and implanting impurity ions into the gate electrode of the first transistor at the same areal density as the source region and the drain region. A second mask having an opening having a width shorter than the gate length of the gate electrode of the first transistor, and exposing the upper surface of the gate electrode of the first transistor through the opening; The gate electrode of the first
And a step of implanting impurity ions of a conductivity type different from that of the gate electrode of the transistor. 7. A constricted part having a narrow width is provided between the gate electrode of the second transistor and a contact region for forming a metal wiring on the gate electrode, and the resist is the gate of the second transistor. 7. The method of manufacturing a reference voltage generating circuit according to claim 5, wherein the reference voltage generating circuit is formed to have a size smaller than the gate length of the electrode by twice the size of the alignment margin of photolithography. 8. A first conductivity type formed on the semiconductor substrate between the source region and the drain region, and a second conductivity type source region and a drain region formed on the first conductivity type semiconductor substrate. Type channel region and a gate electrode formed on the channel region, respectively, and a semiconductor that generates a reference voltage based on a threshold voltage difference between the first and second transistors. In the device, the impurity concentrations of the channel regions of the first and second transistors are substantially the same, and the gate electrodes of the first and second transistors are both made of a semiconductor material and of the second conductivity type. And the impurity concentration of the gate electrode of the first transistor is higher than the impurity concentration of the gate electrode of the second transistor. Location. 9. The semiconductor device according to claim 8, wherein the impurity concentration of the channel region is substantially the same as the impurity concentration of the semiconductor substrate. 10. The semiconductor device according to claim 8, wherein the impurity concentration of the gate electrode of the first transistor is such that the gate electrode exhibits substantially the same conductivity as a metal, and A semiconductor device characterized in that the impurity concentration of the gate electrode is such that the gate electrode exhibits substantially the same conductivity as a semiconductor. 11. The semiconductor device according to claim 10.
hand, The impurity concentration of the gate electrode of the first transistor is almost
10⁺¹⁹/ Cm³And above, the second transistor
The impurity concentration of the gate electrode is about 10⁺¹⁶/ Cm ³Below
There is a semiconductor device. 12. A source region and a drain region of a second conductivity type formed on a semiconductor substrate of the first conductivity type, and a first conductivity formed on the semiconductor substrate between the source region and the drain region. Type channel region and a gate electrode formed on the channel region, respectively, and a semiconductor that generates a reference voltage based on a threshold voltage difference between the first and second transistors. In the device, the channel regions of the first and second transistors have substantially the same impurity concentration, the gate electrodes of the first and second transistors are made of a semiconductor material, and the gate electrodes of the first transistors are One conductivity type, the gate electrode of the second transistor is of the second conductivity type, and the gate electrodes of the first and second transistors are made of metal. Wherein a has an impurity concentration enough to exhibit similar conductive crucible. 13. The semiconductor device according to claim 12, wherein the impurity concentration of the channel region is substantially the same as the impurity concentration of the semiconductor substrate. 14. The semiconductor device according to claim 12, wherein the impurity concentration of the gate electrode is approximately 10 ⁺¹⁹ / cm ³ or more. 15. A semiconductor substrate having a first conductivity type region is prepared, and the first conductivity type region is formed into first and second regions.
And a conductive film is formed on the semiconductor substrate, and the conductive film is patterned to form a first gate electrode on the first region and a second gate electrode on the second region. Forming a gate electrode respectively, forming a mask on the second gate electrode, using the mask and the first gate electrode as a mask, the first gate electrode and the first and second regions An impurity of a second conductivity type is implanted into the first gate electrode to form a first gate electrode having an impurity concentration higher than that of the second gate electrode, and a source region and a drain region in the first and second regions. A method of manufacturing a semiconductor device, comprising: 16. The method of manufacturing a semiconductor device according to claim 15, wherein the mask has a width shorter than a width of the second gate electrode in the gate length direction, and the step of patterning the conductive film is performed. Forming the first gate electrode, the second gate electrode and the second gate electrode
A contact region to which a wiring for applying a potential to the gate electrode is connected, and a connection portion connecting the contact region and the second gate electrode and having a width shorter than the width of the mask in the gate length direction are formed. A method of manufacturing a semiconductor device, comprising: 17. The method of manufacturing a semiconductor device according to claim 15, wherein the impurity implantation into the first gate electrode and the first and second regions is performed so that the first gate electrode has substantially the same conductivity as a metal. The method for manufacturing a semiconductor device is characterized in that the impurity concentration is such that 18. The method of manufacturing a semiconductor device according to claim 17, wherein the impurity concentration when implanting impurities into the first gate electrode and the first and second regions is approximately 10 ⁺¹⁹ / cm ³ or more. A method of manufacturing a semiconductor device, comprising: 19. A semiconductor substrate having a region of the first conductivity type is prepared, and the regions of the first conductivity type are formed into first and second regions.
And a conductive film is formed on the semiconductor substrate, and the conductive film is patterned to form a first gate electrode on the first region and a second gate electrode on the second region. Forming a gate electrode, forming a first mask on the first gate electrode, and using the first mask and the second gate electrode as masks, the second gate electrode and the first and second gate electrodes, respectively. In the second area,
A step of implanting a second conductivity type impurity at an impurity concentration such that the second gate electrode exhibits substantially the same conductivity as a metal, and forming a source region and a drain region in the first and second regions, respectively. Forming a second mask on the semiconductor substrate, the second mask having an opening having a width shorter than a width of the first gate electrode in the gate length direction and exposing an upper surface of the first gate electrode through the opening. And, using the second mask as a mask, implanting an impurity of the first conductivity type into the first gate electrode at an impurity concentration such that the first gate electrode exhibits substantially the same conductivity as a metal. A method for manufacturing a semiconductor device, comprising: 20. The method of manufacturing a semiconductor device according to claim 19, wherein an impurity concentration at which the first gate electrode exhibits conductivity similar to that of a metal is approximately 10 ⁺¹⁹ / cm ³ or more. And a method for manufacturing a semiconductor device.