JPS6226813A - Formation of resist pattern - Google Patents

Formation of resist pattern

Info

Publication number
JPS6226813A
JPS6226813A JP16537285A JP16537285A JPS6226813A JP S6226813 A JPS6226813 A JP S6226813A JP 16537285 A JP16537285 A JP 16537285A JP 16537285 A JP16537285 A JP 16537285A JP S6226813 A JPS6226813 A JP S6226813A
Authority
JP
Japan
Prior art keywords
resist pattern
pattern
temperature
resist
raised
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16537285A
Other languages
Japanese (ja)
Inventor
Hiroyuki Taniguchi
浩之 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16537285A priority Critical patent/JPS6226813A/en
Publication of JPS6226813A publication Critical patent/JPS6226813A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE:To obtain a good configurational accuracy for the title resist pattern and high resistivity for etching by a method wherein the prescribed pattern is exposed on a photosensitive resist film, and when a resist pattern is going to be formed by hardening after developing, rinsing and drying work is performed, temperature is raised in a step-like manner. CONSTITUTION:A photosensitive photoresist film is coated on the surface of the silicon wafer to be used for manufacture of an IC, and then exposing, developing, washing and drying processes are performed thereon. The silicon wafer 1, wherein a non-hardened resist pattern is formed, is moved to split type hot plates 301-305, and they are moved to the hot plates in the direction as shown by the arrow in the diagram. If the set temperature is raised as going to the downstream of a semiconductor wafer, the semiconductor wafer 1 is moved to the heated region of relatively high temperature from the heated region of relatively low temperature, and the non-hardened pattern on the surface is heated up to a high temperature gradually and hardened. As a result, the final heating temperature can be raised without deterioration of the pattern form, and the formed resist pattern has sufficient resistivity against a reactive ion etching.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はIC等の半導体装置の製造に際し、選択エツチ
ングのマスク或いは不純物のイオン注入に対するマスク
として用いるレジストパターンを形成する方法に関し、
特にその硬化方法の改良に係る。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for forming a resist pattern used as a mask for selective etching or a mask for ion implantation of impurities in the manufacture of semiconductor devices such as ICs.
In particular, it relates to improvements in the curing method.

〔発明の技術的背景〕[Technical background of the invention]

半導体装置を製造する際、写真蝕刻等のマスクに用いる
レジストパターンは次のようにして形成されている。即
ち、半導体ウェハー表面に塗布した感光性レジスト膜に
所定のパターンを露光した後、これを現像し、リンスし
て得た残存パターンを加熱硬化させるものである。この
うち、現像以下の工程は従来第2図に示すようにして行
なわれている。
When manufacturing a semiconductor device, a resist pattern used as a mask in photoetching or the like is formed in the following manner. That is, after a predetermined pattern is exposed to light on a photosensitive resist film applied to the surface of a semiconductor wafer, this is developed, and the remaining pattern obtained by rinsing is heat-cured. Among these steps, the steps following development are conventionally performed as shown in FIG.

第2図において、10はウェハーセンドカセットである
。該カセット10内には露光を終了した半導体ウニハー
ト・・が収容されている。これら半導体ウェハーは一枚
づつ現像装置20内に送られる。そして、スピンナー2
1に固定して回転させ、給液管22から現像液をスプレ
ーして現像を行なう。続いて給液管22からリンス液を
スプレーして洗浄し、更に乾燥空気を送給して乾燥した
後、半導体ウェハー1をホットプレート30上に移され
、該ホットプレート上を所定の速度で移動される。ホッ
トプレート30は全体が120℃〜140℃の一定温度
に加熱されているから、ウェハー表面に残存されたレジ
スト膜は半導体ウェハー1がホシトプレート上を移送さ
れる時間だけ前記所定の温度に加熱される。そして、ホ
ットプレート30の終端に達した半導体ウェハーではレ
ジストパターンの硬化が完了しており、そのままウェハ
ーレシーブカセット40に収容される。
In FIG. 2, 10 is a wafer send cassette. The cassette 10 accommodates a semiconductor sea urchin heart that has been exposed. These semiconductor wafers are fed into the developing device 20 one by one. And spinner 2
1 and rotate it, and spray a developer from the liquid supply pipe 22 to perform development. Subsequently, the rinsing liquid is sprayed from the liquid supply pipe 22 for cleaning, and after drying by supplying dry air, the semiconductor wafer 1 is transferred onto the hot plate 30 and moved on the hot plate at a predetermined speed. be done. Since the entire hot plate 30 is heated to a constant temperature of 120° C. to 140° C., the resist film remaining on the wafer surface is heated to the predetermined temperature for the time period during which the semiconductor wafer 1 is transferred on the hot plate. Ru. The resist pattern of the semiconductor wafer that has reached the end of the hot plate 30 has been completely cured, and is accommodated in the wafer receive cassette 40 as it is.

ところで、選択エツチング等のマスクとして使用するレ
ジストパターンには、パターンの形状精度および硬化度
(エツチングに対する抵抗性)の二つの特性が要求され
る。このうち、パターン精度を向上するためには比較的
低温で硬化させる必要があり、硬化度を向、上するには
比較的高温で硬化させる6畏がある。
By the way, a resist pattern used as a mask for selective etching and the like is required to have two characteristics: pattern shape accuracy and degree of hardening (resistance to etching). Among these, in order to improve pattern accuracy, it is necessary to cure at a relatively low temperature, and in order to improve the degree of curing, it is necessary to cure at a relatively high temperature.

〔背景技術の問題点〕[Problems with background technology]

上記のように、従来のレジスト形成方法では現像により
残存したレジストパターンを硬化する際に一定の温度で
加熱していたため、次のような問題があった。
As described above, in the conventional resist forming method, the resist pattern remaining after development is heated at a constant temperature when curing it, resulting in the following problems.

まず、ホットプレート30の温度を高くしてレジストの
硬化を行なうと、架橋反応が進行して充分な硬度が得ら
れる反面、レジストパターンの形状が崩れてしまう。即
ち、加熱前には第3図(A)のように断面矩形の正常な
形状であったパターン2が、加熱硬化した後には第3図
(8)に示すような蒲鉾型の断面形状2′に変化し、幅
が広がってしまう。その結果、これをマスクに選択エツ
チングを行なうと、エツチング精度が低下する問題を生
じることになる。
First, when the temperature of the hot plate 30 is raised to harden the resist, the crosslinking reaction progresses and sufficient hardness is obtained, but the shape of the resist pattern collapses. That is, before heating, the pattern 2 had a normal rectangular cross-sectional shape as shown in FIG. 3(A), but after heating and curing, the pattern 2 had a semicircular cross-sectional shape 2' as shown in FIG. 3(8). , and the width expands. As a result, if selective etching is performed using this as a mask, a problem arises in that the etching accuracy decreases.

これに対し、ホットプレート30を比較的低温にして加
熱硬化を行なうと、硬化終了時点では第4図(A)のよ
うに正常な断面形状のレジストパターン3が得られる。
On the other hand, if the hot plate 30 is heated at a relatively low temperature for curing, a resist pattern 3 having a normal cross-sectional shape as shown in FIG. 4(A) is obtained at the end of curing.

しかし、このレジストパターン3は硬化が不充分なたあ
エツチング、特に反応性イオンエツチングに対する抵抗
性が低い。このため、反応性イオンエツチングを行なっ
ている間にレジストパターン3は徐々に消耗し、エツチ
ング終了の時点では第4図(B)に示すようにマスク幅
が小さくなってしまい、エツチング精度が劣化してパタ
ーン形状グの寸法11J mが回能になる問題を生じて
いる。
However, since this resist pattern 3 is insufficiently cured, it has low resistance to etching, especially reactive ion etching. For this reason, the resist pattern 3 gradually wears out while performing reactive ion etching, and at the end of the etching, the mask width becomes smaller as shown in FIG. 4(B), and the etching accuracy deteriorates. Therefore, a problem arises in that the dimension of the pattern shape is 11 J m.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、良好な形状
精度とエツチングに対する高い抵抗性とを兼ね備えたレ
ジストパターンを形成する方法を提供しようとするもの
である。
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for forming a resist pattern that has both good shape accuracy and high resistance to etching.

(発明の概要) 本発明によるレジストパターンの形成方法は、半導体ウ
ェハー表面に塗布された感光性レジスト族に所定パター
ンの露光を施し、現像、リンス及び乾燥を行なった後、
残存したレジスト膜を硬化させてレジストパターンを形
成するに際し、温度を段階的に上昇させて前記硬化工程
を実施するようにしたことを特徴とするものである。
(Summary of the Invention) The method for forming a resist pattern according to the present invention involves exposing a photosensitive resist coated on the surface of a semiconductor wafer to light in a predetermined pattern, developing it, rinsing it, and drying it.
The present invention is characterized in that when the remaining resist film is cured to form a resist pattern, the temperature is raised stepwise to carry out the curing step.

このように段階的に温度を加熱して硬化させると、比較
的低温で加熱されている間に一定程度の架橋反応が進行
してパターン形状が固定され、耐熱性も向上する。従っ
て、その後に高温で加熱すれば軟化することなく架橋反
応を完結させることができ、形状精度を維持しつつ高い
エツチング抵抗性をもったレジストパターンを形成する
ことができる。
If the temperature is heated stepwise to cure the pattern in this way, a certain degree of crosslinking reaction will proceed while the pattern is heated at a relatively low temperature, the pattern shape will be fixed, and the heat resistance will also improve. Therefore, by subsequently heating at a high temperature, the crosslinking reaction can be completed without softening, and a resist pattern with high etching resistance can be formed while maintaining shape accuracy.

本発明におけるレジストの硬化工程はどのような加熱手
段を用いて行なってもよいが、ホットプレートを用いて
行なうのが最も好ましい。
The resist curing step in the present invention may be carried out using any heating means, but it is most preferably carried out using a hot plate.

〔発明の実施例〕[Embodiments of the invention]

以下、硬化の手段としてホットプレートによる加熱を用
いた一実施例について説明する。
An example in which heating with a hot plate is used as the curing means will be described below.

まず、IC製造用のシリコンウェハー表面に感光性のフ
ォトレジスト膜を塗布し、従来と同様にして露光、現像
、洗浄および乾燥までを行なう。
First, a photosensitive photoresist film is applied to the surface of a silicon wafer for IC manufacturing, and exposed, developed, washed, and dried in the same manner as before.

こうして未硬化のレジストパターンが形成されたシリコ
ンウェハー1を、第1図に示す分割型のホットプレート
301〜30ジ上に移し、該ホットプレート上を図中矢
印方向に移動させる。
The silicon wafer 1 on which the uncured resist pattern has been formed in this way is transferred onto the split-type hot plates 301 to 30 shown in FIG. 1, and moved on the hot plate in the direction of the arrow in the figure.

ところで、上記分割型のホットプレート301〜305
は夫々独立に温度制御されており、設定温度は下記の通
り半導体ウェハーの下流はど高くなっている。なお、具
体的な設定温度は使用する感光性レジストの種類によっ
て異なる。
By the way, the above-mentioned split type hot plates 301 to 305
The temperature is controlled independently, and the set temperature is higher downstream of the semiconductor wafer as shown below. Note that the specific temperature setting varies depending on the type of photosensitive resist used.

ホットプレート30t  :低温 ホットプレート302 :低中温 ホットプレート303 :中温 ホットプレート304 :中高温 ホットプレート30〈・:高温 従って、半導体ウェハー1は比較的低温の加熱領域から
比較的高温の加熱領域に移動し、表面の未硬化パターン
は徐々に高温で加熱されて硬化される。
Hot plate 30t: Low-temperature hot plate 302: Low-medium temperature hot plate 303: Medium-temperature hot plate 304: Medium-high temperature hot plate 30〈・:High temperature Therefore, the semiconductor wafer 1 moves from a relatively low-temperature heating area to a relatively high-temperature heating area. However, the uncured pattern on the surface is gradually heated to a high temperature and cured.

上記実施例の方法で写真蝕刻用のレジストパターンを形
成したところ、パターン形状の劣化を伴うことなく、最
終加熱温度(ホットプレート30f尋の設定温度)を従
来のホットプレートによる低温硬化に比較して5〜10
℃高くすることができた。
When a resist pattern for photoetching was formed using the method of the above example, the final heating temperature (temperature set at 30 feet on a hot plate) was lower than that of a conventional hot plate at a low temperature. 5-10
It was possible to raise the temperature.

そして、形成されたレジストパターンは反応性イオンエ
ツチングに対しても充分な抵抗性を有し、寸法精度の高
いパターン形状グを行なうことができた。
The formed resist pattern also had sufficient resistance to reactive ion etching, making it possible to form a pattern with high dimensional accuracy.

なお、上記実施例では加熱手段として分割型のホットプ
レートを用いたが、本発明はこれに限定されることなく
、オーブン中で徐々に加熱温度を上昇することにより実
施することも可能である。
Although a split hot plate was used as the heating means in the above embodiment, the present invention is not limited thereto, and may be carried out by gradually increasing the heating temperature in an oven.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明によれば良好な形状R度と
エツチングに対する高い抵抗性とを兼ね備えたレジスト
パターンを形成することができ、写真蝕刻のパターンニ
ング精度を向上して半導体装置の製造歩留を向上できる
等、顕著な効果が得られるものである。
As described in detail above, according to the present invention, it is possible to form a resist pattern that has both a good degree of shape radius and high resistance to etching, and improves the patterning accuracy of photolithography to manufacture semiconductor devices. Remarkable effects such as improved yield can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるレジストパターンの
硬化工程を示す説明図、第2図はレジストパターンを形
成する従来の方法を示す説明図であり、第3図(A)<
8>および第4図(A)(B)はその問題点を示す説明
図である。 1・・・半導体ウェハー、2・・・未硬化のレジストパ
ターン、2′・・・高温硬化により変形したレジストパ
ターン、3・・・低温硬化したレジストパターン、3′
・・・反応性イオンエツチングで消耗したレジストパタ
ーン、10・・・ウェハーセンドカセット、20・・・
現像装置、21・・・スピンナー、22・・・給液管、
30・・・ホットプレート、301〜30ぢ・・・分割
型ホットプレート、40・・・ウェハーレシーブカセッ
ト。
FIG. 1 is an explanatory diagram showing the curing process of a resist pattern in an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a conventional method of forming a resist pattern, and FIG.
8> and FIGS. 4(A) and 4(B) are explanatory diagrams showing the problem. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... Uncured resist pattern, 2'... Resist pattern deformed by high temperature curing, 3... Resist pattern cured at low temperature, 3'
...Resist pattern consumed by reactive ion etching, 10...Wafer send cassette, 20...
Developing device, 21... spinner, 22... liquid supply pipe,
30...Hot plate, 301-30...Divided hot plate, 40...Wafer receive cassette.

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハー表面に塗布された感光性レジスト膜に所
定パターンの露光を施し、現像、リンス及び乾燥を行な
った後、残存したレジスト膜を硬化させてレジストパタ
ーンを形成するに際し、温度を段階的に上昇させて前記
硬化工程を実施するようにしたことを特徴とするレジス
トパターンの形成方法。
After exposing a photosensitive resist film coated on the surface of a semiconductor wafer to a predetermined pattern, developing it, rinsing it, and drying it, the temperature is gradually increased to harden the remaining resist film and form a resist pattern. A method for forming a resist pattern, characterized in that the curing step is performed after the curing process is performed.
JP16537285A 1985-07-26 1985-07-26 Formation of resist pattern Pending JPS6226813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16537285A JPS6226813A (en) 1985-07-26 1985-07-26 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16537285A JPS6226813A (en) 1985-07-26 1985-07-26 Formation of resist pattern

Publications (1)

Publication Number Publication Date
JPS6226813A true JPS6226813A (en) 1987-02-04

Family

ID=15811121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16537285A Pending JPS6226813A (en) 1985-07-26 1985-07-26 Formation of resist pattern

Country Status (1)

Country Link
JP (1) JPS6226813A (en)

Similar Documents

Publication Publication Date Title
TWI478211B (en) Litho-freeze-litho-etch (lfle) double patterning with inline chemical critical dimension slimming
JPS6226813A (en) Formation of resist pattern
US6162591A (en) Photolithography process with gas-phase pretreatment
TW201837622A (en) Baking method
JP2001326153A (en) Method of forming resist pattern
JPH0423425A (en) Manufacture of semiconductor device
JP2000100689A (en) Photolithography method using vapor-phase pretreatment
KR100380274B1 (en) Method for forming etching silicon oxide layer using DUV process
JPS60161621A (en) Manufacture of semiconductor device
JP4328516B2 (en) Resist pattern forming method and heat treatment apparatus
JPH07161619A (en) Method and apparatus for baking semiconductor wafer
CN113759664A (en) Photoetching method suitable for semiconductor discrete device
KR20040005483A (en) Method of forming a photoresist pattern
KR100464654B1 (en) Method for forming contact hole of semiconductor device
JP2002324744A (en) Method for manufacturing semiconductor device
KR100861293B1 (en) Method for fabricating photoresist pattern
JPH0342815A (en) Manufacture of semiconductor integrated circuit
JP2000182940A (en) Method of forming resist pattern
CN118534732A (en) Contour pattern forming process based on photoresist broadening and microscopic contour pattern structure
CN114967374A (en) Wafer developing method
JPS63115337A (en) Processing of photoresist
JPH0689856A (en) Method of forming photoresist pattern
JPH10284398A (en) Developing treatment method and equipment
JPS62113141A (en) Photolithographic method
JPH01137634A (en) Manufacture of semiconductor device