JP2002324744A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technique which can improve uniformity of pattern size of films to be etched between semiconductor chips and in a semiconductor chip. SOLUTION: An exposure baking treatment temperature is changed continuously in a semiconductor substrate by using a baking plate 13 provided with a plurality of heaters 9-12 which can set the respective temperatures independently. Development size distribution of chemical sensitization based positive type resist dependent upon the temperature distribution is formed. Consequently, development size distribution of the chemical sensitization based positive type resist which can cancel size shift distribution in dry etching can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a photolithography technique for forming a predetermined resist pattern on a semiconductor substrate.

[0002]

2. Description of the Related Art In a photolithography process, layout information from a design is transferred to a resist applied on a semiconductor substrate through a photomask or a reticle, and a resist pattern is formed through a development process. The film to be etched formed on the semiconductor substrate using the pattern as a mask is processed.

[0003] The performance required for the etching technique greatly varies depending on the type of the film to be etched and the structure of the semiconductor device, but one of the basic evaluation items is a dimensional conversion difference. This is the difference between the pattern size of the resist pattern as a mask material and the pattern size of the film to be etched, for example, 10% of the pattern size of the resist pattern.
Less than a guideline.

[0004] However, in the future, as the miniaturization of semiconductor devices progresses, stricter requirements for the dimensional conversion difference are expected. Therefore, the present inventor has adopted a method of changing the exposure amount for each exposure shot in the semiconductor substrate as a method of reducing the size conversion difference, thereby achieving uniformity of the pattern size of the film to be etched in the semiconductor substrate. We are considering.

[0005]

However, since the above-described method of changing the exposure amount for each exposure shot is a discontinuous adjustment for each shot, a continuous distribution in the semiconductor substrate is provided as in a variation in dimensional shift. The present inventor has found that the dimensional accuracy within each shot cannot be sufficiently secured in some cases.

An object of the present invention is to provide a technique capable of improving the uniformity of pattern dimensions of a film to be etched between semiconductor chips and within a semiconductor chip.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, a step of applying a chemical amplification type resist to a surface of a film to be etched on a semiconductor substrate and then subjecting the semiconductor substrate to a first bake treatment, a step of exposing the chemical amplification type resist to light, A step of performing a second baking process on the substrate, and a step of performing a developing process on the semiconductor substrate,
In the first baking process or the second baking process, a semiconductor substrate is heated using a bake plate provided with a plurality of heaters each of which can independently set a temperature, so that the semiconductor substrate has a temperature distribution. Thus, the development size distribution of the chemically amplified resist depending on the temperature distribution is obtained.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

A CMOSFE according to one embodiment of the present invention
T (complementary metal oxide semiconductor field
1 to 13 show an example of a method for manufacturing an effect transistor).
Will be described in the order of the steps.

First, as shown in FIG. 1, a semiconductor substrate 1 made of, for example, p ^- type single crystal silicon is prepared, and an element isolation region 2 is formed on a main surface of the semiconductor substrate 1. Semiconductor substrate 1 is formed of, for example, an 8-inch semiconductor wafer. Next, using the patterned photoresist film as a mask, impurities are ion-implanted to form a p-well 3 and an n-well 4. An impurity having a p-type conductivity, for example, boron (B) is ion-implanted into the p-well 3, and an impurity having an n-type conductivity, for example, phosphorus (P) is ion-implanted into the n-well 4. Thereafter, MI is added to each well region.
An impurity for controlling the threshold value of an SFET (metal insulator semiconductor FET) may be ion-implanted.

Next, a silicon oxide film 5 serving as a gate insulating film, a polycrystalline silicon film 6 serving as a gate electrode, and a silicon oxide film 7 serving as a cap insulating film are sequentially deposited to form a laminated film. Gate insulating film 5 can be formed by, for example, a thermal CVD method, and gate electrode 6 is formed by, for example, C
It can be formed by the VD method.

Next, as shown in FIG. 2, after the semiconductor substrate 1 is subjected to a pretreatment for resist coating, spin coating is performed.
A chemically amplified positive resist 8 is applied on the cap insulating film 7 by the ng) method. Chemically amplified resist materials
An acid generator is used as a photosensitive agent, and the acid serves as a catalyst to promote crosslinking and decomposition of the resin in a chain reaction by heating to form a pattern.

Thereafter, in order to volatilize the resist solvent contained in the chemically amplified positive resist 8 immediately after the application and stabilize the photochemical reaction at the time of exposure, the semiconductor substrate 1 is subjected to a pre-bake treatment (first bake treatment). ). Next, after setting the semiconductor substrate 1 in an exposure apparatus together with a predetermined photomask, accurate alignment is performed, and then radiation, for example, ultraviolet rays, an electron beam or a laser beam is irradiated for a certain period of time to print a mask pattern to thereby perform chemical etching. The amplification type positive resist 8 is exposed.

Next, the semiconductor substrate 1 is transferred onto a bake plate 13 having heaters 9 to 12 shown in FIG.
By heating ~ 12, for example, 90-100
An exposure bake process (second bake process) of about ° C. is performed on the semiconductor substrate 1. The temperature of each of the heaters 9 to 12 can be set independently. For example, the heater 9 is arranged at 40 mmΦ, the heater 10 is arranged at 80 mmΦ, the heater 11 is arranged at 120 mmΦ, and the heater 12 is arranged at 160 mmΦ.

The setting of the heating temperature of the heaters 9 to 12 is performed, for example, as follows.

First, a heater 9 to 1 is applied to a semiconductor substrate on which a chemically amplified positive resist is applied and further exposed.
After performing the heat treatment at a constant heating temperature of 2, the developing process is performed, and then the etching target film is processed by dry etching. For example, as shown in FIG.
, Semiconductor chips SC having an exposure shot size of 20 mm □ are arranged in a matrix, and the matrix can be 9 × 9 and the pitch can be 20 mm × 20 mm.

FIG. 5 shows the pattern size of the resist pattern after the development process and the pattern size of the film to be etched after the dry etching in each shot. The horizontal axis is
X at the chip coordinate (5) in the Y direction shown in FIG.
The vertical axis indicates the pattern dimension in the X direction at the chip coordinate (5) in the Y direction. Note that the pattern size in the Y direction shows the same distribution as the pattern size in the X direction. The desired pattern size of the film to be etched after the dry etching is 210 nm. As shown in FIG. 5, the pattern size of the resist pattern after the development process shows a substantially constant size distribution, but the pattern size of the film to be etched after the dry etching is concentrically distributed, and the pattern size of the semiconductor substrate SW It can be seen that the pattern dimension becomes narrower from the center to the periphery.

FIG. 6 shows the distribution in the semiconductor substrate SW of the dimensional conversion difference obtained by subtracting the pattern size of the resist pattern after the development processing from the pattern size of the film to be etched after the dry etching shown in FIG. Note that each shot also has a pattern size according to the distribution in the semiconductor substrate SW, for example, the semiconductor chip S at chip coordinates (9, 5)
Also in C, the pattern dimension becomes narrower toward the periphery of the semiconductor substrate SW.

FIG. 7 shows a pattern size distribution of a resist pattern after development processing in consideration of the size conversion difference shown in FIG. 6 in order to make the pattern size of the film to be etched after dry etching uniform. FIG. 8 shows the relationship between the pattern size of the chemically amplified positive resist and the exposure bake treatment temperature. 7 and 8, the temperature of the heater 9 is set to 98 to make the pattern size of the film to be etched uniform.
° C, the temperature of the heater 10 is 97 ° C, and the temperature of the heater 11 is 9
It can be seen that the temperature of 6 ° C. and the temperature of the heater 12 should be 95 ° C.

After subjecting the semiconductor substrate 1 to the exposure baking process described with reference to FIGS. 5 to 8, a developing solution is dropped on the surface of the semiconductor substrate 1 and filled using the surface tension to develop for a predetermined time. After the treatment, rinsing with pure water and spin drying are continuously performed. Thus, resist patterns 8a and 8b are formed on semiconductor substrate 1, as shown in FIG.
For example, the resist patterns 8a and 8b are located in one semiconductor chip SC, but the resist pattern 8a is located in a region near the center of the semiconductor substrate 1, the resist pattern 8b
Are located in a region near the periphery of the semiconductor substrate 1. Further, the pattern size (Lb) of the resist pattern 8b is formed to be larger than the pattern size (a) of the resist pattern 8a due to the temperature distribution in the exposure baking process.

Next, as shown in FIG. 10, the laminated film (silicon oxide film 7 / polycrystalline silicon film 6 / silicon oxide film 5) is sequentially etched using resist patterns 8a and 8b as a mask. Thus, the gate insulating film 15, the gate electrode 16, and the cap insulating film 17 are formed. Here, the resist patterns 8a and 8 considering the dimensional conversion difference are used.
By forming b, a substantially uniform pattern size of the gate electrode can be obtained.

Next, after removing the resist patterns 8a and 8b, as shown in FIG. 11, a silicon oxide film is deposited on the semiconductor substrate 1 by, for example, a CVD method, and the silicon oxide film is anisotropically etched. Thereby, a sidewall spacer 18 is formed on the side wall of the gate electrode 16. Thereafter, using the photoresist film as a mask, an n-type impurity (for example, phosphorus or arsenic (As)) is ion-implanted into the p-well 3, and n-type impurities are formed on both sides of the gate electrode 16 on the p-well 3.
A type semiconductor region 19 is formed. The n-type semiconductor region 19
It is formed in a self-aligned manner with respect to the gate electrode 16 and the side wall spacer 18 and functions as a source and a drain of the n-channel MISFET. Similarly, using the photoresist film as a mask, p-type impurities (for example, boron fluoride (BF ₂ )) are ion-implanted into n-well 4 to form p-type semiconductor regions 20 on both sides of gate electrode 16 on n-well 4. I do. The p-type semiconductor region 20 is formed in a self-aligned manner with respect to the gate electrode 16 and the sidewall spacer 18, and functions as a source and a drain of the p-channel MISFET.

Next, as shown in FIG.
After a silicon oxide film is deposited thereon by a sputtering method or a CVD method, the silicon oxide film is polished by, for example, a CMP method, so that the surface of the interlayer insulating film 21 is planarized.
To form Next, the interlayer insulating film 21 is etched by using the patterned photoresist film as a mask.
The connection hole 22 is formed. The connection hole 22 is formed in a necessary portion such as on the n-type semiconductor region 19 or the p-type semiconductor region 20.

Next, a titanium nitride film is formed on the entire surface of the semiconductor substrate 1 including the inside of the connection hole 22 by, for example, a CVD method, and a tungsten film for filling the connection hole 22 is formed by, for example, a CVD method. After that, the titanium nitride film and the tungsten film in the region other than the connection hole 22 are removed by, for example, a CMP method, so that the plug 23 is formed inside the connection hole 22.
To form

Subsequently, as shown in FIG. 13, a stopper insulating film 24 is formed on the interlayer insulating film 21 and the plug 23, and further an insulating film 25 for forming a wiring is formed. The stopper insulating film 24 is a film serving as an etching stopper when a groove is formed in the insulating film 25, and is made of a material having an etching selectivity with respect to the insulating film 25. Stopper insulating film 24
Is, for example, a silicon nitride film, and the insulating film 25 is, for example, a silicon oxide film. The stopper insulating film 24
The first wiring layer described below is formed on the insulating film 25. Therefore, the total film thickness is determined by the design film thickness required for the first wiring layer. Next, wiring grooves 26 are formed in predetermined regions of the stopper insulating film 24 and the insulating film 25 by etching using the patterned photoresist film as a mask.
To form

Next, for example, a tungsten film is formed on the entire surface of the semiconductor substrate 1 including the inside of the wiring groove 26. For example, a CVD method is used to form the tungsten film. After that, the tungsten film in the region other than the wiring groove 26 is removed by, for example, the CMP method to form the wiring 27 of the first wiring layer.

Thereafter, although not shown, an upper layer wiring is formed, and the entire surface of the semiconductor substrate 1 is covered with a passivation film, whereby the CMOSFET is substantially completed.

In the present embodiment, the present invention is applied to a CMO
Although the description has been given of the case where the present invention is applied to the exposure bake processing when processing and forming the gate electrode 16 of the SFET, the present invention can also be applied to the prebake processing performed after the application of the chemically amplified positive resist 8.

In this embodiment, a positive resist is used as a chemically amplified resist material. However, a negative resist may be used, and similar effects can be obtained.

As described above, according to the present embodiment, the exposure bake processing temperature can be continuously changed in the semiconductor substrate 1 by using the plurality of heaters 9 to 12, so that the chemical distribution depending on the temperature distribution can be changed. The development dimension distribution of the amplification type positive resist 8 can be obtained. As a result, a developed dimension distribution of the chemically amplified positive resist 8 that can offset the dimension shift distribution in the dry etching is obtained, so that the film to be etched (the silicon oxide film 7 / polycrystalline) between the semiconductor chips and within the semiconductor chips. The uniformity of the pattern size of the silicon film 6 / silicon oxide film 5) can be improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the CMOS
Although the case where the present invention is applied to the process of processing the gate electrode of the FET has been described, the present invention can be applied to the process of processing any semiconductor device, and a similar effect can be obtained.

[0035]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

The uniformity of the pattern size of the film to be etched between and within the semiconductor chips can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a CMOSFET according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a CMOSFET according to an embodiment of the present invention.

FIG. 3 is a top view of a bake plate provided with a heater for heating.

FIG. 4 is a layout view of a semiconductor chip on a semiconductor substrate.

FIG. 5 is a graph showing a pattern size of a resist pattern after development processing and a pattern size of a film to be etched after dry etching in each shot.

FIG. 6 is a graph showing a distribution of a dimensional conversion difference in a semiconductor substrate.

FIG. 7 is a graph showing a pattern size distribution of a resist pattern in consideration of a size conversion difference.

FIG. 8 is a graph showing a relationship between a pattern size of a resist pattern and an exposure bake treatment temperature.

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOSFET according to the embodiment of the present invention;

FIG. 10 is a CMOSFET according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing the semiconductor device.

FIG. 11 is a CMOSFET according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing the semiconductor device.

FIG. 12 is a CMOSFET according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing the semiconductor device.

FIG. 13 is a CMOSFET according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing the semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation region 3 p-well 4 n-well 5 silicon oxide film 6 polycrystalline silicon film 7 silicon oxide film 8 chemically amplified positive resist 8a resist pattern 8b resist pattern 9 heater 10 heater 11 heater 12 heater 13 bake plate Reference Signs List 15 gate insulating film 16 gate electrode 17 cap insulating film 18 sidewall spacer 19 n-type semiconductor region 20 p-type semiconductor region 21 interlayer insulating film 22 connection hole 23 plug 24 stopper insulating film 25 insulating film 26 wiring groove 27 wiring SW semiconductor substrate SC Semiconductor chip

Claims (4)

[Claims] 1. A step of (a) applying a chemically amplified resist to the surface of a film to be etched on a semiconductor substrate and then subjecting the semiconductor substrate to a first bake treatment; and (b) exposing the chemically amplified resist to light. Performing a second bake process on the semiconductor substrate using a bake plate provided with a plurality of heaters; and (d) performing a development process on the semiconductor substrate. A method of manufacturing a semiconductor device, wherein a temperature of each of the plurality of heaters can be independently set. 2. (a) a step of applying a chemically amplified resist on the surface of a film to be etched on a semiconductor substrate and then subjecting the semiconductor substrate to a first bake treatment using a bake plate having a plurality of heaters; And (b) exposing a chemically amplified resist, (c) performing a second baking process on the semiconductor substrate, and (d) performing a developing process on the semiconductor substrate. A method of manufacturing a semiconductor device, wherein a temperature of each of the plurality of heaters can be independently set. 3. A step of (a) applying a chemically amplified resist to the surface of a film to be etched on a semiconductor substrate, and then subjecting the semiconductor substrate to a first baking treatment; and (b) exposing the chemically amplified resist to light. Performing a second bake process on the semiconductor substrate using a bake plate provided with a plurality of heaters; and (d) performing a development process on the semiconductor substrate. A method of manufacturing, wherein a temperature distribution of the chemically amplified resist depending on the temperature distribution is obtained by independently setting temperatures of the plurality of heaters and giving the semiconductor substrate a temperature distribution. A method for manufacturing a semiconductor device, comprising: 4. A step of: (a) applying a chemically amplified resist to the surface of a film to be etched on a semiconductor substrate, and then subjecting the semiconductor substrate to a first bake process using a bake plate having a plurality of heaters. And (b) exposing a chemically amplified resist, (c) performing a second baking process on the semiconductor substrate, and (d) performing a developing process on the semiconductor substrate. A method of manufacturing, wherein a temperature distribution of the chemically amplified resist depending on the temperature distribution is obtained by independently setting temperatures of the plurality of heaters and giving the semiconductor substrate a temperature distribution. A method for manufacturing a semiconductor device, comprising: