JPS6362323A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6362323A JPS6362323A JP20817686A JP20817686A JPS6362323A JP S6362323 A JPS6362323 A JP S6362323A JP 20817686 A JP20817686 A JP 20817686A JP 20817686 A JP20817686 A JP 20817686A JP S6362323 A JPS6362323 A JP S6362323A
- Authority
- JP
- Japan
- Prior art keywords
- baking
- semiconductor device
- immediately
- room temperature
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000000059 patterning Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 210000000744 eyelid Anatomy 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、特に感光性樹脂
を用いるパターン形成プロセスに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a pattern forming process using a photosensitive resin.
半導体装置の製造工程においては、半導体基板（以後、
ウェハーと呼ぶ）に感光性樹脂（以後、フォトレジスト
と呼ぶ）を塗布して、パターン形成を行なう工程がある
。この工程は、数種類の単一工程の組合せにより完結さ
れる。例えば、酸化珪素被膜（以後、酸化膜と呼ぶ）の
パターニングを行なう場合、あらかじめ熱酸化等で、ウ
ェハー上に酸化膜を形成し、次にスピンナー（塗布機）
により、ウェハー上に適量だけ流出したフォトレジスト
を４０００ＲＰＭ ８度の回転速度で一定の厚さにす
る。次に約９００で約１０分間ベークする。次にパター
ン形成しであるガラスマスクを用いて紫外線を部分感光
させる。次に現像液を用いて現像する。次に約１５０７
：’で約３０分間ベークする。このウェハーを７ツ酸系
の溶液に適正時間だけ浸漬する（エツチング〕と、酸化
膜のバターニングがされる。以上のプロセスが従来の感
光性樹脂を用いるバターニング方法である。In the manufacturing process of semiconductor devices, semiconductor substrates (hereinafter referred to as
There is a step in which a photosensitive resin (hereinafter referred to as a photoresist) is coated on a wafer (hereinafter referred to as a wafer) to form a pattern. This process is completed by a combination of several single steps. For example, when patterning a silicon oxide film (hereinafter referred to as oxide film), the oxide film is first formed on the wafer by thermal oxidation, etc., and then a spinner (coating machine) is used to pattern the oxide film.
The photoresist, which has flowed out in an appropriate amount onto the wafer, is rotated at a rotation speed of 4000 RPM and 8 degrees to a constant thickness. Next, bake at about 900 for about 10 minutes. Next, a patterned glass mask is used to partially expose the film to ultraviolet light. Next, it is developed using a developer. Then about 1507
:' Bake for about 30 minutes. The wafer is immersed (etched) in a 7-acid solution for an appropriate amount of time to pattern the oxide film.The above process is a conventional patterning method using a photosensitive resin.
上述した従来の７オトレジストを用いるパターニングプ
ロセスで現像後約１５０Ｃで３０分べ一り後の放置時間
（適正放置時間は２時間以内）が長ずざると、空気中の
水分を吸収して、フォトレジストが膨潤してしまい、次
のエツチングで精確なパターン形成が得られない。従来
では、この欠点を防ぐために、放置時間が長くなってし
まった場合は、再びオーブン（約１５０ｔｌ：’）
に入れて再ベークしていた。この再ベーク作業は作業を
繁雑とし、又パターン形成精度も再ベークを行なわず、
正常放置時間以内に行なった場合に較べて若干劣るとい
う問題がある。In the patterning process using the above-mentioned conventional 7 photoresist, if the exposure time (appropriate exposure time is within 2 hours) after development and baking at approximately 150C for 30 minutes is not long enough, moisture in the air will be absorbed and the photo The resist swells, making it impossible to form a precise pattern in the next etching. Conventionally, in order to prevent this drawback, if the left time is too long, the oven (approx. 150 tl) is heated again.
I put it in and rebaked it. This re-bake work is complicated, and the pattern formation accuracy is also reduced without re-bake.
There is a problem that it is slightly inferior to the case where it is performed within the normal standing time.
本発明の目的は、前記問題点を改善し、放置時間が長く
なっても精確なパターンの形成が得られるようにした半
導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that improves the above-mentioned problems and allows accurate pattern formation even if the exposure time is long.
本発明の構成は、半導体基板に感光性樹脂を塗布し、パ
ターンを形成する半導体装置の製造方法において、前記
感光性樹脂をベークする工程で、前記半導体基板をベー
ク直後に、温度が室温から１５０Ｃの間に定められた保
管容器に入れることを特徴とする。The structure of the present invention is that in a method for manufacturing a semiconductor device in which a photosensitive resin is applied to a semiconductor substrate and a pattern is formed, in the step of baking the photosensitive resin, the temperature is increased from room temperature to 150C immediately after baking the semiconductor substrate. It is characterized by being placed in a storage container specified between
次に本発明を図面を用いて詳細に説明する。 Next, the present invention will be explained in detail using the drawings.
第１図、第２図は本発明の一実施例の半導体装置の製造
方法で使用するベーク用オープン、保管用オープンを示
す模式図でおる。第１図において、ベーク用オーブン１
は、ウェハー３を入れたウェハーホルダ２を有し、電源
５から供給された電力により発熱するヒーター４を備え
ている。この内部１１Ｃ，Ｎｓ ガスが送られる。第２
図における保管用オープン１′は、第１図と構造＃ｉ同
様であるが設定された内部温度等が異なる。FIGS. 1 and 2 are schematic diagrams showing a baking opening and a storage opening used in a method of manufacturing a semiconductor device according to an embodiment of the present invention. In Figure 1, a baking oven 1
has a wafer holder 2 containing a wafer 3, and a heater 4 that generates heat using electric power supplied from a power source 5. This internal 11C,Ns gas is sent. Second
The storage opening 1' in the figure has the same structure #i as in FIG. 1, but the set internal temperature and the like are different.
マス、ウェハー上の酸化膜のパターン形成プロセスから
説明する。あらかじめ熱酸化等でウェハー上に酸化膜を
形成しておく。次にスピンナー（塗布機）Ｋより、ウェ
ハー上に適量の７オトレジストを流出し、４０００ＲＰ
Ｍ の回転速度で１５秒間回転し、一定の厚さにする
。次に約９Ｏｒで１０分間ベークする。次に、パターン
形成しであるガラスをマスクとし、回合露光装置で紫外
線を部分露光させる。次に現像液を用いて現像する。The process of patterning the oxide film on the mass and wafer will be explained. An oxide film is formed on the wafer in advance by thermal oxidation or the like. Next, an appropriate amount of 7-otoresist is poured onto the wafer from a spinner (coating machine) K, and 4000RP is applied.
Rotate at a rotation speed of M for 15 seconds to achieve constant thickness. Next, bake for 10 minutes at about 90 mA. Next, using the patterned glass as a mask, partial exposure to ultraviolet rays is performed using a combination exposure device. Next, it is developed using a developer.
次に第１図に示したベーク用オーブン（１５０Ｃ。Next, the baking oven (150C) shown in FIG.
Ｎｚ１０４／分）Ｋ３０分入れる。終了後、すぐに第２
図に示した保管用オープン（５０Ｃ，Ｎ２１０）７分）
Ｋ保管しておくと、次の作業のエツチングまでの放置許
容時間が、従来の保管用オープンを用いていなかった方
法に較べて、数倍に伸びた。(Nz104/min) Add K30 minutes. Immediately after finishing the second
Open for storage as shown in the figure (50C, N210) 7 minutes)
By storing K, the allowable time for etching before the next operation was extended several times compared to the conventional method that did not use a storage open.
これによって、再ベーク（１５０Ｃ，Ｎｚ １０−６／
分）を行なう頻度が非常に少なくなって、作業能率が向
上した。This allows re-bake (150C, Nz 10-6/
(minutes) has become much less frequent, improving work efficiency.
即ち、本実施例の７オトレジストの現像後のベーク（約
１５０ｔｌｌ’、３０分）後の放置許容時間の拡大 −
方法は、ベーク後、乾燥ガスが流れており、温Ｋが室温
から１５０Ｃの間の一定に設定されている保管容器を利
用するものである。In other words, the allowable leaving time after baking (approximately 150 tll', 30 minutes) after development of the 7 photoresist of this example is expanded.
The method utilizes a storage container in which drying gas is flowing after baking and the temperature K is set constant between room temperature and 150C.
次に本発明の他の実施例の半導体装置の製造方法を説明
する。まず、フォトレジストを用いるバターニング・プ
ロセスで、フォトレジスト塗布後、９０Ｃで１０分間ベ
ークした後、目金露光を行なうが、９０Ｃ，１０分間ベ
ーク後、目金露光までの間の放置許容時間を長くするた
めＩｃ、９０ｃ、１０分間ベーク後に１第２図の保管用
オープンを用いて、３０Ｃ，Ｎｚ ＩＯＡ／分の条件で
保管することにより、放置許容時間が大幅に伸びる。Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described. First, in the buttering process using photoresist, after applying the photoresist, baking at 90C for 10 minutes, and then exposing the eyelid. To increase the length of time, after baking at Ic, 90c, for 10 minutes, using the storage open shown in Figure 2, and storing under the conditions of 30C, Nz IOA/min, the allowable time of storage can be greatly extended.
以上説明したように、本発明によれば、フォトレジスト
のベーク後の放置許容時間が大幅に長くなり、精度が高
く、バラツキの少ない半導体装置が得られ、再ベークを
行なう頻度も非常に少なくなり、作業能率が向上すると
いう効果が得られる。As explained above, according to the present invention, the allowable time for leaving the photoresist after baking is significantly increased, a semiconductor device with high precision and less variation can be obtained, and the frequency of re-baking can be extremely reduced. , the effect of improving work efficiency can be obtained.
第１図、第２図は本発明の一実施例の半導体装置の製造
方法で用いるそれぞれベーク用オープン、保管用オープ
ンを示す模式図である。
１・・・・・・オープン、２・・・・・・ウェハーホル
ダ、３・・・・・・ウェハー、４・・・・・・ヒータ、
５・・・・・・電源。
第１図
第２図FIGS. 1 and 2 are schematic diagrams showing a baking opening and a storage opening, respectively, used in a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1...Open, 2...Wafer holder, 3...Wafer, 4...Heater,
5...Power supply. Figure 1 Figure 2
Claims (1)
半導体装置の製造方法において、前記感光性樹脂をベー
クする工程で、前記半導体基板をベーク直後に、温度が
室温から１５０℃の間に定められた保管容器に入れるこ
とを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which a photosensitive resin is applied to a semiconductor substrate to form a pattern, in the step of baking the photosensitive resin, the temperature is set between room temperature and 150° C. immediately after baking the semiconductor substrate. A method of manufacturing a semiconductor device, the method comprising: placing the semiconductor device in a storage container.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20817686A JPS6362323A (en) | 1986-09-03 | 1986-09-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20817686A JPS6362323A (en) | 1986-09-03 | 1986-09-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6362323A true JPS6362323A (en) | 1988-03-18 |
Family
ID=16551918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20817686A Pending JPS6362323A (en) | 1986-09-03 | 1986-09-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6362323A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04111714A (en) * | 1990-08-30 | 1992-04-13 | Izumo Sangyo Kk | Tap |
| US5516626A (en) * | 1990-04-23 | 1996-05-14 | Tadahiro Ohmi | Resist processing method |
| EP2100683A1 (en) | 2008-03-13 | 2009-09-16 | Mitsubishi Materials Corporation | End mill |
| JP2012206197A (en) * | 2011-03-29 | 2012-10-25 | Mitsubishi Materials Corp | End mill with chip breaker |
-
1986
- 1986-09-03 JP JP20817686A patent/JPS6362323A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5516626A (en) * | 1990-04-23 | 1996-05-14 | Tadahiro Ohmi | Resist processing method |
| JPH04111714A (en) * | 1990-08-30 | 1992-04-13 | Izumo Sangyo Kk | Tap |
| JPH0777693B2 (en) * | 1990-08-30 | 1995-08-23 | 出雲産業株式会社 | Tap |
| EP2100683A1 (en) | 2008-03-13 | 2009-09-16 | Mitsubishi Materials Corporation | End mill |
| JP2012206197A (en) * | 2011-03-29 | 2012-10-25 | Mitsubishi Materials Corp | End mill with chip breaker |
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