JPS62266833A - Fine processing - Google Patents
Fine processingInfo
- Publication number
- JPS62266833A JPS62266833A JP11155886A JP11155886A JPS62266833A JP S62266833 A JPS62266833 A JP S62266833A JP 11155886 A JP11155886 A JP 11155886A JP 11155886 A JP11155886 A JP 11155886A JP S62266833 A JPS62266833 A JP S62266833A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- opening
- semiconductor substrate
- etching
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000001020 plasma etching Methods 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体基板に形成された穴の開口部に傾斜
を形成する微細加工方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microfabrication method for forming an inclination in the opening of a hole formed in a semiconductor substrate.
従来、開口部に傾斜を形成する方法として2ま、レジス
トを用いてバターニングした後、ウェットエッチを行う
方法が行なわれてきた。第2図は従来のこの方法を示す
工程図である。図において、■はレジスト、2は半導体
基板である。Conventionally, as a method of forming a slope in an opening, a method has been used in which patterning is performed using a resist and then wet etching is performed. FIG. 2 is a process diagram showing this conventional method. In the figure, ■ is a resist, and 2 is a semiconductor substrate.
次に、この方法について説明する。まず半導体基板2上
に塗布されたレジスト1をパターニングする(第2図(
a))。次に傾斜をつけるためにエツチング液によりウ
ェットエッチを行う。ウェットエッチは等方性であるた
め第2図(′b)のような形状となる。この後、RI
E (Reactive Ion Etch)により異
方性エッチを行ない、エツチングを完了する(第2図(
C))。エツチング終了後レジストを剥離する(第2図
(d))。Next, this method will be explained. First, the resist 1 coated on the semiconductor substrate 2 is patterned (see Fig. 2).
a)). Next, wet etching is performed using an etching solution to create a slope. Since wet etching is isotropic, the shape is as shown in FIG. 2('b). After this, R.I.
Perform anisotropic etching using E (Reactive Ion Etch) to complete the etching (see Figure 2 (
C)). After etching is completed, the resist is peeled off (FIG. 2(d)).
従来の方法は、ウェットエッチであるため、レジストと
基板の密着性が悪い場合には、エツチング液の浸入によ
り傾斜部分が大きくなりすぎるという問題点があった。Since the conventional method uses wet etching, there is a problem that if the adhesion between the resist and the substrate is poor, the sloped portion becomes too large due to penetration of the etching solution.
この発明は上記のような従来の問題点を解消するために
なされたもので、ウェットニッチを用いないで穴の開口
部に傾斜を形成することのできる微細加工方法を提供す
ることを目的としている。This invention was made to solve the above-mentioned conventional problems, and aims to provide a microfabrication method that can form a slope at the opening of a hole without using a wet niche. .
この発明に係る微細加工方法は、半導体基板上に該基板
に形成された穴に応じた凹部を有するよう液穴を覆って
レジストを塗布し、レジストと半導体基板を同時にプラ
ズマエツチングして、上記穴の開口部に傾斜を形成する
ようにしたものである。In the microfabrication method according to the present invention, a resist is applied on a semiconductor substrate to cover the liquid hole so as to have a recess corresponding to the hole formed in the substrate, and the resist and the semiconductor substrate are simultaneously plasma etched to form the hole. The opening is sloped.
この発明においては、半導体基板上に該基板に形成され
た穴に応じた凹部を存するよう液穴を覆ってレジストを
塗布すると、液穴の開口部においてはレジスト膜厚が薄
くなるので、レジストと半導体基板を同時にプラズマエ
ツチングすることにより、レジストとともに開口部の半
導体基板もエツチング除去されることとなり、開口部に
傾斜を形成することができる。In this invention, when a resist is applied to cover a liquid hole on a semiconductor substrate so that a recess corresponding to the hole formed in the substrate exists, the resist film thickness becomes thinner at the opening of the liquid hole. By performing plasma etching on the semiconductor substrate at the same time, the semiconductor substrate in the opening is etched away together with the resist, making it possible to form a slope in the opening.
以下、この発明の一実施例を図について説明する。第1
図はこの発明の一実施例による微細加工方法を工程順に
示す図であり、図において、1はレジスト、2は半導体
基板である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a diagram showing the process order of a microfabrication method according to an embodiment of the present invention. In the figure, 1 is a resist, and 2 is a semiconductor substrate.
次に、本実施例方法について説明する。まずRT E
(Reactive Ion Etch)を用いて、異
方性エツチングを行い穴を形成した後(第1図(a))
、レジスト1を除去する。そして、第1図(b)に示す
ように、半導体基板2上に上記穴に応じた凹部を有する
よう上記穴を覆ってレジスト1を塗布する。この時、レ
ジスト1の膜厚は、穴の開口部において薄くなる。次に
、第1図(C)に示すように、プラズマによって半導体
基板2とレジスト1が同時にエツチングされるような条
件でエツチングを行う。Next, the method of this embodiment will be explained. First, RT E
After forming a hole by anisotropic etching using (Reactive Ion Etch) (Figure 1(a))
, resist 1 is removed. Then, as shown in FIG. 1(b), a resist 1 is applied on the semiconductor substrate 2 to cover the hole so as to have a recess corresponding to the hole. At this time, the film thickness of the resist 1 becomes thinner at the opening of the hole. Next, as shown in FIG. 1C, etching is performed under conditions such that the semiconductor substrate 2 and the resist 1 are simultaneously etched by plasma.
エツチング終了後レジスト1を除去し、第1図(d)の
ような形状を得る。After etching is completed, the resist 1 is removed to obtain a shape as shown in FIG. 1(d).
このように本実施例方法では、プラズマエツチングによ
り穴の開口部に傾斜を形成するので、従来のウェットエ
ッチの方法に比べ精度良く傾斜を形成でき、またエツチ
ング液関連の設備が不要になる。As described above, in the method of this embodiment, since the slope is formed at the opening of the hole by plasma etching, the slope can be formed more accurately than the conventional wet etching method, and equipment related to etching solution is not required.
なお、上記実施例では、レジストを塗布した例を示した
が、このレジストの代わりにSOG (スピン オング
ラス)を塗布してもよい。In the above embodiment, a resist was applied, but SOG (spin on glass) may be applied instead of this resist.
以上のように、この発明の光発電素子の製造装置によれ
ば、半導体基板上に該基板に形成された穴に応じた凹部
を有するよう液穴を覆ってレジストを塗布し、レジスト
とともに上記基板をプラズマエツチングして開口部に傾
斜を形成するようにしたので、従来のウェットエッチの
方法に比べ精度良く傾斜を形成でき、また、エツチング
液関連の設備が不要になるという効果がある。As described above, according to the photovoltaic device manufacturing apparatus of the present invention, a resist is applied to the semiconductor substrate so as to cover the liquid hole so as to have a concave portion corresponding to the hole formed in the substrate, and the resist is applied to the semiconductor substrate together with the resist. Since the slope is formed in the opening by plasma etching, the slope can be formed more accurately than the conventional wet etching method, and there is also an effect that equipment related to etching liquid is not required.
第1図はこの発明の一実施例による微細加工方法を示す
工程図、第2図は従来の方法を示す工程図である。
図において、1はレジスト、2は半導体基板である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a process diagram showing a microfabrication method according to an embodiment of the present invention, and FIG. 2 is a process diagram showing a conventional method. In the figure, 1 is a resist, and 2 is a semiconductor substrate. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
する方法において、 上記半導体基板上に上記穴に応じた凹部を有するよう上
記穴を覆ってレジストを塗布し、レジストと半導体基板
を同時にエッチングして上記穴の開口部に傾斜を形成す
ることを特徴とする微細加工方法。(1) In a method of forming a slope at the opening of a hole formed in a semiconductor substrate, a resist is applied to cover the hole so as to have a recess corresponding to the hole on the semiconductor substrate, and the resist and the semiconductor substrate are bonded. A microfabrication method characterized by etching simultaneously to form a slope at the opening of the hole.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11155886A JPS62266833A (en) | 1986-05-14 | 1986-05-14 | Fine processing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11155886A JPS62266833A (en) | 1986-05-14 | 1986-05-14 | Fine processing |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62266833A true JPS62266833A (en) | 1987-11-19 |
Family
ID=14564431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11155886A Pending JPS62266833A (en) | 1986-05-14 | 1986-05-14 | Fine processing |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62266833A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS582031A (en) * | 1981-06-29 | 1983-01-07 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-05-14 JP JP11155886A patent/JPS62266833A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS582031A (en) * | 1981-06-29 | 1983-01-07 | Toshiba Corp | Manufacture of semiconductor device |
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