JPS61196541A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61196541A JPS61196541A JP3687985A JP3687985A JPS61196541A JP S61196541 A JPS61196541 A JP S61196541A JP 3687985 A JP3687985 A JP 3687985A JP 3687985 A JP3687985 A JP 3687985A JP S61196541 A JPS61196541 A JP S61196541A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- etching
- wet etching
- resist
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 abstract 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に絶縁膜とく
に酸化膜のエツチング方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of etching an insulating film, particularly an oxide film.
従来、この種のエツチング方法は、レジスト塗布、開孔
後、弗酸系のエツチング液で酸化膜を一度にエツチング
していた。Conventionally, in this type of etching method, after resist coating and hole opening, the oxide film was etched at once with a hydrofluoric acid-based etching solution.
上述した従来のエツチング方法では、第２図に示す様に
、シリコン基板３上の酸化膜２を縦方向にエツチングす
ると共に、開孔部からレジスト１の下部の横方向にもエ
ツチングが進み、酸化膜除去後の上面の開孔面積が大き
くなり、微細加工には大きな欠点となる。一方、第３図
のように等方性エツチングと異方性エツチングとを組み
合せる方法は工程が複雑となる。In the conventional etching method described above, as shown in FIG. 2, the oxide film 2 on the silicon substrate 3 is etched in the vertical direction, and etching also proceeds in the horizontal direction from the opening to the lower part of the resist 1, causing oxidation. After the film is removed, the area of the openings on the top surface increases, which is a major drawback for microfabrication. On the other hand, the method of combining isotropic etching and anisotropic etching as shown in FIG. 3 requires complicated steps.
半導体基板表面に、設けられた酸化膜をレジストで覆い
、任意の場所のレジストを開孔した後、湿式エツチング
にて酸化膜を任意の膜厚までエツチングした後、熱を加
えてレジストを酸化膜に密着させて、再度酸化膜をエツ
チングをする事を特徴としている。Cover the oxide film provided on the surface of the semiconductor substrate with resist, open holes in the resist at desired locations, and then use wet etching to etch the oxide film to the desired thickness. Heat is applied to transform the resist into an oxide film. The feature is that the oxide film is etched again after the oxide film is brought into close contact with the surface.
次に第１図（ａ）〜（Ｃ）を用いて、本発明の実施例を
述べる。第１図（ａ）の如く、シリコン基板３′上の酸
化膜２を７オトレジストをマスクとしてウェットエツチ
ングで酸化膜を約１／２の膜厚を残して、ウェットエツ
チングし、次に第１図山）に示すように、約１８０℃で
約１時間ベークする事によシ、レジストをエツチングし
た表面に密着させる。次に再度ウェットエツチングすれ
ば第１図（Ｃ）の如くの形状のコンタクトが得られる。Next, an embodiment of the present invention will be described using FIGS. 1(a) to 1(C). As shown in FIG. 1(a), the oxide film 2 on the silicon substrate 3' is wet-etched using the photoresist as a mask, leaving about 1/2 the thickness of the oxide film. As shown in Fig. 1, the resist is brought into close contact with the etched surface by baking at about 180°C for about 1 hour. Next, wet etching is performed again to obtain a contact having the shape as shown in FIG. 1(C).
以上説明したように本発明は、ウェットエツチングの途
中に、レジストの酸化膜への密着をさせることによシ、
横方向の広が９の少ないコンタクトが得られる効果があ
る。又、第３図の様に等方性エツチングした後、異方性
のエツチングをすれば、同様に横方向の広が９の少ない
従来技術もあるが、異方性であるドライエツチングをす
ると、コンタクト表面にダメージや付着物が残シ、デバ
イスのリークも発生させていた。が本発明ではウェット
の等方性エツチングが使用できる事より、コンタクト表
面のダメージや付着物を防止する効果もある。As explained above, the present invention enables the resist to adhere to the oxide film during wet etching.
There is an effect that a contact with less lateral spread 9 can be obtained. Also, as shown in FIG. 3, if anisotropic etching is performed after isotropic etching, there is a conventional technique that similarly reduces the lateral spread 9, but if anisotropic dry etching is performed, Damage and deposits remained on the contact surface, which also caused device leaks. However, since wet isotropic etching can be used in the present invention, damage to the contact surface and deposits can be prevented.
【図面の簡単な説明】
第１図は本発明の実施例の各工程での縦断面図、第２図
は従来技術を示す縦断面図、第３図は従来技術の等方性
と異方性エツチングの組み合せ構造の縦断面図である。
ｌ・・・・・・レジスト、２・・・−・・酸化膜、３・
・・・・・シリコン基板。
代理人 弁理士 円 原 昔 ゛°゛ミ°・ゝ、
第１図（勾
第１図（ｂ”１
第１図ＣＧ）
第３図[Brief Description of the Drawings] Figure 1 is a vertical cross-sectional view of each step of the embodiment of the present invention, Figure 2 is a vertical cross-sectional view showing the prior art, and Figure 3 is isotropy and anisotropy of the prior art. FIG. 3 is a longitudinal cross-sectional view of a combination structure of sexual etching. l...Resist, 2...--Oxide film, 3.
...Silicon substrate. Agent Patent Attorney Yen Hara ゛°゛mi°・ゝ、
Figure 1 (gradient Figure 1 (b”1 Figure 1 CG) Figure 3
Claims (1)
の場所のレジストを開孔した後、湿式エッチングにて該
絶縁膜を所定の膜厚までエッチングした後、該レジスト
を該エッチング途中の絶縁膜に密着させる工程を有し、
再び湿式エッチングにて該絶縁膜をエッチングする事を
特徴とする半導体装置の製造方法。After providing an insulating film on the surface of the semiconductor substrate, covering the resist and opening holes in the resist at arbitrary locations, etching the insulating film to a predetermined thickness by wet etching, and then applying the resist to the insulating film that is being etched. It has a process of bringing it into close contact,
A method of manufacturing a semiconductor device, comprising etching the insulating film again by wet etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3687985A JPS61196541A (en) | 1985-02-26 | 1985-02-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3687985A JPS61196541A (en) | 1985-02-26 | 1985-02-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61196541A true JPS61196541A (en) | 1986-08-30 |
Family
ID=12482064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3687985A Pending JPS61196541A (en) | 1985-02-26 | 1985-02-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61196541A (en) |
-
1985
- 1985-02-26 JP JP3687985A patent/JPS61196541A/en active Pending
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