JPS62264663A - Heetro junction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To facilitate the provision of an electrode and a wiring for a minute collector by a structure wherein a collector electrode metal covers the whole surface of the collector and extends to a semi-insulative region adjacent to a hetero junction bipolar transistor. CONSTITUTION:A mask 13 is applied on a prescribed multilayer epitaxial structure 1-6 which is the source of preparation of HBT, and ions are implanted into a peripheral portion 14 to provide a semi-insulative layer. The mask being removed, SiOX 15 and an Al layer 16 are superposed, and the layers 15 and 6 are removed by etching. Covering is made with a photoresist 17, the Al layer 16 is exposed by dry etching, and Al 16 and SiOX 15 are removed by etching to make an indent 18. A collector metal is evaporated and then lifted off to prepare a collector electrode 7-1. After a collector layer 5 is exposed, ion implantation of two stages and annealing are applied, with a dummy collector used as a mask, to provide a semi-insulative region 11 and a highconcentration region 10 of the same type with a base. A base electrode 8-1 is provided on the top of the region 10, and further an electrode for an emitter 3 and wirings 9-1 and 9-2 are provided on a ground layer 2 of high concentration exposed by etching, for completion.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a heterojunction bipolar transistor, which is promising as an ultra-high speed, ultra-high frequency transistor, and a method for manufacturing the same.

Background of the Invention In recent years, heterojunction bipolar transistors, which use a semiconductor material with a larger bandgap than the base as the emitter of the bipolar transistor, have been actively researched as one of the promising candidates for ultra-high speed, ultra-high frequency transistors. .

A conventional heterojunction bipolar transistor and its manufacturing method will be described below with reference to the drawings.

FIGS. 9, 10, and 1) show structural examples of conventional inverted heterojunction bipolar transistors in which the collector is provided on the upper side. 9 and 10 are cross-sectional views of the transistor, and FIG. 1) is a top view of the transistor. FIG. 10 shows a structure in which the base electrode extraction layer is made thicker than the structure shown in FIG. 9 to facilitate the formation of the base electrode and to reduce the base resistance. FIG. 12 and FIG. 13 are FIG. 9.

Figure 10, Figure 1) Figures 9, Figure 10, Figure 1) showing the manufacturing method of the heterojunction bipolar transistor shown in Figure 1).
In the figure and FIGS. 12 and 13, ■ is a substrate, 2 is an underlayer of the same type as the emitter for facilitating the formation of the ohmic electrode of the emitter and mitigating the influence of defects on the substrate;
3 is an emitter or a layer for forming the emitter, 4 is a base or a layer for forming the base, 5 is a collector or a layer for forming the collector, and 6 is for facilitating the formation of the ohmic contact 1 of the collector. Highly 4 degree doped layer with carriers of the same type as the collector for 7-1
is collector electrode metal, 7-2 is collector electrode wiring metal,
8-1 is base electrode metal, 8-2 is base electrode wiring metal, 9-1 is emitter electrode metal, 9-2 is -mitter electrode wiring metal, 10 is a highly doped region of the same type of carrier as the base, 1) is A semi-insulating region 12 is an insulating film formed by ion implantation.

The operation of the heterojunction bipolar transistor configured as described above will be explained.

fT and fm, which are indicators of high-speed operation of a heterojunction bipolar transistor, are expressed as follows.

fT−τE+τB +τC+τcc Here, τB (emitter depletion layer travel time)=TE(C
BC: +CEB “CPB)” τ8 (Base travel time) = WB2 /πDB, τG (Collector depletion layer travel time) = Wo/2VS, τ.. (Collector depletion layer charging time) = (REE+Ro) (CBo+C2o) RB
is the base resistance, Co8 is the base-collector capacitance, CE
B is the base-emitter capacitance, C1B is the base layer stray capacitance, C9° is the collector layer stray capacitance, WB is the base layer thickness, DB is the base layer diffusion coefficient, Wo is the collector depletion layer thickness, vs is the collector layer RF18 is the emitter contact resistance, and Ro is the collector resistance.

In a heterojunction bipolar transistor, a hole leaf (P
(in the case of nP type), the base can be highly doped and the emitter and collector can be lightly doped, contrary to a normal bipolar transistor. This makes it possible to reduce the base resistance R8, which is important for achieving high speed and high frequency transistors. becomes larger. Furthermore, in a bipolar transistor, -1G is 02B, and CCB is a factor C due to doping of the junction capacitance.
8B Cn, h), CoB (n, h), and junction area A
It is expressed as the product of EF3=ACB.

In a heterojunction bipolar transistor, the emitter and collector are lightly doped and the base is highly doped, so CE8 (n, h) and CoB (n, h) depend only on the doping of the emitter and collector, and CB! 3.0CB
becomes as follows.

Therefore, a heterojunction bipolar transistor has a lower cEB than a normal bipolar transistor.

Since CCB becomes small, τ8. τ. . becomes smaller and fT
It is possible to increase the Furthermore, since CEB becomes smaller, it becomes possible to increase fffl in conjunction with the above-described small RB.

Next, a method for manufacturing these heterojunction bipolar transistors will be explained. In the heterojunction bipolar transistor of the type shown in Fig. 9, first, Fig. 12(a) and 1
3 (Fig. 13C) by photolithography and etching from the epitaxially formed multilayer structure material shown in Fig. 81.
b), the highly doped layer 6 and the collector layer 5 or the first
As shown in Fig. 2('b), the highly doped layer 6 is removed to form a portion that will become the collector, and then ion implantation is performed to form the twelfth layer.
(Figure Mountain).

After first forming a semi-insulating region 1 as shown in FIG. 13 (bl), a highly doped region 10 of the same type as the base is formed by ion implantation and activation heat treatment. After this, the 12th
A base mesa is formed as shown in Figure (C) and Figure 13 (C1), and the highly doped layer 2 is exposed for forming an emitter bridge.Then, the entire surface is covered with an insulating film 12 such as 5tyx.
As shown in FIG. 12 (dl) and FIG. 13 (dl, FIG. 12!a+ and FIG. 13(e)', holes are made in the insulating film 12 using photolithography in the electrode formation portions of the collector electrode metal 7- 1. Form emitter electrode metal 9-1 and base electrode metal 8-1.Furthermore, on top of this,
As shown in Figure 3, wiring metals 7-2, 8-2, and 9-2 are formed, and metal wiring is formed as shown in Figure 1).

Problems to be Solved by the Invention However, FIGS. 9, 10, 1) and 1
With the structures and manufacturing methods shown in Figures 2 and 13, there is a process disadvantage in that the smaller the transistor size, the more difficult it is to place electrodes and metal wiring on the collector. In practice, it was nearly impossible to provide electric bridges and metal wiring for small transistors.

The present invention has been developed in view of the above problems, as shown in FIGS. 9 and 10.

1) A new heterojunction bipolar structure in which the emitter electrode metal shown in Figure 7-1 covers the entire upper surface of the emitter and extends into the semi-insulating region adjacent to the heterojunction bipolar transistor. The present invention aims to provide a transistor and a method for manufacturing the same.

Means for Solving the Problems In order to solve the above problems, in the heterojunction bipolar transistor of the present invention, in the epitaxially formed multilayer structure material from which the heterojunction bipolar transistor is formed, the heterojunction bipolar transistor is a step of making the peripheral part of the portion corresponding to the surface semi-insulating, and a step of forming a protective layer of the multilayer structure material;
forming a masking material layer extending from the collector to the semi-insulating region adjacent to the heterojunction bipolar transistor on the protective layer; and etching the protective layer in the periphery using the masking material layer as a mask. and etching the multilayer structure material around the mask material layer to expose the base material layer;
Or at least etching away the high degree doped layer having carriers of the same type as the collector above the collector material layer and exposing the exposed peripheral portion at least up to the base material layer having carriers of the same type as the base material. After converting into a semiconductor material, or converting at least the collector material layer in the peripheral region into a semiconductor material having carriers of the same type as the base, etching away the highly doped layer on top of the collector material layer; After coating the upper part of the multilayer structure material with a photoresist and etching the photoresist by dry etching to locate the beginning of the mask material layer or the protective layer formed on the collector, the mask layer and the protective layer are etched. By etching away the protective layer and using the photoresist left around the collector to deposit collector electrode metal to form a lift-off, the collector electrode covers the entire upper part of the collector and the heterojunction bipolar A new structure of a heterojunction bipolar transistor is realized having an extended structure in a semi-insulating region adjacent to the transistor.

Function: In the manufacturing method of the present invention, the collector electrode is reliably formed even for a collector of very small size, and the collector electrode extends into the semi-insulating region adjacent to the metal or heterojunction bipolar transistor. The alignment becomes extremely easy, and the formation of the collector metal wiring becomes even easier. Therefore, it is possible to solve the problem of the conventional process in which it was extremely difficult to form an electrode on a micro-sized collector and provide metal wiring. This allows the collector area to be reduced. It is extremely effective in increasing the size of Furthermore, in the manufacturing method of the present invention, a dummy collector consisting of a protective film layer and a mask material layer is formed on the collector portion at a stage before forming the collector electrode. Since the process of ion implantation and heat treatment of the implanted layer can be included, there are extremely large process advantages.

EXAMPLE Hereinafter, an example of a heterojunction bipolar transistor of the present invention and a method for manufacturing the same will be described with reference to the drawings.

1, 2, and 3 are structural examples of a heterojunction bipolar transistor according to the present invention, and FIG.

FIG. 2 is a sectional view, and FIG. 3 is a top view. Figures 1 and 2
The figure shows an example in which the present invention is applied to a heterojunction bipolar transistor formed using a combination of etching and ion implantation. FIG. 9 shows a conventional example.

Figure 10, 1) What is the collector electrode metal? -1 extends to the semi-insulating region 14 that covers the entire upper surface of the collector and is adjacent to the heterojunction bipolar transistor, and the metal wiring 7-2 exists only on the semi-insulating region. The difference is that 4 to 8 show a method of manufacturing a collector electrode and collector electrode wiring according to the present invention.

4 and 5 show cross-sectional views in the manufacturing process, and the process (al to tdl in FIG. 4) is also used as a preceding process to the process (ta) to ffl in FIG. 5. Figure 6 is a top view of Figure 4 fat, Figure 7 is Figure 4 fd
Figure 8 shows the top view of Figure 4 (ft+) and Figure 5 (81). First, Figure 4 (al
In the multilayer structure material shown in FIG. 4, Q)1, the part 13 where the heterojunction bipolar transistor will be formed is masked as shown in FIG. 6, and ions are implanted into the peripheral part 14 to form a semi-insulating region. do. Then, the mask 13 is removed and a 5tyx insulating film 15 is formed on the Al multilayer structure material as shown in FIG. 4 (FIG. 4+C). On this, an A1 layer 16 is deposited and lifted off at a portion corresponding to the collector as shown in FIG. 4(d) and FIG. 7. This A1
Using the layer as a mask, the SiOx around the mask is removed by etching, and then the multilayer structure material of the 41st ffl (al) is etched to expose the base forming material layer 4 as shown in FIG. The highly doped layer 6 is exposed as shown in FIG. As shown in Figure 5 (C1), the A1 layer 16 or 5iOxIIJ 15 is cued up. Then, the A12 layer 16 and the Siox layer 15 are removed by etching, and the 41f
A depression 18 is formed as shown in fl or FIG. 5+dl. Next, using the photoresist 17 around the periphery of the recess 18 as a mask, collector electrode metal is deposited and lifted off to form the collector electrode 7 as shown in FIGS. 4(1) and 8 or 5(e) and 8. -1 is formed.

FIG. 1 shows the formation process of the collector electrode described above.

It is used in the fabrication of various types of heterojunction bipolar transistors shown in FIGS. 2 and 3 as follows. In the type shown in Figure 1, fal→(bl→(C1-(d
Following the process of l, (al→(bl→(c
A collector electrode is formed by the process l→(dl -tel -(rl). In the middle of the process, as shown in FIG.
After exposing the base material layer like Al, a semi-insulating region 1) and the same type of height as the base are formed by two-step ion implantation and annealing using the dummy collector formed on the top of the collector as a mask. doped region 10
However, in this case, the formation of the semi-insulating region 1) is not necessarily necessary depending on the purpose.
It is also possible to perform ion implantation after etching away the protective layer, and then expose the base material layer as shown in Figure 5 (al). Afterwards, to form an emitter electrode, the underlying highly doped layer 2 is exposed by etching as shown in FIG. 5 (fl), and an emitter electrode 9-1 is formed.
Furthermore, a base electrode 8-1 is formed. Thereafter, the periphery of the transistor is deeply insulated by ion implantation, or an insulating film is formed and metal wiring is provided thereon to form the structure shown in the top view of FIG. For the type shown in Figure 2, the type shown in Figure 4 (
at −(bl −(cl →(d) −(el →(
f) - (gl - (hl → (1) - (Jl) The emitter electrode is formed by the process. During the process, the collector material layer is exposed as shown in Figure 4 (tel), and then the emitter electrode is formed on the top of the collector. Using the dummy collector as a mask, a semi-insulating region 1) and a highly doped region 10 of the same type as the base are formed by two-step ion implantation and annealing. ) and the formation of the highly doped N region 10 is not absolutely necessary.In this process, the remaining collector-forming semiconductor material layer can be changed to a layer of semiconductor material with carriers of the same type as the base, or the formation of the highly doped N region 10 in FIG. After removing the protective layer by etching, ions are implanted to change the collector material layer to a semiconductor material layer having carriers of the same type as the base, and then the semiconductor material layer is exposed by etching as shown in Figure 4+el. Of course it's good too.

Thereafter, as shown in FIG. 4fj), the underlying highly doped layer 2 is exposed by etching, an emitter electrode 9-1 is formed, and a base electrode 8-1 is further formed.

Thereafter, the periphery of the transistor is deeply insulated by ion implantation or an insulating film is attached and metal wiring is provided, resulting in the structure shown in the top view of FIG.

The Siox I 5 shown in the example serves as a mask during ion implantation and etching of the multilayer structure material, and in the annealing heat treatment after ion implantation, the multilayer structure material layer diffuses the material formed on the top of the SiOx layer. It acts as a protective layer to prevent damage caused by. As the protective layer, in addition to SiOx, an SiNx thin film or an etchant that etches the multilayer structure material or a material that is not attacked by the etching method can be used.

The mask material layer 16 extending from the collector shown in the embodiment to the semi-insulating region adjacent to the transistor is S
It serves as a mask for dry etching a protective layer such as iOx. This layer may be present or absent after it serves as a mask for etching the protective layer, and various metals can be used.

In the example, a structure in which the base electrode is formed on both sides of the collector is used as an example of the structure of the transistor, but it is of course possible to use a type in which the base electrode is formed on one side.In addition, in the example, the emitter electrode is also formed upward. Of course, if the substrate 1 is made of the same type of highly doped material as the emitter, the emitter electrode can also be formed from the underside of the substrate. In addition, in the process of insulating the peripheral area of the transistor (see the mountain in Figure 4), if the base and emitter electrodes are insulated to the extent that the underlying highly doped layer 2 is not insulated, the collector base It is also possible to fabricate a planar heterojunction bipolar transistor in which emitter electrodes are formed on the same plane.

Effects of the Invention As described above, in the present invention, a heterojunction bipolar transistor in which the emitter and the collector are made of a semiconductor material having a larger band gap than at least the base serving as the emitter, and the collector is provided above, is converted into a heterojunction bipolar transistor. In the process of forming the epitaxially formed multilayer structure material, first,
The peripheral part of the part where the heterojunction bipolar transistor is formed is made semi-insulating, then a protective layer is provided on the multilayer structure material, and a layer is formed on the protective layer from the part corresponding to the collector to the semi-insulating region. Forming a stretched layer of mask material, etching away the protective layer at the periphery of the mask material, and etching the multilayer structure material layer at the periphery of the mask material layer to expose the base material layer. Alternatively, the heavily doped layer on top of the collector material layer is etched away and the exposed peripheral area is changed to a semiconductor material having the same type of carrier as the base material, at least up to the base material layer, or the peripheral area is etched away. After changing at least the collector material layer to a semiconductor material layer having carriers of the same type as the base, the entire surface is then covered with a photoresist, and the photoresist is etched by dry etching to form an upper part of the collector. After identifying the beginning of the mask material layer or the protective layer, the mask material layer and the protective layer are etched away, and the photoresist left around the collector is used to remove the semi-insulating layer from the collector. The collector extending to the sexual region is coated with a super metal.

By using a manufacturing method characterized by lift-off formation, the collector electrode metal covers the entire upper part of the collector and extends to a semi-insulating region around the heterojunction bipolar transistor. We fabricate a heterojunction bipolar transistor characterized by:

In the manufacturing method of the present invention, the collector has a structure in which the polar metal is reliably and easily formed over the entire surface of the upper part of the collector and extends to the semi-insulating region in the periphery adjacent to the heterojunction bipolar transistor, which was extremely difficult in the past. This greatly facilitates the process of forming electrodes and wiring on a micro-sized collector. Further, the manufacturing method of the present invention can be used in combination with a process for reducing the emitter area by ion implantation, which is extremely important for manufacturing heterojunction bipolar transistors.

[Brief explanation of drawings]

1 and 2 are process diagrams showing the method for manufacturing a heterojunction bipolar transistor of the present invention, FIG. 6 is a top view of FIG. 4(bl), FIG. 7 is a top view of FIG. 4+d+, and FIG. is Figure 4+l
te+, the top view of FIG. 5, and FIGS. 9 and 10 are process diagrams showing a conventional method for manufacturing a heterojunction bipolar transistor. ■...Substrate, 2...Highly doped underlayer,
3. Old: Emitter or a semiconductor material layer forming an emitter, 4... Base or a semiconductor material layer forming a base, 5... Collector or a semiconductor material layer forming a collector, 6... . . . Highly doped semiconductor material layer to facilitate the ohmic electrode of the collector, 7-
1... Collector electrode metal, 7-2...
Collector electrode wiring metal, 8-1...Base bridge metal, 8-2...Base electrode wiring metal, 9-1
...Emitter electrode metal, ρ-2...Emitter electrode wiring metal, 10...Highly doped region of the same type as the base, 1)... Semi-insulating region by ion implantation, 12... Insulating film, 13...
. . . Mask for insulating the transistor forming part and its surroundings, 14 . . . Insulating region around the transistor,
15...Protective layer, 16...Metal mask layer, 17...Photoresist, 18...
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Claims (5)

[Claims] (1) In the heterojunction bipolar transistor in which at least the emitter of the emitter and collector of the bipolar transistor is made of a semiconductor material with a larger band gap than the base, and the collector is provided on the upper side,
A heterojunction bipolar transistor characterized in that the electrode metal of the collector covers the entire upper surface of the collector and extends into a semi-insulating region adjacent to the heterojunction bipolar transistor. (2) The heterojunction bipolar transistor in which at least the emitter of the emitter and collector of the bipolar transistor is made of a semiconductor material with a larger band gap than the base, and the collector is provided on the upper side. In a manufacturing process of forming an epitaxially formed multilayer structure material comprising at least a large layer of semiconductor material, a layer of semiconductor material for the formation of the base and a layer of semiconductor material for the formation of the collector, the heterojunction bipolar structure of the multilayer structure material a step of making a peripheral part of a portion where a transistor is to be formed semi-insulating; a step of providing a protective layer on the surface of the multilayer structure material; forming a mask material layer extending over an insulating region; removing the protective layer at the periphery of the mask material layer; and etching the multilayer structure material at the periphery of the mask material layer. The base material layer is exposed, or at least a heavily doped layer having carriers of the same type as the collector above the collector material layer is etched away to extend the exposed peripheral portion to at least the base material layer. a highly doped layer on top of the collector material layer after converting it into a semiconductor material having carriers of the same type as the material, or converting at least the collector material layer in the periphery into a semiconductor material having carriers of the same type as the base; coating the upper part of the multilayer structure material with a photoresist, and etching the photoresist by dry etching to locate the beginning of the mask material layer or the protective layer formed on the upper part of the collector. After that, the mask material layer and the protective layer are removed by etching, and the photoresist left around the collector is used to deposit a collector electrode metal to form a lift-off. A method for manufacturing a heterojunction bipolar transistor. (3) A method for manufacturing a heterojunction bipolar transistor according to claim (2), characterized in that a metal is used as the mask material layer. (4) The method for manufacturing a heterojunction bipolar transistor according to claim (2), wherein silicon oxide or silicon nitride is used as the protective layer. (5) A method for manufacturing a heterojunction bipolar transistor according to claim (2), characterized in that a metal is used as the mask material layer, and silicon oxide or silicon nitride is used as the protective layer.