JPS62232160A - Heterojunction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease the contact resistance of a collector electrode remakably in comparison with a conventional value, by coating the entire upper surface of a collector with the collector electrode. CONSTITUTION:A protecting layer is formed on a multilayer structure material, which is formed by epitaxy and is a base material for forming a heterojunction bipolar transistor. A mask material layer is formed at a part corresponding to a collector thereon. with the mask material layer as a mask, the protective layer at the peripheral part is etched away. The multilayer structure material at the peripheral part of the mask is further etched. Thus a base material layer is exposed, or a collector material layer at the peripheral part under the state the collector material layer is attached is converted into a semiconductor region having the same type as a base. Then, the entire surface is coated with photoresist. The photoresist undergoes dry etching. The mask layer or the protecting layer formed on the upper part of the collector is exposed. Thereafter, the mask layer and the protective layer are etched away. By using the photoresist remaining at the peripheral part of the collector, a collector metal electrode is evaporated and formed by liftoff.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a heterojunction bipolar transistor, which is promising as an ultra-high-speed 1MU high-frequency transistor, and a method for manufacturing the same.

Background of the Invention In recent years, heterojunction bipolar transistors, which use a semiconductor material with a larger bandgap than the base as the emitter of the bipolar transistor, have been actively researched as one of the promising candidates for ultra-high speed, ultra-high frequency transistors. .

A conventional heterojunction bipolar transistor and its manufacturing method will be described below with reference to the drawings.

Figure 3 ia1. fbl shows an example of the structure of a normal type heterojunction bipolar transistor with a conventional collector provided on the upper side, and (b) shows an example of a structure in which the emitter area is smaller than that of the fat structure. Fig. 4 shows a method for manufacturing the heterojunction bipolar transistor shown in Fig. 3. In Figs. 3 is an emitter or a layer for forming an emitter;
4 is a layer for forming a base or a base, 5 is a collector or a layer for forming a collector, 6 is a layer for facilitating the formation of an ohmic contact electrode of the collector, 7 is a collector electrode, and 8 is a layer for forming a collector. 9 is an emitter II, 10 is a highly doped region of the same type as the base, and 1) is a semi-insulating region formed by ion implantation. Various materials are used, for example, AIX Ga I
-X A3-Ga AS system, l is semi-insulating G3 A3 % 2 is highly doped n-type GaA, 3 is n-doped AtxG, +-x A, 4 is highly doped p A combination of type G, A, , 5 is n-type doped C; , A, , 6 is highly doped n-type GaA is often used.

The operation of the heterojunction bipolar transistor configured as described above will be explained.

fT and g, which are indicators of high-speed operation of a heterojunction bipolar transistor, are expressed as follows.

Here, 1c is the collector current, WB is the base width, ■36
is the running velocity of electrons in the collector region, i is the collector depletion layer [1), 08B is the capacitance between the emitter and the base, Cc
a is the capacitance between the collector and base, CP is the stray capacitance, W8
is the base width, DB is the electron diffusion coefficient at the base, q and k
is a natural constant and T is the absolute temperature.

In a heterojunction bipolar transistor, the hole leaf from the base to the emitter is suppressed by using a semiconductor material with a larger bandgap than the base as the emitter.Contrary to a normal bipolar transistor, the base is highly doped and the emitter and collector are doped. Can be doped. This makes it possible to reduce the base resistance, which is important for increasing the speed and frequency of the transistor, and increases L. Furthermore, in general, C8, in bipolar transistors.

C08 is the junction capacitance doping factor C8゜(n,
h), C(B (n, h) and junction area A8B.

It is expressed as a product of ACB. In a heterojunction bipolar transistor, the emitter and collector are lightly doped and the base is highly doped, so C86 (n = h)
, Cc a (n, h) depends only on the doping of the emitter and collector, and CE8=CCB is as follows.

CBBχ5・A88, CC8” W” CB ' Therefore, the heterojunction bipolar transistor has a power consumption of 08. compared to a normal bipolar transistor. .

CCB becomes smaller and Lr can be increased. Furthermore, the size of the transistor was reduced to A88゜8. By making 8 smaller, CEFL and co8 can be made smaller, allowing higher speed and higher frequency. Figure 3 +bl is C8
In this case, U3 is made smaller than in the case of FIG. 3 (8).

Next, a method for manufacturing these heterojunction bipolar transistors will be explained. In the type of transistor shown in Fig. 3 fal, the epitaxially formed multilayer structure material shown in Fig. 4 fat is used as a basis for fabricating a heterojunction bipolar transistor by photolithography and etching. A collector mesa is formed as shown in FIG. The base electrode 8 is formed by chemical heat treatment, and then the base electrode 8 is formed by lift-off and alloying heat treatment.In the type of transistor shown in FIG. 3(b), the type shown in FIG. The highly doped layer 6 as shown in FIG. 4 tbl or the highly doped layer 6 and the collector layer 5 as shown in FIG. After forming a portion that will become the collector, a highly doped region 10 of the same type as the base is formed by ion implantation, and then an insulating region 1) of the same type as the base is formed by ion implantation and activation heat treatment.
form. After this, figure 4 (base like GL)
A mesa is formed to expose the emitter electrode forming layer 2.

Below, Fig. 4 fh1. If the collector voltage is as shown in fl)
17. Form emitter electrode 9 and base electrode 8.

Problems to be Solved by the Invention However, with the structure and manufacturing method shown in FIGS. 3 and 4, there is a problem in the process that the smaller the size of the transistor, the more difficult it is to form an electrode on the collector. Therefore, the electrode area had to be made considerably smaller than the collector size. For this reason, as the transistor size becomes smaller, the contact resistance between the electrode and the recirculation, which occupies a smaller proportion of the electrode area, becomes thicker (which becomes an obstacle to increasing the JT), which is a problem.

In view of the above-mentioned problems, the present invention provides a heterojunction bipolar transistor having a new structure in which the collector electrode of FIG. 3 covers the entire upper part of the collector, and a method of constructing the same.

Means for Solving the Problems In order to solve the above-mentioned problems, the heterojunction bipolar transistor of the present invention includes an epitaxy layer on the epitaxially formed multilayer structure material from which the heterojunction bipolar transistor is formed. ! a mask material layer is formed on the protective layer in a portion corresponding to the collector, the protective layer in the peripheral area is etched away using the mask material layer as a mask, and the protective layer in the peripheral area of the mask is etched away. The multilayer structure material is etched to expose the base material layer or, with the collector material layer attached, at least the collector material layer in the peripheral area is converted into a semiconductor region of the same type as the base, and then the entire surface is coated with photoresist. After etching the photoresist for one hour by coating and dry etching to locate the beginning of the mask layer or the protective layer formed on the upper part of the collector, the mask layer and the protective layer are removed by etching, and the area around the collector is etched. By using a manufacturing method characterized by evaporating collector electrode metal using the photoresist left on the part and forming a lift-off in combination with a commonly used method, a new collector electrode that covers the entire upper part of the collector is created. Realizes a heterojunction bipolar transistor structure.

Operation In the heterojunction bipolar transistor of the present invention, since the collector electrode covers the entire upper part of the collector, the contact resistance of the collector electrode can be significantly reduced compared to conventional transistors. For this reason, in heterojunction bipolar transistors manufactured using conventional manufacturing methods, when the collector size becomes smaller, the collector electrode area must be made considerably smaller than the collector, which significantly increases the contact resistance and impedes the speeding up of the transistor. Can solve problems.

Furthermore, in the manufacturing method of the present invention, since the collector electrode is reliably formed on the collector, the process of forming the electrode on the micro-sized collector, which was conventionally required, can be simplified.

EXAMPLE Hereinafter, an example of a heterojunction bipolar transistor of the present invention and a method for manufacturing the same will be described with reference to the drawings.

Figure 1 ta1. +b+, (cl is an example of the structure of the heterojunction bipolar transistor of the present invention. Fig. 1 f
at is an example in which the present invention is applied to a heterojunction bipolar transistor formed by etching, and FIG. The difference from FIG. 3, which shows the conventional example, is that the collector electrode 7 covers the entire upper part of the collector. FIG. 2 shows the manufacturing process of the collector electrode of the present invention. First, the heterojunction Figure 2: Evitakin-formed multilayer structure material that is the basis of bipolar fabrication (5ioX on top of al
The insulating film 12 is formed as shown in Fig. M2 fbl. On top of this, A13 is sporadically deposited and lift-off formed on a portion corresponding to the collector. Using this AlffJ as a mask, S around the mask
, 02 is removed by etching, and the multilayer structure shown in FIG.
The base forming material layer 4 is etched as shown in FIG.
The collector layer is exposed as shown in FIG. 2 (dl) or a part or the whole of the collector layer is exposed as shown in FIG. using the second
As shown in figure ffl or ik+, cue the A/l1) 13 or 5IOx layer 12, then connect the AI layer 13 and S, O□I! 12 is removed by etching to form a recess 15 as shown in FIG. (The collector electrode is formed as shown in ml. The collector electrode forming process described above is used in the production of various types of heterojunction bipolar transistors shown in Fig. 1 as follows. , Fig. 2 ta+
-(bl-(C)→(1)→(31→fkl→(1)→
(Use the process (2) for the collector electrode, then
Apply the process of forming the base mesa and forming the emitter and base electrodes as shown in the figure. Figure 1 (for bl type, Figure 2 tal -(bl -(C1-+l
Collector of l-tel −(kl −+I+−+1ll)? In the middle of the process of forming ili 4%, as shown in Figure 2 (1
) and (J), a commonly used process is applied after (1) to form a semi-insulating region 1) and a highly doped region 10 of the same type as the base by two steps of ion implantation and annealing heat treatment. . Note that this two-step ion implantation and annealing heat treatment process is performed in the post-protection process shown in Figure 2.
! 1) The process in Figure 2 ((b) may be carried out after removing 2, and then etching away 6 and 5 or a part of 6, 5, and 4 and entering the process in Figure 2 01. After that, the base-mesa format, the general process of emitter and base electrode formation is used.For the type of Fig. 1 fc), Fig. 2 (al→fbl −fcl→idl −(
In the middle of the collector snow formation process of el→tri-tgl-fhl, a semi-insulating region +1 and a highly doped region of the same type as the base are formed between fdl and tel by two steps of ion injection and annealing heat treatment after fd+. A commonly used process for forming region 10 of FIG. This process converts the remaining collector-forming material layer to the same type as the base. Note that this two-step ion implantation and annealing heat treatment process is carried out after Fig. 2+c+.
It is also possible to carry out the process after removing 12, and then etching away parts of 6 and 5 or 6, 5 and 4, and then proceeding to the process shown in FIG. Thereafter, a commonly used process for forming the base-mesa type, emitter':rL pole and base electrode is used.

The S, 0x12 shown in the example serves as a mask during ion implantation and etching of the multilayer structure material, and when the multilayer structure material layer is S during the 7-anneal treatment after ion implantation.
, 5I serves as a protective layer to prevent the material formed on top of the Ox layer from being damaged by diffusion.
In addition to Ox, an etchant for etching the 5INx thin film or the multilayer structure or a material that is not attacked by the etching method can be used.

Alflij, which has the same shape as the collector shown in the example, is 5
It serves as a mask for dry etching a protective layer such as IOx. This layer may be present or absent after it serves as a mask for etching the protective layer, and various metals can be used.

In the embodiment, as an example of the structure of the transistor, a structure in which the base bridge is formed on both sides of the collector is used, but of course a type in which the base electrode is formed on one side may also be used.

Furthermore, although the embodiment uses a structure in which the emitter electrode is also taken from above, it is of course possible to take the emitter electrode from the bottom side of the substrate if the substrate l is made of the same type of highly doped material as the emitter. It is about.

In the example, AIX Gal-X As Ga A
This shows an npn-type heterojunction bipolar transistor made of s-based material, and the structure of the epitaxially formed multilayer structure material is the same as in the conventional example. 1 is a semi-insulating Ga substrate, 2 is a highly doped n-type G, A, , 3 is n-type doped A
It z G31-X A3.4 is highly doped p-type G,
A3.5 is n-type doped G, A, 6 is highly doped n-type G
, A is shown, but it goes without saying that the structure and manufacturing method of the present invention can be applied to other materials and pnp types.

Effects of the Invention As described above, in the present invention, a heterojunction bipolar transistor in which at least the emitter and the collector is made of a semiconductor material having a larger band gap than the base, and the collector is provided above, can be fabricated using a heterojunction bipolar transistor. In the process of forming a base multilayer structure material by epitaxy, a protective layer is provided on the multilayer structure material, a mask material layer is formed on the protective layer in a portion corresponding to the collector, and the mask layer The protective layer in the peripheral area is etched away using the mask as a mask, and the multilayer structure material in the peripheral area of the mask is further etched to expose the base material layer, or a small portion of the peripheral area is removed with the collector material layer still attached. In both cases, the collector material layer is replaced with the same type of semiconductor region as the base,
Next, the entire surface is coated with a photoresist, and the photoresist is etched by dry etching to locate the beginning of the mask layer or protective layer formed on the collector, and then the mask and the protective layer are removed by etching. , the collector electrode covers the entire upper part of the collector by using a manufacturing method characterized by depositing collector electrode metal using photoresist left around the collector and forming a lift-off. Fabricate a heterojunction bipolar transistor.

In the manufacturing method of the present invention, the collector electrode can be reliably and easily formed on the entire upper surface of the collector, so that the process of forming the electrode on the micro-sized collector, which has been difficult in the past, becomes extremely easy. Furthermore, the manufacturing method of the present invention can be used in combination with a process for reducing the emitter area by ion implantation, which is extremely important for manufacturing heterojunction bipolar transistors. In addition, in the heterojunction bipolar transistor of the present invention manufactured by the manufacturing method of the present invention, since the collector electrode is formed on the entire upper surface of the collector, the contact resistance of the collector electrode is significantly smaller than that of the conventional one, and the transistor This is extremely effective for speeding up the process. This effect becomes particularly large when manufacturing a micro-sized heterojunction bipolar transistor.

[Brief explanation of drawings]

Figure 3 is a process diagram illustrating a similar method for manufacturing a heterojunction bipolar transistor according to the present invention. 3...Emitter or semiconductor material layer for emitter formation, 4...Base or t-conductor material layer for base formation, 5...Collector or collector formation Semiconductor material 13.6...
...Highly doped 1 conductor layer to facilitate the formation of collector ohmink electrode, 7...Collector electrode, 8...Base electrode, 9...Emitter Electrode, 10... Highly doped region of the same type as the base, 1)... Semi-insulating region by ion implantation,
12... Protective layer, 13... Metal material layer, 14... Photoresist, 15...
dimple. Name of agent Patent attorney Toshio Nakao 1 person 3 --- Lid 4 4 ---↑-Mata 4 5--181ヾ layer B-5- Kazutomo 9 9°-° Lid 'to -, -,, - again eyes iﾛchidoa filial (J<. ii°-+tt*q+* ｰ Q Fig. 4, 5.6--Emi・,? 7-・Electropus

Claims (2)

[Claims] (1) A heterojunction bipolar transistor in which at least the emitter of an emitter and collector is made of a semiconductor material with a larger band gap than the base, and the collector is provided on the upper side, and the transistor has an electrode on the entire upper surface of the collector. A heterojunction bipolar transistor characterized by: (2) A heterojunction bipolar transistor in which at least the emitter of the emitter and the collector is made of a semiconductor material with a larger band gap than the base, and the collector is provided on the upper side, and a semiconductor material layer with a large band gap for forming the emitter; A manufacturing method of forming an epitaxy-formed multilayer structure material including at least a semiconductor material layer for forming the base and a semiconductor material layer for forming the collector, the method comprising forming a protective layer on the multilayer structure material. , forming a mask material layer on the protective layer in a portion corresponding to the collector, removing the protective layer around the masked portion using the mask material layer as a mask, and removing the multilayer layer around the masked portion; Etching the structural material to expose the base material layer, or converting at least the collector material layer in the peripheral region with the collector material layer into a semiconductor region of the same type as the base, and then coating the entire surface with photoresist. Then, the photoresist is etched by dry etching to locate the beginning of the mask layer or protective layer formed on the upper part of the collector, and then the mask layer and the protective layer are removed by etching, leaving no residue around the collector. 1. A method for manufacturing a heterojunction bipolar transistor, comprising depositing a collector electrode metal using a photoresist and forming a lift-off.