JPS62264664A - Hetero junction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To facilitate the provision of an electrode and a wiring for a minute emitter by a structure wherein an emitter electrode metal covers the whole surface of an emitter and extends to a semi-insulative region adjacent to a hetero junction bipolar transistor. CONSTITUTION:A mask 13 is applied on a prescribed multilayer epitaxial structure 1-6 which is the source of preparation of HBT, and ions are implanted into a peripheral portion 14 to provide a semi-insulative layer. The mask being removed, SiOX 15 and Al 16 are superposed, and the layers 15 and 6 are removed by eching. Covering is made with a photoresist 17, Al 16 is exposed by dry etching, and Al 16 and SiOX 15 are removed by etching to make an indent 18. An emitter metal is evaporated and then lifted off to prepare an emitter electrode 7-1. After an emitter layer 5 is exposed, ion implantation of two stages and annealing are applied, with a dummy emitter used as a mask, to provide a semi-insulative layer 11 and a high-concentration region 10 of the same type with a base. A base electrode 8-1 is attached onto the region 10, and further an electrode 9-1 for a collector 3 and a wiring 9-2 for the same use are attached onto a high-concentration ground layer 2 exposed by etching, for completion.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a heterojunction bipolar transistor, which is promising as an ultra-high speed and ultra-high frequency transistor, and a method for manufacturing the same.

Conventional technology In recent years, heterojunction bipolar transistors, which use a semiconductor material with a larger bandgap than the base as the emitter of the bipolar transistor, have been actively researched as one of the promising candidates for ultra-high speed and ultra-high frequency transistors. .

A conventional heterojunction bipolar transistor and its manufacturing method will be described below with reference to the drawings.

FIG. 9, FIG. 10, and FIG. 11 show structural examples of a normal type heterojunction bipolar transistor in which a conventional emitter is provided on the upper side. 9 and 10 are cross-sectional views of the transistor, and FIG. 11 is a top view of the transistor. FIG. 10 shows a structure in which the base electrode layer is made thicker than the structure shown in FIG. 9 to facilitate the formation of the base electrode and to reduce the base resistance. FIG. 42 and FIG. 13 are FIG. 9.

A method of manufacturing the heterojunction bipolar transistor shown in FIGS. 10 and 11 will be described. Figure 9, Figure 10, Figure 11
In the figure, FIGS. 12 and 13, 1 is a substrate, 2 is an underlayer of the same type as the collector for facilitating the formation of the collector ohmic electrode and mitigating the influence of defects on the substrate;
3 is a collector or a layer for forming the collector, 4 is a base or a layer for forming the base, 5 is an emitter or a layer for forming the emitter, and 6 is for facilitating the formation of the ohmic contact electrode of the emitter. Highly doped layer having carriers of the same type as the emitter of 7-1
is the emitter electrode metal, 7-2 is the emitter electrical wiring metal,
8-1 is a base 1 metal, 8-2 is a base electrode wiring metal, 9-1 is a collector electrode metal, 9-2 is a collector electrode wiring metal, 10 is a highly doped region of the same type of carrier as the base, and 11 is an ion A semi-insulating region 12 is an insulating film formed by implantation.

The operation of the heterojunction bipolar transistor configured as described above will be explained.

fT and fm, which are indicators of high-speed operation of a heterojunction bipolar transistor, are expressed as follows.

fT1111τB+τB+τC+τccHere, τB
(Emitter depletion layer travel time) = 18 (C8o+C8B+
C2B), τ8 (base running time) = WB2/πDB
, τG (collector depletion layer running time) = Wc/2V,,
τCC (collector depletion layer charging time) = -(R,, +Ro
) (CBo+c, .), R8 is the base resistance, Cca is the base-collector capacitance, C8B is the base-emitter capacitance, CPa is the base layer stray capacitance, C1° is the collector layer stray capacitance, W8 is the base layer thickness. , DB is the base layer diffusion coefficient, Wo is the thickness of the collector depletion layer, ■, is the collector scanning velocity, REFI is the emitter contact resistance, and Ro is the collector resistance.

In a heterojunction bipolar transistor, hole leakage from the base to the emitter (P
(in the case of nP type), the base can be highly doped and the emitter and collector can be lightly doped, contrary to a normal bipolar transistor. This makes it possible to reduce the base resistance RB, which is important for increasing the speed and frequency of the transistor, thereby increasing Cm. Furthermore, in general, in bipolar transistors, CIl:BSCoB is a factor CF:B (n + h ) −C(B (n
+h), and the junction area AEB''CB.

In a heterojunction bipolar transistor, the emitter and collector are lightly doped and the base is highly doped, so CB 8 (n, h), C, 3 (n+ h) depends only on the doping of the emitter and collector, and C1l: 8.
The CoB is as follows.

Therefore, in a heterojunction bipolar transistor, 088° CoB is smaller than in a normal bipolar transistor, so τ8. As τcc becomes smaller, it becomes possible to increase r and r. Also, since C[EB becomes small, the above-mentioned R
In combination with the fact that B is small, fm can be increased.

Next, a method for manufacturing these heterojunction bipolar transistors will be explained. In the heterojunction bipolar transistor of the type shown in Fig. 9, first, Fig. 12(a) and 1
The epitaxially formed multilayer structure material shown in Fig.
Highly doped layer 6 and emitter layer 5 or first
The highly doped layer 6 is removed as shown in Figure 2 (bl) to form a portion that will become an emitter, and then ion implantation is performed as shown in Figure 12 (bl).

As shown in FIG. 13 (bl), a semi-insulating region 11 is first formed, and then a highly doped region 10 of the same type as the base is formed by ion implantation and activation heat treatment.
13 (C1), a base mesa is formed and the highly doped layer 2 is exposed for forming a collector electrode.Then, the entire surface is covered with an insulating film 12 such as Siox, and as shown in FIG. fd), FIG. 13(d), FIG. 12(el) and FIG. 13(tel), a hole is made in the insulating film 12 using photolithography in the electrode formation part. Emitter electrode metal 7-1. Collector electrode metal. 9-1 and base electrode metal 8-1 are formed.

Furthermore, wiring metals 7-2.8-2.9-2 are formed on this as shown in FIGS. 12 and 13, and metal wiring is formed as shown in FIG. 11.

Problems to be solved by the invention However, FIGS. 9, 10, 11 and 1
With the structure and manufacturing method shown in Figures 2 and 13, there is a problem in the process that the smaller the transistor size, the more difficult it is to place electrodes and metal wiring on the emitter. For small transistors, it was practically impossible to provide electrodes and metal wiring. As the size of the transistor decreases, the proportion of the electrode area decreases, and the contact resistance REIE between the emitter and the electrode increases, which poses a problem in increasing fT.

The present invention has been developed in view of the above problems, as shown in FIGS. 9 and 10.

A new heterojunction bipolar transistor in which the emitter electrode metal shown in FIG. 11 7-1 covers the entire upper surface of the emitter and extends into a semi-insulating region adjacent to the heterojunction bipolar transistor. and its manufacturing method.

Means for Solving the Problems In order to solve the above problems, in the heterojunction bipolar transistor of the present invention, in the epitaxially formed multilayer structure material from which the heterojunction bipolar transistor is formed, the heterojunction bipolar transistor is a step of making the peripheral part of the portion corresponding to the surface semi-insulating, and a step of forming a protective layer of the multilayer structure material;
forming a masking material layer extending from the emitter to the semi-insulating region adjacent to the heterojunction bipolar transistor on the protective layer, and etching away the peripheral portion of the protective layer using the masking material layer as a mask; etching the multilayer structure material around the mask material layer to expose the base material layer;
Alternatively, at least the heavily doped layer having carriers of the same type as the emitter material layer above the emitter material layer is etched away, and the exposed peripheral area is covered with carriers of the same type as the base material up to at least the base material layer. After converting at least the emitter material layer in the peripheral region into a semiconductor material having the same type of carrier as the base, the highly doped layer on top of the emitter material layer is removed by etching. After coating the upper part of the multilayer structure material with a photoresist and etching the photoresist by dry etching to locate the mask material layer or the protective layer formed on the upper part of the emitter, , the mask layer and the protective layer are removed by etching, and the photoresist left around the emitter is used to evaporate emitter electrode metal to form a lift-off, so that the emitter electrode covers the entire upper surface of the emitter. A new structure of a heterojunction bipolar transistor is realized having a structure extending over a semi-insulating region that is covered and adjacent to the heterojunction bipolar transistor.

Operation In the heterojunction bipolar transistor of the present invention, since the emitter electrode covers the entire upper part of the emitter, the contact resistance of the emitter electrode can be significantly reduced compared to the conventional one. For this reason, in heterojunction bipolar transistors manufactured using conventional manufacturing methods, when the emitter size becomes smaller, the emitter electrode area must be made considerably smaller than the emitter, which significantly increases contact resistance and prevents high-speed transistors. This problem can be solved.

Furthermore, the manufacturing method of the present invention reliably forms an emitter electrode even for a very small emitter, and the metal extends into the semi-insulating region adjacent to the heterojunction bipolar transistor. Mask alignment becomes extremely easy and formation of emitter metal wiring becomes extremely easy.

Therefore, it is possible to solve the problem of the conventional process in which it was extremely difficult to form electrodes on microscopic emitters and provide metal wiring. In addition, in the manufacturing method of the present invention, a dummy emitter consisting of a protective film layer and a mask material layer is formed on the emitter portion before forming the emitter electrode, and this is used as a mask to ionize in a self-line manner. Since the process of injection and heat treatment of the injection layer can be included, there are extremely large process advantages.

EXAMPLE Hereinafter, an example of a heterojunction bipolar transistor of the present invention and a method for manufacturing the same will be described with reference to the drawings.

1, 2, and 3 are structural examples of a heterojunction bipolar transistor according to the present invention, and FIG.

FIG. 2 is a sectional view, and FIG. 3 is a top view. Figures 1 and 2
The figure shows an example in which the present invention is applied to a heterojunction bipolar transistor formed using a combination of etching and ion implantation. FIG. 9 shows a conventional example.

10 and 11, emitter electrode metals 7 to 1 cover the entire upper surface of the emitter and extend to a semi-insulating region 14 adjacent to the heterojunction bipolar transistor, and metal wiring 7 to The difference is that 2 exists only on the semi-insulating region. 4 to 8 show a method of manufacturing an emitter electrode and emitter electrode wiring according to the present invention.

FIGS. 4 and 5 show cross-sectional views of the manufacturing process, and the process (al to di) in FIG. 4 is also used as a preceding process to the process in FIG. 5 te) to ff).

Fig. 6 is a top view of Fig. 4 ta+, Fig. 7 is a top view of Fig. 4 (di
8 shows the top views of FIG. 4 (il) and FIG. 5(e). First, the epitaxy shown in FIG. In the multilayer structure material, a portion 1 forming a heterojunction bipolar transistor as shown in FIG.
3 is masked as shown in FIG. 6, and ions are implanted into the peripheral portion 14 to form a semi-insulating region.

Next, the mask 13 is removed, and an Siox insulating film 15 is formed on the multilayer structure material of FIG. 4 (al) as shown in FIG. 4(e).
Layer 16 is deposited and lifted off as shown in FIGS. 4(d) and 7. Using this A1 layer as a mask, the SiOx around the mask was removed by etching, and further, as shown in FIG.
Either the base forming material layer 4 is exposed as shown in FIG. 5 (al) by etching the multilayer structure material of FIG. The entire surface is coated with a photoresist 17 as shown in FIG. 1fl or FIG. I do,
Next, the A1 layer 16 and the 5iOxlS layer are removed by etching, and as shown in FIG. 4 (hl) or FIG.
form. Then, using the photoresist 17 around the recess 18 as a mask, emitter electrode metal is vapor deposited and lifted off to form the emitter electrode 7- as shown in FIGS. 4(i) and 8 or 5(e) and 8. Form 1.

FIG. 1 shows the formation process of the emitter electrode described above.

It is used in the fabrication of various types of heterojunction bipolar transistors shown in FIGS. 2 and 3 as follows. In the type shown in Fig. 1, fat→fbl -te+-(
Following the process of dl, (al → mountain) → (C
1- Form an emitter electrode by the process of (dl→(el→(f)).
After exposing the base material layer as shown in FIG. 2, a semi-insulating region 11 and a highly doped region of the same type as the base are formed by two-step ion implantation and annealing using the dummy emitter formed on the emitter as a mask. However, in this case, the formation of the semi-insulating region 11 is not necessarily required depending on the purpose. It is also possible to perform ion implantation after etching away the protective layer after FIG. 4 1fl, and then expose the base material layer as shown in FIG. 5 (al).

After the emitter electrode is formed through the process shown in FIG. 5 tel, the underlying highly doped layer 2 is exposed by etching as shown in FIG. 4 1fl to form the collector electrode 9-1. , further base electrode 8-
Form 1. Thereafter, the periphery of the transistor is deeply insulated by ion implantation, or an insulating film is formed and metal wiring is provided thereon to form the structure shown in the top view of FIG.

In the type shown in Fig. 2, (al - (bl - (
C1-(dl-(el-(fl-1g'1→(h
An emitter electrode is formed by the process l→(1)-(Jl. During the process, the emitter material layer is exposed as shown in Figure 4 tel, and then the dummy emitter formed on the top of the emitter is used as a mask. Then, a semi-insulating region 11 and a highly doped region 10 of the same type as the base are formed by two-step ion implantation and annealing heat treatment. However, depending on the purpose, the formation of the semi-insulating region 11 and highly doped region 1o may not necessarily be This process does not require that the remaining emitter-forming semiconductor material layer be converted into a semiconductor material layer with carriers of the same type as the base, or
After removing the protective layer by etching after 1fl of FIG. 4, ions are implanted to change the emitter material layer to a semiconductor material layer having carriers of the same type as the base, and then the semiconductor is etched as shown in 1fl of FIG. Of course, the material layer may be exposed. Thereafter, as shown in FIG. 4 1fl, the underlying highly doped layer 2 is exposed by etching, a collector electrode 9-1 is formed, and a base electrode 8-1 is further formed. Thereafter, the periphery of the transistor is deeply insulated by ion implantation, or an insulating film is attached and metal wiring is provided, resulting in the structure shown in the top view of FIG.

The 5iOx15 shown in the example serves as a mask for etching the multilayer structure material during ion implantation, and during annealing heat treatment after ion implantation, the multilayer structure material layer is damaged by diffusion of the material formed on top of the SiOx layer. It acts as a protective layer to prevent As the protective layer, in addition to SiOx, a material that is not attacked by an etchant or an etching method for etching the SiNx thin film or the multilayer structure material can be used.

The mask material layer 16 extending from the emitter to the semi-insulating region adjacent to the transistor shown in the embodiment is S
This layer serves as a mask for dry etching a protective layer such as iox, and can be made of various metals as it may be present or absent after it serves as a mask for etching the protective layer. be able to.

In the embodiment, a structure in which the base electrode is formed on both sides of the emitter is used as an example of the structure of the transistor, but of course a type in which the base electrode is formed on one side of the emitter may also be used. Furthermore, in the embodiment, a structure is used in which the collector electrode is also taken from above, but if the substrate 1 is made of the same type of highly doped material as the collector, the collector electrode can also be taken from the bottom of the substrate. Of course. In addition, in the process of insulating the peripheral area of the transistor (at the stage shown in Fig. 4 (bl),
Also between the base and collector electrodes, if the underlying highly doped layer 2 is insulated to the extent that it is not insulated, the emitter
It is also possible to fabricate a planar heterojunction bipolar transistor in which the base and collector electrodes are formed on the same plane.

Effects of the Invention As described above, in the present invention, a heterojunction bipolar transistor in which the emitter and the collector are made of a semiconductor material having a larger band gap than at least the base serving as the emitter, and the emitter is provided above, is converted into a heterojunction bipolar transistor. In the process of forming the epitaxially formed multilayer structure material, first,
The peripheral part of the part where the heterojunction bipolar transistor is to be formed is made semi-insulating, then a protective layer is provided on the multilayer structure material, and a layer is formed on the protective layer from the part corresponding to the emitter to the semi-insulating region. Forming a stretched layer of mask material, etching away the protective layer at the periphery of the mask material, and etching the multilayer structure material layer at the periphery of the mask material layer to expose the base material layer. Alternatively, the heavily doped layer above the emitter material layer is etched away and the exposed peripheral area is changed to a semiconductor material having the same type of carrier as the base material, at least up to the base material layer, or the peripheral area is etched away. The mask material is formed on the emitter by changing at least the emitter material layer to a semiconductor material layer having carriers of the same type as the base, then covering the entire surface with a photoresist, and etching the photoresist by dry etching. After locating the layer or protective layer, the masking material layer and the protective layer are etched away, and the emitter is extended from the emitter to the semi-insulating region using the photoresist left around the emitter. Deposit electrode metal.

By using a manufacturing method characterized by lift-off formation, the emitter electrode metal covers the entire upper part of the emitter and extends to a semi-insulating region around the heterojunction bipolar transistor. We fabricate a heterojunction bipolar transistor characterized by:

In the manufacturing method of the present invention, the emitter electrode metal is reliably and easily formed over the entire surface of the upper part of the emitter, and has a structure extending to the semi-insulating region in the periphery adjacent to the heterojunction bipolar transistor, which was extremely difficult in the past. The process of forming electrodes and wiring for micro-sized emitters becomes significantly easier. Furthermore, the manufacturing method of the present invention can be used in conjunction with a collector area reduction process using ion implantation, which is extremely important for manufacturing heterojunction bipolar transistors. Furthermore, in the heterojunction bipolar transistor of the present invention manufactured by the manufacturing method of the present invention, since the emitter electrode is formed on the entire upper surface of the emitter, the contact resistance of the emitter electrode is significantly smaller than that of the conventional one, and the transistor This is extremely effective for speeding up. This effect becomes particularly large when manufacturing a micro-sized heterojunction bipolar transistor.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a heterojunction bipolar transistor according to the present invention. FIG. 3 is a process diagram showing a method for manufacturing a veterinary transistor according to the present invention. FIG. 6 is a top view of FIG.
The figures are Fig. 4 (a top view of d+), Fig. 8 is a top view of Figs. 1 is a process diagram showing 1...substrate, 2... highly doped underlayer,
3... Collector or semiconductor material layer forming collector, 4... Base or semiconductor material layer forming base, 5... Emitter or semiconductor material layer forming emitter, 6... ...a highly doped semiconductor material layer to facilitate the ohmic electrode of the emitter,
7-1...Emitter electrode metal, 7-2...
...Emitter electrode wiring metal, 8-1...Base electrode metal, 8-2...Base electrode wiring metal, 9
-1... Collector electrode metal, 9-2...
・Collector electrode wiring metal, 10... Highly doped region of the same type as the base, 11... Semi-insulating region by ion implantation, 12... Insulating film, 13...
...Insulation mask for the transistor formation part and its surroundings, 14...Insulation region around the transistor, 15...Protective layer, 16...Metal mask layer , 17... Photoresist, 18...
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Claims (5)

[Claims] (1) In the heterojunction bipolar transistor in which at least the emitter of the emitter and collector of the bipolar transistor is made of a semiconductor material with a larger band gap than the base, and the emitter is provided on the upper side,
A heterojunction bipolar transistor characterized in that the electrode metal of the emitter covers the entire upper surface of the emitter and extends into a semi-insulating region adjacent to the heterojunction bipolar transistor. (2) The heterojunction bipolar transistor in which at least the emitter of the emitter and collector of the bipolar transistor is made of a semiconductor material with a larger band gap than the base, and the emitter is provided on the upper side. In a manufacturing process of forming an epitaxially formed multilayer structure material comprising at least a large layer of semiconductor material, a layer of semiconductor material for the formation of the base and a layer of semiconductor material for the formation of the collector, the heterojunction bipolar structure of the multilayer structure material a step of making a peripheral part of a portion where a transistor is to be formed semi-insulating; a step of providing a protective layer on the surface of the multilayer structure material; forming a mask material layer extending over an insulating region; removing the protective layer at the periphery of the mask material layer; and etching the multilayer structure material at the periphery of the mask material layer. The base material layer is exposed, or at least the heavily doped layer having carriers of the same type as the emitter on the top of the emitter material layer is etched away to extend the exposed peripheral portion to at least the base material layer. a highly doped layer on top of the emitter material layer after converting it into a semiconductor material having carriers of the same type as the material, or converting at least the emitter material layer in the periphery to a semiconductor material having carriers of the same type as the base; and coating the upper part of the multilayer structure material with a photoresist, and etching the photoresist by dry etching to locate the beginning of the mask material layer or the protective layer formed on the upper part of the emitter. After that, the mask material layer and the protective layer are etched away, and the photoresist left around the emitter is used to deposit an emitter electrode metal to form a lift-off. A method for manufacturing a heterojunction bipolar transistor. (3) A method for manufacturing a heterojunction bipolar transistor according to claim (2), characterized in that a metal is used as the mask material layer. (4) The method for manufacturing a heterojunction bipolar transistor according to claim (2), wherein silicon oxide or silicon nitride is used as the protective layer. (5) A method for manufacturing a heterojunction bipolar transistor according to claim (2), characterized in that a metal is used as the mask material layer, and silicon oxide or silicon nitride is used as the protective layer.