JPH0377331A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To offer a transistor which can comply with a high speed and a large-scale integration of an LSI by a method wherein a collector contact region is formed in the center, a base contact region is formed at its outside and an emitter is formed at an outermost circumference. CONSTITUTION:A slender and long emitter region 31 which is required to lower a base resistance and to increase a cutoff frequency is obtained when it is formed at an outer circumference of an element formation region; it can be formed as the smallest element area. A base contact region 32 is formed at the inside of the emitter region 31; a collector contact region 33 which is connected only to a buried layer 2 to be used as a collector and which does not require an area specially is formed in the central part at its inside. Sizes of the individual regions differ largely; the outside region is longer and the area becomes larger; as compared with transistors of a structure in which an emitter is formed in the center, an emitter area becomes large by 8.9 times or 4.0 times; it is possible to solve a problem of a drop in a cutoff frequency in a large electric-current region due to an increase in a current density.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to bipolar transistors, and in particular,
The present invention relates to a self-aligned transistor with a structure suitable for SI.

[Conventional technology]

With the aim of increasing the speed and density of LSIs, element dimensions have been miniaturized, and their performance has been significantly improved, especially by the adoption of self-alignment technology as described in JP-A-53-132275. It has become possible to use patterns smaller than the size that can be formed using photoetching techniques, and the active area of transistors has been significantly reduced.

With the miniaturization of device dimensions, the reduction in the cutoff frequency in the operating current region due to the increase in current density of the emitter, which becomes a serious problem, can be solved by placing the base contact region in the center as shown in JP-A-61-112378. , by adopting a structure in which an annular emitter region is formed on the outside, the emitter region can be several times larger with the same base area.

In order to reduce the collector region, a method of utilizing polycrystalline silicon buried in the isolation region as a collector lead-out electrode is described in JP-A-62-134941 and other publications. Furthermore, a method of forming polycrystalline silicon that reaches a buried layer around an element region using a self-alignment technique to form a collector electrode is described in Japanese Patent Laid-Open No. 63-215068.

Japanese Patent Laid-Open No. 53-967 describes a method of forming a hole reaching the buried layer and directly forming an aluminum electrode in order to lower the collector resistance.
66.

[Problem to be solved by the invention]

By combining these technologies, bipolar LSIs have been able to reduce the element size and at the same time become interconnected, but they are now close to their limits, and in order to achieve even higher speeds in the future, a simple combination of these technologies will be inefficient. To increase speed, it is important to increase density and reduce parasitic capacitance by reducing element dimensions.
A transistor with a structure suitable for ultra-high-speed LSI is required.

An object of the present invention is to provide a transistor having a structure suitable for an ultra-high-speed LSI, which can support high-speed and large-scale integration of LSIs.

[Means to solve the problem]

The above object can be achieved by adopting a new transistor structure in which a collector contact region is provided in the center, a base contact region is formed outside of the collector contact region, and an emitter, which requires a long and thin region, is formed at the outermost periphery.

[Effect]

The adoption of self-aligned transistors has greatly increased the switching speed of individual transistors, but LSI
The increase in speed is not necessarily satisfactory, and the main reason for this is the increase in the average wiring length due to the expansion of the integration scale,
Another reason is that the current that can be passed through the 14th element has decreased, and the delay due to the addition of the load has become much larger than the switching time of the transistor itself.

Therefore, in order to increase the speed of LSI in the future, it will be necessary to increase the speed of the transistors used there, but we will also consider increasing the density by further reducing the element size, reducing parasitic capacitance, etc., and improving the overall LSI. It is more effective to speed up the process.

Self-aligned transistors currently in common use have a structure in which an emitter region is located in the center, a base contact region is formed outside the emitter region, and a collector contact region is formed next to the base contact region. If the element size is reduced with this structure, it will be difficult to secure the emitter size, and as a countermeasure,
A base contact region is provided in the center, and an annular emitter region is formed on the outside of the base contact region.
Methods of increasing the ratio of kYM are being considered.

In addition, to reduce the collector area, methods are being considered that utilize isolation grooves to pull out the collector.

The present invention is a transistor having a structure that can achieve a reduction in parasitic capacitance, which is important as a transistor for future ultra-high-speed LSIs, and can obtain the largest emitter area with the smallest element area. This transistor is a center collector type annular emitter transistor with a new structure in which an emitter region is provided at the outermost periphery to secure the emitter area, a base contact region is provided inside the emitter region, and a collector contact region is formed at the innermost center. be.

Figure 1 shows the cross-sectional structure of the transistor according to the present invention, and Figure 2 shows the cross-sectional structure of the transistor according to the present invention.
The figure shows a planar structure. The thin and long emitter region 31, which is necessary to reduce the base resistance and increase the cutoff frequency, can be obtained by forming it on the outer periphery of the element forming region.

The element area can be minimized. A pace contact region I' 432 is formed inside the emitter region 31, and a collector contact region 33, which does not require a particular area and is simply connected to the buried layer 2 which becomes the collector, is provided at the center inside thereof. .

As is clear from the figure, there are large differences in the dimensions of each region, with the outer region being longer and having a larger area.For example, if the width of the central collector contact region 33 is 0.6 μm,
The distance between the collector and base contact isolation regions 34 is set to 0.
．． 1 μm, and the width of the base contact region 32 is 0.2 μm.
μm, and the distance between the base and emitter isolation regions 35 is 0.
When it is 2 μm, the collector contact area is 0.36
μm, base contact area area is 0.80 μm
The emitter area is 0.4 times the other areas shown in the figure.
The width is 3.2 μm, and the same film is 0.2 μm, which is the same as other areas.
But it becomes 1.44 μm. Note that the two-element area has a width of 2.4 x 2.4 μm when the emitter width is 0.4 μm, and a width of 2.4 μm when the emitter width is 0.2 μm. OX2.0μ resistance.

This value means that the emitter area is 80% compared to a transistor with the same element size and a general structure where the emitter is formed in the center.
．． 9 times (when the emitter width is 0.4 μm) or 4.
0 times (when the emitter width is 0.2 μm), and the problem of a decrease in cutoff frequency in a large current region due to an increase in current density can also be solved.

By adopting an electrode configuration that is different from that of conventional transistors, the device area can be used effectively, the device dimensions can be reduced, and the wiring length can be shortened due to the reduction of parasitic capacitance and higher density. , crystal interconnection of LSI can be realized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In the figure (a), after forming an N-wall buried layer 2 in a predetermined region of a P-type silicon substrate 1, an epitaxial layer 3 is grown, its surface is thermally oxidized to form silicon dioxide de4, and then The silicon nitride film 5 is deposited by CV IJ (chemical vapor deposition).
This is the place where the material was deposited using the Sitj, On) method.

Figure (b) shows N-type embedded yf using photoetching technology.
After leaving the silicon nitride film 5 and the underlying silicon dioxide film 4 in the element formation region corresponding to 12, a part of the epitaxial layer 3 is etched using these films as a mask, and then an inversion layer is formed as necessary. A p-type impurity for prevention is ion-implanted in the etch direction.

Next, a thick silicon dioxide film 6 for isolation is formed by thermal oxidation, and the silicon nitride film 5 and the silicon dioxide film 4 thereon are removed to expose the epitaxial layer 3.

The steps up to this point are a general isoplanar element isolation step, and then a polycrystalline silicon film 7, which will serve as a conductor layer for leading out the emitter, is deposited by CVD. First, boron ions for forming a base layer are implanted into this polycrystalline silicon film 7, and heat treatment is performed to form a base v8 at a predetermined depth. This state is shown in FIG. 4(c).Subsequently, arsenic ions are implanted into the polycrystalline silicon film 7 as an impurity for forming an emitter.

Next, after removing the polycrystalline silicon film 7 other than the area to be used as an emitter electrode by photoetching,
Silicon dioxide film 9 and polycrystalline silicon l are formed by CVD method.
! When A10 is layered and applied, it becomes the shape shown in the same figure (d). In the same figure (e), after slowly cooling the polycrystalline silicon 11 in the base contact and collector contact forming regions, the silicon dioxide Ill and the polycrystalline silicon film 7 are oxidized. 11 is deposited on silicon 11 by the CVD method.

Next, this silicon dioxide removal 11 is etched in the depth direction, but if the entire surface is etched using an anisotropic etching device that does not cause so-called side etching in the lateral direction, the interlayer film 11 can be left only in the step portions. . The thickness of this film becomes the separation distance between the emitter region and base contact region. Next, a polycrystalline silicon film 12 is deposited by CVD method,
After boron ions for forming an external base are implanted, a silicon nitride film 13 is deposited. Subsequently, when heat treatment is performed, the arsenic ion-implanted into the polycrystalline silicon film 7 is diffused and an emitter layer 14 is formed.At the same time, the polycrystalline silicon film 1
Boron in 2 can diffuse to form an external base N15,
The shape will be as shown in (f) in the same figure.

FIG. 3(g) shows that a photoresist film 16 is applied to the surface of the silicon nitride film 13, and the entire surface is etched to leave only the holes where the interlayer is thickly applied, leaving the exposed area. This is the place where the silicon nitride film 13 has been removed. Next, by photo-etching, the polycrystalline silicon film 10.12 in areas other than the area used as the base electrode is removed, resulting in the shape shown in FIG.

Figure (i) shows this polycrystalline silicon 1lililo, 1
2 is partially oxidized to form a silicon dioxide film 17.

The silicon nitride film 13 used as an oxidation mask has been removed. Since the base and emitter layers have already been formed, this oxidation cannot be carried out at a high temperature that would cause the periphery of these layers to re-diffuse. Therefore, a high-pressure oxidation method that allows the formation of a silicon dioxide film at a low temperature was employed.

In the same figure (j), the polycrystalline silicon film 12 and the epitaxial layer 3 thereunder are etched using an anisotropic etching device using the silicon dioxide films 9 and 17 as masks, and the N-type buried layer 2 is etched.
This is where the hole 18 for the collector contact reaching the hole 18 is formed.

Next, thermal oxidation is performed to form a silicon dioxide film 1 on the surface of the hole 18.
After forming hole 9, hole 1 is etched using an anisotropic etching device.
Remove only the corner part [19] (k in the same figure). Here, a thermal oxide film is used because the film thickness may be thin, but C
When the silicon dioxide films 17 and 9 of the base contact hole 20 and the emitter contact hole 21 are etched by zero-order photoetching technology, which can also be used with a silicon dioxide film produced by the VL) method, the mold shown in FIG. 1 (1) is obtained. .

Next, wiring made of aluminum or the like is formed to complete the annular emitter type transistor with a collector contact formed in the center as shown in FIG.

An example of a method for manufacturing a transistor having a structure suitable for an ultrafast LSH according to the present invention has been described above, but the feature of the present invention is the connection to the emitter region. A second conductor layer connected to the base contact is formed on the first conductor layer, a collector contact region reaching the buried layer is formed in a region surrounded by these conductor layers, and an emitter and base extraction electrode is formed. It goes without saying that there will be no problem if the polycrystalline silicon film used as a metal silicide film or a 2M structure of a polycrystalline silicon film and a metal silicide film is used.

〔Effect of the invention〕

According to the present invention, a transistor with a predetermined emitter area can be formed in a smaller area, parasitic capacitance is significantly reduced, and at the same time, wiring length can be shortened due to high density, and LSH delay time can be shortened. A great effect can be obtained in speeding up the process.

In addition, compared to the conventional structure in which the collector contact is formed outside the base contact area, the contact area between the two is shortened, and the capacitance between the collector and the base, which has a large effect on the delay time of the LSI, is significantly reduced. There are also effects that can reduce it.

Furthermore, compared to the conventional method in which the collector contact is formed outside the element formation area in the initial process,
The present invention, in which the hole for the collector contact is formed in a step close to the final step, does not require burying and planarizing the conductive material in the circuit, and has the effect of simplifying the manufacturing process of the transistor.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a transistor according to the present invention, and FIG.
The figure is a planar structural diagram thereof, and FIG. 3 is a new structural diagram showing the manufacturing process of a transistor according to the present invention. 1... Silicon substrate, 2... N-type buried layer, 3...
Epitaxial layer, 4, 6, 9, 11, 17, 19...
・Silicon dioxide film, 5.13...Silicon nitride in general,
7゜10.12... Polycrystalline silicon film, 8... Base layer, 14... Emitter layer, 15... External base layer, 16... Photoresist film, 18... Collector contact hole. 20... Base contact hole, 21... Emitter contact hole, 31... Emitter region, 32... Base contact region, 33... Collector contact region, 34... Base/collector separation region, 35・・・Emifuru Atsushizu Z Sendaizu

Claims (1)

[Claims] 1. A semiconductor having an element formation region isolated by an insulating film, in which a buried layer of a second conductivity type is formed in a predetermined region of a semiconductor substrate of a first conductivity type, and a semiconductor layer is grown. In the device, a first conductive layer of a second conductivity type is formed on an outer peripheral surface of the element forming region.
a first conductor layer connected to the region, and a second conductor layer connected to a second region of the first conductivity type in a predetermined region surrounded by the first conductor layer.
the first conductor layer and the second conductor layer are separated by an insulating film, the second conductor layer is formed to cover at least a part of the first conductor layer, and the second conductor layer is separated from the second conductor layer by an insulating film; 1. A semiconductor device, characterized in that a hole is formed in a predetermined region surrounded by layers and whose side surface reaching the buried layer of the second conductivity type is covered with an insulating film. 2. Forming a buried layer of a second conductivity type in a predetermined region of a semiconductor substrate of a first conductivity type, growing a semiconductor layer, and using a semiconductor substrate having an element formation region isolated by an insulating film, forming a first conductor layer connected to the first region of the second conductivity type on the surface of the outer peripheral region of the formation region; and forming a second conductor layer surrounded by the first conductor layer in a predetermined region of the first conductor layer.
a step of forming a region for connecting a conductor layer; and a step of forming a second conductor layer connected to the second region of the first conductivity type and covering at least a portion of the first conductor layer via an insulating film. , second
forming a third region reaching the buried layer of a second conductivity type in a predetermined region surrounded by a conductor layer.