JPS6226055B2 - - Google Patents

Info

Publication number
JPS6226055B2
JPS6226055B2 JP57161934A JP16193482A JPS6226055B2 JP S6226055 B2 JPS6226055 B2 JP S6226055B2 JP 57161934 A JP57161934 A JP 57161934A JP 16193482 A JP16193482 A JP 16193482A JP S6226055 B2 JPS6226055 B2 JP S6226055B2
Authority
JP
Japan
Prior art keywords
transfer
register
address
bit string
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57161934A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5952334A (ja
Inventor
Mitsuki Fukuzumi
Chihiro Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP57161934A priority Critical patent/JPS5952334A/ja
Publication of JPS5952334A publication Critical patent/JPS5952334A/ja
Publication of JPS6226055B2 publication Critical patent/JPS6226055B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
JP57161934A 1982-09-17 1982-09-17 Ｄｍａ転送方式 Granted JPS5952334A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57161934A JPS5952334A (ja) 1982-09-17 1982-09-17 Ｄｍａ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57161934A JPS5952334A (ja) 1982-09-17 1982-09-17 Ｄｍａ転送方式

Publications (2)

Publication Number Publication Date
JPS5952334A JPS5952334A (ja) 1984-03-26
JPS6226055B2 true JPS6226055B2 (de) 1987-06-06

Family

ID=15744809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57161934A Granted JPS5952334A (ja) 1982-09-17 1982-09-17 Ｄｍａ転送方式

Country Status (1)

Country Link
JP (1) JPS5952334A (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202254A (ja) * 1986-02-07 1987-09-05 Fujitsu Ltd 論理装置に対する連続デ−タ転送方式
JPS62217766A (ja) * 1986-03-19 1987-09-25 Canon Inc メモリ制御回路
JPS63279351A (ja) * 1987-05-12 1988-11-16 Fujitsu Ltd Ｄｍａ転送制御装置
JPS63276154A (ja) * 1987-05-07 1988-11-14 Fujitsu Ltd Ｄｍａ転送制御装置
JP2747353B2 (ja) * 1990-02-08 1998-05-06 富士通株式会社 アドレス発生装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49111562A (de) * 1973-02-22 1974-10-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49111562A (de) * 1973-02-22 1974-10-24

Also Published As

Publication number Publication date
JPS5952334A (ja) 1984-03-26

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