JPS6225455A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a hetero junction bipolar transistor which operates at ultrahigh speed by using a superlattice structure in which an impurity is doped only in a semiconductor for forming a shallow impurity level, and using one or more base layers and the secondary carrier. CONSTITUTION:A p<+> type GaAs layer 31 in which B is doped as a dopent in density of 1X10<19>cm<-3>, an undoped p<-> type GaAs layer 32, and an n-type AlGaAs/GaAs superlattice layer 33 are laminated and epitaxially grown on a p<+> type GaAs substrate 30 in which Ge is doped as a dopant in density of 2X10<19>cm<-3>. Here, the layer 33 is formed of an undoped AlxGa1-xAs/n-type GaAs/undoped AlxGa1-xAs/n-type GaAs/undoped AlxGa1-xAs, further a p-type AlGaAs/GaAs superlattice layer 35 formed thereon is formed of an undoped AlxGa1-xAs/p-type GaAs, and the mixture crystal of the aluminum, the Si and the Be is specified. Thereafter, the entire surface is coated with a p-type GaAs layer 36, a window is opened at a superlattice layer, and a base electrode 59 is formed on the layer 33.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a heterojunction bibolar transistor,
In particular, the present invention relates to a semiconductor device which has excellent temperature characteristics and is suitable for ultra-high speed operation at low temperatures of 7'7/'.

[Background of the invention]

Conventionally, silicon [Si] bipolar transistors or GaAs layer A Q GaAs heterojunction bipolar transistors [for example, prosthetic junction bipolar transistors]
The Twelges Conference on Solid
State Devices
the 12th conference on 5o
lid 5tate Devices) 1980, P
1] at 77K [liquid nitrogen temperature], the number of carriers in the emitter, base, and collector decreases drastically due to carrier freezing [freezp out], resulting in performance deterioration compared to room temperature, and the device I was never interested in it.

In the case of Si bipolar transistors, the commonly used r
For l-type impurities, the impurity levels Ed of phosphorus (P) and arsenic (As) are 45 mV and 54 mV, respectively, and the impurity level Ea of boron (B), which is an n-type impurity, is 45 mV.
It is.

For such deep impurity levels, 77K (>6.4 m
It is well known that when the carrier is cooled to V), the carrier freezes.

-For force ratio compound semiconductors, e.g. GaAs, n
The impurity level of (Si), which is a type impurity, is 1017】-
At high concentrations of 3 or higher, freezing of the carrier hardly occurs to the extent of 77%. On the other hand, p-type impurities include Be, MKT
It is known that even in Zn, at a high concentration of 10"cxr-" or higher, the impurity level (the energy difference from the valence band edge to the ionized acceptor) becomes extremely shallow, and freezing of the carrier at 77 does not occur. (Heterostraft Laser Academic Press)
New York (HeteroStructure L
a5ers, Academic Press.

Neti York) 1978. p. 132).

In addition, a normal GaAs layer A Q GaAs heterojunction bipolar transistor [abbreviated as HBT, npn
In the type, n-type AQ GaAs is used as an emitter, and pn
In the case of p-type, p-type AQ GaAs is used for the emitter.

However, the commonly used AQ mixed crystal ratio X (~0.3
), Si is an n-type impurity and Be is an n-type impurity.
, Mg forms a relatively deep impurity level of around 60 mV called a Dx center, and carrier freezing occurs at 77°C, resulting in performance deterioration of HBT by more than an order of magnitude compared to the case at room temperature.

[Purpose of the invention]

The aim of the invention is to achieve particularly ultra-high speeds at low temperatures of 77°C. An object of the present invention is to provide a heterojunction bipolar transistor structure using a two-dimensional carrier as a base layer.

[Summary of the invention]

In the case of GaAs/A Q GaAs heterojunction bipolar transistor, A Q GaA doped with impurities
As mentioned above, as long as s is used, it is impossible to expect high-speed operation at liquid nitrogen temperature (77K).

On the other hand, the two-dimensional electron gas layer accumulated at the single heterojunction interface between n-type AQ GaAs and undoped GaAs is 77'
"C extremely high mobility (~117,0OOa&/v-
For example, Japanese Journal on Applied Physics
of Applied Physics) 20 (I98
1) See L455, )) is known experimentally. In such a high-mobility system, the sheet resistance ρ, 2DIO of the secondary electron-perfect gas layer is around 100Ω/portion, and the normal npn type GaAs/AQ GaAsH
The base sheet resistance of BT is approximately 1740. That is,
If the secondary electron perfect gas layer in 77 is used as a base layer, H has a base resistance about 1/40 lower than that of a normal HBT
There is a possibility that BT can be realized.

Furthermore, AQ GaAs layer GaAs superlattice [for example, the literature Japanese Journal on Applied Physics (Japanese Journal on Applied Physics)
of Applied Physics) 20 (I983
) L627] and a structure in which only the GaAs layer is doped with impurities, it is possible to have the same effect as an A Q GaAs layer doped with impurities without carrier freezing.

That is, conventional HBT doped AQ
Instead of a GaAs layer, GaAs is doped with impurities,
A Q GaAs is not doped with impurities A Q G
It can be said that if an aAs/G a As superlattice is used, freezing of the carrier at 77 will hardly occur.

Therefore, in consideration of the above two items, the inventors developed an emitter (
We have invented a new pnp bipolar transistor that has a superlattice structure in the base layer and the base layer and uses a two-dimensional electron gas in the base layer.

FIGS. 1(a) to 1(d) show a semiconductor structure for explaining the operating principle of the pnp transistor of the present invention (see FIG. 1(a)).
) and its band structures (b), (c), and (d) are shown.

The specific operating principle of the invention is the GaAs layer A Q GaAs
The case will be explained using a heterojunction.

FIGS. 1(a) and 1(b) show a sectional view of the main part of a transistor (a) and a corresponding energy band diagram (b), respectively, and FIGS. 1(c) and 1(d) show supplementary band diagrams.

31 is the collector layer 1, which usually has Be or Mg as a p-type impurity and has an impurity level of ~10"m-'G a A
It is s. 32 is p-(significantly 1015au-3)GaA
There are usually around 3,000 people in the S class. The key points of the present invention are the n-type A n GaAs layer GaAs superlattice layer 33 and the p-type A Q GaAs layer GaAs superlattice layer 35 . Here, the n-type superlattice layer 33 is composed of n-type doped Ga A 5332 and A with a doping level of not intentionally doped with impurities or 1 usually 101 s low 1 or less.
It has a superlattice structure in which Q GaAs layers 331 are alternately stacked.

Usually, AQ mixed crystal ratio or between 0.15 and 0.45 is often used. The energy band diagram is shown in FIG. 1(d). The thickness of the normal GaAs layer 332 and the AQGaAs layer 331 can be varied within a wide range from 31 to 100 layers. Also, something important.

The collector 32 side of the n-type superlattice layer 33 is Ait GaAs.
It is important that the layer 331 is formed.

On the other hand, the p-type superlattice layer 35 is p-doped GaA
s352 and do not intentionally tope impurities, usually 10
A Q GaAs with doping level below “am-”
It has a superlattice structure in which layers 351 are alternately stacked. In this case as well, the GaAs layer 352. The thickness of the AQ(EaAs layer 351) is 5 to 100.

Further, in this case, the AQ GaAs layer 351 can increase the current amplification factor by increasing the mixed crystal ratio of AQ as the distance from the n-type superlattice increases.

The biggest reason for introducing such a superlattice structure is that p-type/n
This is because if the type impurity is appropriately selected, the donor and acceptor levels of the impurity in GaAS are shallow, so that freezing of the carrier at 77 does not occur.

Furthermore, the term "superlattice" as used herein refers to one in which the carriers are spread throughout the superlattice. In other words, A Q GaAa/GaAs
It is not localized on the Ga As side of the well-type potential consisting of .

From the standpoint of transistor design, the n-type superlattice 33 and the p
- The two-dimensional electron gas 19 accumulated at the heterojunction interface of the collector layer 32 is used as the base layer, but as shown in the band diagram shown in FIG. 1(e), n-type A Q G
aAs layer G a A a superlattice layer 33' and undoped GaAs layer 32' are formed, and further n-type A Q GaAs
Layer A GaAs superlattice layer 33 may be formed.

By forming two two-dimensional electron gas layers 19 and 19' in this manner, the base resistance can be halved.

In addition, in order to shorten the hole base travel time, at the p-n junctions 35 and 33 between the P-type superlattice and the n-type superlattice, the n-type superlattice is depleted except for the two-dimensional electron gas part. The n-type superlattice is also partially depleted. As shown in the amphoteric depletion layer 34 (FIG. 1(a)), it is normal to avoid forming a neutral region in which carriers exist in the n-type superlattice.

In addition, the p-Ga base layer in which the two-dimensional electron gas exists
As 32 and n-type A Q GaAs layer Ga As
Energy jump in the conduction band of the superlattice AED9 is 300
Because the m e V (difference in electron affinity between the superlattice and Ga As) is large, the high current amplification factor becomes large, and the film thickness of the two-dimensional electron gas is very thin on the eaves of about 100 people. For.

The base transit time of holes becomes negligible, and compared to the conventional p
With np-type HBTs, it is now possible to remove the base running time limit that causes extremely slow speeds.

Next, the general application of the present invention when two-dimensional holes are used in the base layer is shown in Figure 2 (a). ) and (b).

Figure 2(a) shows the cross-sectional structure of the main part of the new HBT.
FIG. 2(b) is a diagram of the corresponding energy pan 1.

n+G containing about 5 X I O1'rx-3 Si
1.014 antimony sb on the aAs collector layer 41
The n-Ge collector layer 42 containing about 0.011-3
00 people, Ga containing 5 x 10"3-' Be
About 200 people form A s43, and n is the emitter layer.
Type A Q GaAs layer GaAs superlattice 45 3000
A size is formed.

Here, the impurity doping level of the n-type superlattice is 2XL O
"It's about an-3.

In GaAs and G, valence band gap discontinuity AEv7
Because of this, a portion of the free holes in the p-type GaAs layer 43 accumulates on the G side 42, forming a two-dimensional hole gas 29. At room temperature, the mobility is about 3,0OOcj/vs and the sheet density is about 2.times.IQ"an-".

On the other hand, some of the free holes in the p-type GaAs layer 43 move to the n-type superlattice 45, forming a space charge layer gas.

At a low temperature of 77°C, the mobility of the two-dimensional hole gas is 50.0
00aJ/vs, and the sheet resistance is around 20Ω/mouth, resulting in an extremely low base resistance.

In this example in which a two-dimensional hole gas is used in the base layer, even if the n-type superlattice 45 is replaced with n-type GaAs, high-speed operation can be achieved at 77.

As explained in the novel pnp HBT, it is possible to further reduce the base resistance by using multiple two-dimensional hole gas layers in the base.

As described above, the present invention is a GaAs/Al2GaAs heterojunction system,
The case has been explained using an AQGaAs (GaAs) heterozygous system.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail through examples.

Embodiment 1: The main steps carried out in the case where the collector layer is provided on the back side of the substrate are shown in FIG.

MBE l
A p + GaAs layer (concentration I
X 10"■-1. Thickness 5000 layers) 31. Undoped (results in p-type of 101san-') GaA
S layer 32 has 3000 people, n type A Q GaAs layer G
a A s superlattice 33 has 200 people [undoped A Q
, Ga,, 50 As / 25 n-type GaAs / undoped A Q , Ga 1-x As25 As2 25 As: AQ mixed crystal ratio x-0.3, Si impurity concentration 4
X 1 0”G! 1-31, p-type A Q GaA
s/GaAs superlattice 352,000 people [undoped AQx
Gal-. As 25 people/p-type GaAs 25 people to 40
superlattice with
an-' degree], Be I X 10"m-'
The p-type GaAs layer 36 containing 2000 layers was formed [FIG. 3(d)].

Subsequently, 5L02583000 layers are formed on the entire surface by CVD method to form a p-type GaAs layer 36 and a p-type superlattice layer 35.
was removed by etching, and a base electrode 59 was formed using a normal photolithography process. AuGe/Ni/Au was used as the base electrode. Next, 450'
Alloying for C13 minutes was carried out in H2 atmosphere. Similarly, Cr/Au was deposited on the entire back surface as a collector 11i electrode, and Cr/Au was also formed on the p-type GaAs layer 36 as an emitter electrode.

Ohmic contact was obtained by performing alloying at 300°C for 10 minutes [Fig. 3(b)].

Next, mesa etching was performed for isolation between elements.

In this example, the AQ of the n-type superlattice 35 is
The mixed crystal ratio X was 0.3 and uniform. This is not necessarily necessary. The current amplification factor h rt can also be increased by adding a gradient of 0.2 on the n-type superlattice side and 0.40 on the p-type GaAs 36 side.

It is also possible to form a collector electrode in a planar manner by forming 31 or more epitaxial layers on a semi-insulating GaAs substrate, as is usually done in planar HBTs.

Example 2: An example in which a two-dimensional hole gas is used in the base layer is shown in FIGS. 4(a) and 4(b).

n-type Ga containing 2×10”am-’ Si
2×1 Si is deposited on the As substrate 70 by the MBE method.
The n+GaAs layer 71 containing 0"a++-'
Formed as a human collector layer. Next, Si is I
The Ga As layer 72 containing Q"n-3 is 3000
Form people.

Next, a P-type AQ GaAs/GaAs superlattice 73 is
0 people [Undoped A Q xG a +-xAs5 0
Human lp type G a A s 25 people / Undoped A Q x
G a ,, 25 As / p-type GaAs 25 / undoped A Q x Ga ,, As 25 / p-type GaAs
25 undoped A Q xG a , -xAs25; ``C3I-'' containing G
After forming the a A s layer 74, the p-type A Q similar to 73 is formed.
GaAs layer GaAs superlattice 75 with 300 layers [Undoped A Q zGa t-xAs25 layers IP type GaAs
Super lattice consisting of 25 people and 6 pieces = x ~ 0.45p type Ga
As s is a p-type impurity, Be is I x 10”C1
1-'containing] and furthermore, n-type A Q GaAs/
2000 GaAs superlattice 76 [undoped A n
xG a 1-xAs50 people/n-type GaAs50 people is 2
Superlattice formed from 0=X~Q-4. n-type Ga
As contains 3 x 10"am-' of Si.

], and furthermore, an n+ GaAs layer 77 [Si impurity of 3 x 10'''C to facilitate the formation of an ohmic electrode.
I! 1-' Formation] was formed by 2000 people [Figure 4(d)].

After forming 3000 Sin on the entire surface by CVD method, collector tl! is formed on the back side. As pole 67 A u G e/
Vacuum evaporate Ni/Au and use normal phosphorography to form the emitter electrode 6 on the n''GaAs layer 77.
8, A.sub.G e/N.sub.i/A.sub.u was deposited. Subsequently, alloying was performed at 400° C. for 3 minutes in an H2 atmosphere to obtain ossic contact.

Next, the n0 type GaAs layer 77 and the n type superlattice 76 were removed by etching, and a base electrode 69 was formed by a conventional method. Cr/Au is used for the base electrode, 3'0
Alloying was performed at 0°C for 10 minutes.

In the above embodiments, the present invention was implemented using an AQ GaAs layer GaAs heterojunction system.

The present invention is also effective in other heterozygous systems.

For example, I n P / I n GaAsP+ G
aAsP+ Q GaAsP.

InP/InGaAs, InAs/GaAs
5b, CbTe/InSb, GaSb/InA
s etc.

〔Effect of the invention〕

According to the invention, using a superlattice structure in which only the semiconductor forming the shallow impurity level (donors and acceptors) and the semiconductor forming the shallow impurity level are doped with impurities,
Since we have formed a heterojunction bipolar transistor using one or more two-dimensional carriers as a base layer, the carriers do not freeze at low temperatures of 77°C, unlike conventional carriers, and the high mobility of the two-dimensional carriers at 77°C can be maintained. Therefore, it has become possible to have a base resistance about 1/40 lower than that of conventional HBTs.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view of a pnp-type hetero bipolar transistor of the present invention and an energy band diagram corresponding to it, FIG. 2 is a longitudinal cross-sectional view of an npn-type hetero bipolar transistor of the present invention and an energy band diagram corresponding to it, and FIG. , FIG. 4 is a longitudinal sectional view of the transistor of the present invention.

Claims (1)

[Claims] 1. At least one heterojunction is formed by a high-resistance semiconductor (I) and a semiconductor (II), and the semiconductor (II) has a higher resistance than the semiconductor (I). When the electron affinity is small, n-type impurity is used, and when the sum of electron affinity and energy gap width is larger than that of the semiconductor (I), p-type impurity is used.
A two-dimensional carrier is formed at the heterojunction interface between the semiconductor (I) and the semiconductor (II) by doping type impurities, and an electrode is electrically connected to the two-dimensional carrier, and the semiconductor (I, II) conductive semiconductor layers (III) and (IV) provided on both sides of the two-dimensional carrier and having opposite signs to the two-dimensional carrier;
At least two electrodes electronically connected to the semiconductor layer (III, IV) are formed, and the level of the impurity is adjusted to a donor level E_ from the conduction band edge in the case of an n-type impurity.
When D is a p-type impurity, the acceptor level E_A from the valence band edge is the liquid nitrogen temperature (77K 6.5meV)
1. A semiconductor device characterized in that the semiconductor device has the following characteristics: 2. In claim 1, the semiconductor (II)
(III) At least one of (IV) is combined with a semiconductor (A) whose donor level E_D or acceptor level E_A is below the liquid nitrogen temperature, or whose electron affinity is smaller than that of the semiconductor A, or where the electron affinity and the energy forbidden band width are different. 1. A semiconductor device formed of a superlattice of semiconductor B which has a large sum and does not intentionally contain impurities. 3. In claim 2, the semiconductor layer (I)
GaAs is added to the semiconductor layer (IV) as p^-GaAs/p^+
GaAs as n-type G as semiconductor (A) of semiconductor (II)
aAs, undoped AlGaAs as the semiconductor (B), p-type GaAs as the semiconductor (A) of the semiconductor layer (III) connected to the semiconductor layer (II), and undoped AlGaAa as the semiconductor (B). Semiconductor equipment.