JPS6225211B2 - - Google Patents
Info
- Publication number
- JPS6225211B2 JPS6225211B2 JP57045910A JP4591082A JPS6225211B2 JP S6225211 B2 JPS6225211 B2 JP S6225211B2 JP 57045910 A JP57045910 A JP 57045910A JP 4591082 A JP4591082 A JP 4591082A JP S6225211 B2 JPS6225211 B2 JP S6225211B2
- Authority
- JP
- Japan
- Prior art keywords
- scan
- input
- circuit
- register
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
- 
        - G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
 
- 
        - G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
 
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP57045910A JPS58163049A (ja) | 1982-03-23 | 1982-03-23 | 論理回路システムの試験方式 | 
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP57045910A JPS58163049A (ja) | 1982-03-23 | 1982-03-23 | 論理回路システムの試験方式 | 
Publications (2)
| Publication Number | Publication Date | 
|---|---|
| JPS58163049A JPS58163049A (ja) | 1983-09-27 | 
| JPS6225211B2 true JPS6225211B2 (OSRAM) | 1987-06-02 | 
Family
ID=12732394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date | 
|---|---|---|---|
| JP57045910A Granted JPS58163049A (ja) | 1982-03-23 | 1982-03-23 | 論理回路システムの試験方式 | 
Country Status (1)
| Country | Link | 
|---|---|
| JP (1) | JPS58163049A (OSRAM) | 
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title | 
|---|---|---|---|---|
| JPS60142432A (ja) * | 1983-12-28 | 1985-07-27 | Fujitsu Ltd | シリアル・データ・スキャン・イン/アウト方法 | 
| JPS61193082A (ja) * | 1985-02-21 | 1986-08-27 | Nec Corp | Lsiのスキヤンパス方式 | 
| JPH0743655B2 (ja) * | 1985-08-28 | 1995-05-15 | 日本電気株式会社 | 情報処理装置 | 
- 
        1982
        - 1982-03-23 JP JP57045910A patent/JPS58163049A/ja active Granted
 
Also Published As
| Publication number | Publication date | 
|---|---|
| JPS58163049A (ja) | 1983-09-27 | 
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