JPS6224616A - Epitaxial growth method - Google Patents
Epitaxial growth methodInfo
- Publication number
- JPS6224616A JPS6224616A JP16331185A JP16331185A JPS6224616A JP S6224616 A JPS6224616 A JP S6224616A JP 16331185 A JP16331185 A JP 16331185A JP 16331185 A JP16331185 A JP 16331185A JP S6224616 A JPS6224616 A JP S6224616A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion
- epitaxial growth
- back surface
- wafer
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
埋込拡散層を有するエピタキシャルウェハを製造する方
法であって、半導体基板の裏面側の不純物拡散層を除去
した後、エピタキシャル成長を行ない、裏面からのオー
トドーピングを防止する。[Detailed Description of the Invention] [Summary] A method for manufacturing an epitaxial wafer having a buried diffusion layer, in which an impurity diffusion layer on the back side of a semiconductor substrate is removed, epitaxial growth is performed, and autodoping from the back side is performed. To prevent.
本発明はバイポーラ・ICのコレクタ抵抗低減の為の低
抵抗層、圧力センサ等の三次元加工が必要なデバイスの
エツチング停止層等として埋込拡散層を有するエピタキ
シャルウェハを製造する方法に関する。The present invention relates to a method for manufacturing an epitaxial wafer having a buried diffusion layer as a low resistance layer for reducing the collector resistance of bipolar ICs, an etching stop layer for devices such as pressure sensors that require three-dimensional processing, and the like.
第2図A−Eに従来のオートドーピングを防止したエピ
タキシャル成長方法を示している。FIGS. 2A to 2E show a conventional epitaxial growth method that prevents autodoping.
図A(初期酸化)においてSi基板1にSiO2膜2,
3を形成し、図B(フォトエッチ)において裏面を研摩
する等してSt基板を所定の厚味となし、S iO2膜
2に拡散窓4を形成し、図C(デボ、拡散)において熱
拡散により埋込拡散層5を形成し、その際裏面拡散層6
が形成されるので、図D(マスク除去、裏面被覆)にお
いて、裏面にCVD、減圧CVD、プラズマCVD等に
よりPSG (燐シリケートガラス)、N5C(シリケ
ート舛ガラス)、Si3N4.Po1ySi等の裏面被
覆層7をもうけると共に拡散マスクのSi O2膜2を
除去し、図Eにおいてエピタキシャル成長を行なう。In Figure A (initial oxidation), a SiO2 film 2,
3 is formed, and the back surface is polished to a predetermined thickness in Figure B (photoetching), a diffusion window 4 is formed in the SiO2 film 2, and heat treatment is performed in Figure C (debo, diffusion). A buried diffusion layer 5 is formed by diffusion, and at that time, a back diffusion layer 6 is formed.
In Figure D (mask removal, backside coating), PSG (phosphorus silicate glass), N5C (silicate glass), Si3N4. A backside coating layer 7 of Po1ySi or the like is formed, the SiO2 film 2 serving as a diffusion mask is removed, and epitaxial growth is performed as shown in FIG.
ところが上記従来法では次のような欠点がある。 However, the above conventional method has the following drawbacks.
■埋込拡散層形成後に裏面の処理を行なう(フォトエッ
チ、CVD等)為、表面側で保持することが必要になり
、表面に傷や汚染をあたえる原因になり、歩留りが低下
する。(2) Since the back side is processed (photoetching, CVD, etc.) after the buried diffusion layer is formed, it is necessary to hold it on the front side, which causes scratches and contamination on the surface and reduces yield.
■埋込拡散層形成後に、裏面被覆層形成の為余分な熱工
程を有する為、埋込拡散層の不純物プロファイルの制御
が難しく、素子特性が劣化する。(2) After the buried diffusion layer is formed, an extra thermal process is required to form the backside coating layer, which makes it difficult to control the impurity profile of the buried diffusion layer, resulting in deterioration of device characteristics.
■裏面被覆工程が必要であり、工程数が増加する。■A backside coating process is required, increasing the number of processes.
■熱膨張率の異なる被覆層を有する為エピタキシャル成
長工程でウェハに反りが生ずる。(2) Warpage occurs in the wafer during the epitaxial growth process because the wafer has coating layers with different coefficients of thermal expansion.
本発明においては、上記問題点を解決するために半導体
基板上の一主面側に拡散マスクを形成して選択拡散によ
り埋込拡散層を形成した後、該半導体基板の一主面側表
面を保護膜で覆い、半導体基板の裏面側の不純物拡散層
を除去し、前記一主面側の保護膜及び拡散マスクを除去
し、しかる後膣−生面上にエピタキシャル成長層を形成
するようにする。In order to solve the above problems, in the present invention, after forming a diffusion mask on one main surface side of a semiconductor substrate and forming a buried diffusion layer by selective diffusion, the surface on one main surface side of the semiconductor substrate is formed. Cover with a protective film, remove the impurity diffusion layer on the back side of the semiconductor substrate, remove the protective film and diffusion mask on the one main surface side, and then form an epitaxial growth layer on the vaginal surface.
上記によれば、埋込拡散層形成後に余分の熱工程がない
ので特性劣化のおそれがなく、またエピタキシャル成長
時に熱膨張率の異なる被覆層がないのでウェハの反りも
生じない。According to the above, since there is no extra heat step after forming the buried diffusion layer, there is no risk of deterioration of characteristics, and since there is no covering layer with a different coefficient of thermal expansion during epitaxial growth, no warping of the wafer occurs.
さらに、ウェハの初期厚味にバラツキがあっても(ウェ
ハ間、ウェハ内典)、前記裏面側の不純物拡散層の除去
時に研摩により均一化ができる。Furthermore, even if there is variation in the initial thickness of the wafers (between wafers or within a wafer), it can be made uniform by polishing when removing the impurity diffusion layer on the back side.
第1図に本発明の実施例の製造工程図を示してあり、以
下これを説明する。FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention, which will be explained below.
図A〜図Cまでは従来の第2図と同様であり、符号は統
一しである。FIGS. A to C are the same as the conventional FIG. 2, and the reference numerals are the same.
図りにおいて、埋込拡散層が形成されたウニ/’%の裏
面を機械的に研摩し、裏面拡散層6を除去する。In the drawing, the back surface of the urchin/'% on which the buried diffusion layer is formed is mechanically polished to remove the back surface diffusion layer 6.
舛このとき、同時にウェハの厚味を均一化する。At the same time, the thickness of the wafer is made uniform.
この裏面研摩の際には、表面を保護する為、保護膜(図
示せず)、例えばワックス、フィルム(日東電工製、エ
レフプカバー)等で覆っておく。その後、洗浄を十分行
ない、表面の保護膜及び拡散マスクのSiO2膜2を除
去する。During this backside polishing, in order to protect the surface, it is covered with a protective film (not shown), such as wax or film (manufactured by Nitto Denko, Elepcover). Thereafter, thorough cleaning is performed to remove the surface protective film and the SiO2 film 2 of the diffusion mask.
図Eにおいて、常法によりエピタキシャル成長を行なう
。In Figure E, epitaxial growth is performed by a conventional method.
以上のことから明らかなように、本発明によれば次の効
果が得られる。As is clear from the above, according to the present invention, the following effects can be obtained.
■素子の特性劣化1歩留り低下がない。■Deterioration of device characteristics 1 No decrease in yield.
これは、本発明では裏面研摩の際に表面を保護膜で藺憎
あり、傷や汚染を与えることがない為であり、又埋込拡
散層形成後に従来のように余分の熱工程が無いことに基
づく。This is because in the present invention, the surface is covered with a protective film during backside polishing, so there is no damage or contamination, and there is no extra heat process required in the conventional method after forming the buried diffusion layer. based on.
■ウェハの反りが生じない。■Wafer does not warp.
エピタキシャル成長時に熱膨張率の異なる被覆が存在し
ない為。Because there is no coating with a different coefficient of thermal expansion during epitaxial growth.
■ウェハの厚味を均一化できる。■The thickness of the wafer can be made uniform.
ウェハ内、ウェハ間共、初期値にバラツキがあっても裏
面拡散層の除去時の研摩工程で均一化できる。Even if there are variations in the initial values both within a wafer and between wafers, they can be made uniform by the polishing process when removing the backside diffusion layer.
特に、圧力センサ等の製造においては、そのダイアフラ
ム形成均一化のためのウェハ厚味調整が裏面拡散層の除
去時の研摩工程の際同時に行なえる利点がある。In particular, in the manufacture of pressure sensors and the like, there is an advantage that the wafer thickness adjustment for uniform diaphragm formation can be performed simultaneously during the polishing process for removing the back diffusion layer.
第1図A−Eは本発明の実施例の工程図、第2図A−E
は従来例の製造工程図である。
主な符号
1:Si基板
2 : S i02膜
3:5i02膜
4:拡散窓
5:埋込拡散層
6:裏面拡散層
7:裏面波rit層
8:エピタキシャル成長層Figure 1 A-E is a process diagram of an embodiment of the present invention, Figure 2 A-E
is a manufacturing process diagram of a conventional example. Main code 1: Si substrate 2: Si02 film 3: 5i02 film 4: Diffusion window 5: Buried diffusion layer 6: Back diffusion layer 7: Back surface wave RIT layer 8: Epitaxial growth layer
Claims (1)
散により埋込拡散層を形成する工程、該半導体基板の一
主面側表面を保護膜で覆う工程、 該半導体基板の裏面側の不純物拡散層を除去する工程、 前記一主面側の保護膜及び拡散マスクを除去する工程、 該一主面上にエピタキシャル成長層を形成する工程、 の各工程を有することを特徴とするエピタキシャル成長
方法。[Claims] A step of forming a diffusion mask on one main surface side of a semiconductor substrate and forming a buried diffusion layer by selective diffusion, a step of covering the one main surface side of the semiconductor substrate with a protective film. The method includes the following steps: removing an impurity diffusion layer on the back side of the semiconductor substrate, removing a protective film and a diffusion mask on the one main surface, and forming an epitaxial growth layer on the one main surface. Characteristic epitaxial growth method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16331185A JPS6224616A (en) | 1985-07-24 | 1985-07-24 | Epitaxial growth method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16331185A JPS6224616A (en) | 1985-07-24 | 1985-07-24 | Epitaxial growth method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6224616A true JPS6224616A (en) | 1987-02-02 |
Family
ID=15771417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16331185A Pending JPS6224616A (en) | 1985-07-24 | 1985-07-24 | Epitaxial growth method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6224616A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100790725B1 (en) | 2006-12-20 | 2008-01-02 | 동부일렉트로닉스 주식회사 | A method for fabricating a semiconductor |
-
1985
- 1985-07-24 JP JP16331185A patent/JPS6224616A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100790725B1 (en) | 2006-12-20 | 2008-01-02 | 동부일렉트로닉스 주식회사 | A method for fabricating a semiconductor |
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