JPH08111409A - Manufacturing for semiconductor device - Google Patents

Manufacturing for semiconductor device

Info

Publication number
JPH08111409A
JPH08111409A JP24636194A JP24636194A JPH08111409A JP H08111409 A JPH08111409 A JP H08111409A JP 24636194 A JP24636194 A JP 24636194A JP 24636194 A JP24636194 A JP 24636194A JP H08111409 A JPH08111409 A JP H08111409A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
film
oxide film
semiconductor
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24636194A
Other languages
Japanese (ja)
Inventor
Hajime Nakajima
元 中島
Norio Hashimoto
規生 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP24636194A priority Critical patent/JPH08111409A/en
Publication of JPH08111409A publication Critical patent/JPH08111409A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To provide a manufacturing method for a semiconductor device in a CVD process, in which a warp in semiconductor wafer is prevented in a heating process and a uniform film formation step or a uniform treatment step is carried out. CONSTITUTION: In a manufacturing method for a semiconductor device, a film formation step and an etching step are carried out to form a semiconductor element on a semiconductor wafer 1. After that, the semiconductor wafer 1 is diced. At least an oxide film 1a made of the same material as the wafer 1 is formed on the rear face of the semiconductor wafer 1 before a CVD film formation step on a face of the semiconductor wafer 1. The oxide film 1a on the rear face of the semiconductor wafer 1 is left as it is still after a last film formation step is carried out in the CVD method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製法に関す
る。さらに詳しくは、CVD法などの高温状態で成膜す
る際に半導体ウェハの反りに基因する成膜ムラなどの処
理ムラをなくする半導体装置の製法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device that eliminates process unevenness such as film unevenness due to warpage of a semiconductor wafer when forming a film in a high temperature state such as a CVD method.

【0002】[0002]

【従来の技術】ICなどの半導体装置は一般につぎのよ
うに製造されている。すなわち、たとえば直径が6イン
チまたは5インチなどの半導体ウェハにエピタキシャル
成長やCVD法などによる成膜工程、ホトレジストの塗
布、露光、現像、エッチングなどによる一連のフォトリ
ソグラフィ技術によるパターニング、イオン注入などの
各プロセスを経て1枚のウェハに複数個の同じ半導体素
子が形成される。そして半導体ウェハでの各プロセスが
完了したのち、半導体ウェハをダイシングして各チップ
に分離し、そのチップをリードフレームなどにボンディ
ングし、モールドすることにより半導体装置が製造され
ている。
2. Description of the Related Art Semiconductor devices such as ICs are generally manufactured as follows. That is, each process such as a film forming process on a semiconductor wafer having a diameter of 6 inches or 5 inches by epitaxial growth or a CVD method, patterning by a series of photolithography techniques such as photoresist coating, exposure, development, etching, and ion implantation. After that, a plurality of the same semiconductor elements are formed on one wafer. After each process on the semiconductor wafer is completed, the semiconductor wafer is diced to be separated into individual chips, and the chips are bonded to a lead frame or the like and molded to manufacture a semiconductor device.

【0003】前述の半導体ウェハは半導体単結晶の塊り
であるインゴットを薄いウェハに切り出して形成される
が、各半導体装置の目的に適した厚さに半導体ウェハが
切削研磨されたり、切り出しによるウェハ表面の粗面を
平滑にするため研磨剤によるラッピングやポリシングが
行われる。厚さ調整段階では切削や化学的処理、比較的
粗い研磨剤を用いた研磨などが行われ、半導体ウェハの
表面側はのちのエピタキシャル成長や成膜などのため、
細かい研磨剤を用いた鏡面仕上にされている。したがっ
て半導体ウェハは一般に表面側は鏡面状態で裏面側は鏡
面に至らず比較的粗い面になっている。
The above-mentioned semiconductor wafer is formed by cutting an ingot, which is a lump of semiconductor single crystals, into a thin wafer. The semiconductor wafer is cut and polished to a thickness suitable for the purpose of each semiconductor device, or a wafer obtained by cutting. Lapping and polishing with an abrasive are performed to smooth the rough surface. In the thickness adjustment stage, cutting, chemical treatment, polishing with a relatively rough abrasive, etc. are performed, and the surface side of the semiconductor wafer is for epitaxial growth or film formation later, so
It is mirror-finished with a fine abrasive. Therefore, in general, a semiconductor wafer has a mirror surface on the front surface and a relatively rough surface on the back surface that does not reach the mirror surface.

【0004】[0004]

【発明が解決しようとする課題】前述のように、半導体
ウェハは表面側と裏面側とでその仕上面が異なり、加熱
プロセスで温度が上がると裏面側の粗面に引張りの熱応
力が加わる。そのため、たとえばCVD工程で400℃
程度にし成膜するばあい、図3に示されるように、半導
体ウェハ1は下が凸となるように反る。この反りは成膜
時に反応管の外から見ると肉眼ではっきりと確認できる
程大きな反りになる。そのため半導体ウェハ1の周囲は
400℃程度に加熱されたサセプタ2から浮き上がり半
導体ウェハ1の周囲の温度が低くなるとともに、また反
応ガス3の流動範囲が狭くなる。その結果半導体ウェハ
1の周囲では膜の成長が遅くなり成膜しにくく、端部で
はほとんど成膜されないばあいもあり、半導体ウェハ表
面の膜厚のムラが、たとえば0.1〜0.2μmと大き
くなる。そのため、ダイシングして各チップに分離した
ときチップの不良が発生して歩留りが低下したり、信頼
性が低下するという問題がある。
As described above, the semiconductor wafer has different finishing surfaces on the front surface side and the back surface side, and when the temperature rises in the heating process, tensile thermal stress is applied to the rough surface on the back surface side. Therefore, for example, 400 ° C in the CVD process
When the film is formed to a certain degree, the semiconductor wafer 1 is warped so that the bottom is convex as shown in FIG. This warp is so large that it can be clearly confirmed with the naked eye when viewed from outside the reaction tube during film formation. Therefore, the periphery of the semiconductor wafer 1 floats up from the susceptor 2 heated to about 400 ° C., and the temperature around the semiconductor wafer 1 becomes low, and the flow range of the reaction gas 3 becomes narrow. As a result, the growth of the film is slow around the semiconductor wafer 1 and it is difficult to form a film, and there is a case where the film is hardly formed at the edge. The unevenness of the film thickness on the surface of the semiconductor wafer is, for example, 0.1 to 0.2 μm. growing. Therefore, when the chips are diced and separated into chips, there arises a problem that chip defects occur, yield decreases, and reliability decreases.

【0005】本発明はこのような問題を解決し、CVD
工程など半導体ウェハの加熱プロセスにおいて、半導体
ウェハの反りを極力抑え、均一な成膜や処理をできる半
導体装置の製法を提供することを目的とする。
The present invention solves such a problem, and CVD
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress the warp of the semiconductor wafer as much as possible in a heating process of the semiconductor wafer such as steps and can perform uniform film formation and processing.

【0006】[0006]

【課題を解決するための手段】本発明者らは、前述の加
熱プロセスの際の半導体ウェハの反りに基因する成膜の
バラツキなど加熱プロセスにおける半導体ウェハ表面の
処理のバラツキをなくするため鋭意検討を重ねた結果、
半導体ウェハの裏面にSiO2 などからなる酸化膜を形
成することにより、粗面に基因する熱応力の引張力を相
殺する圧縮力が裏面側に働き、加熱時にも半導体ウェハ
の反りが殆ど生じなく、たとえばCVD法の成膜工程に
おいても半導体ウェハの中心部と周辺部で均一な膜厚が
えられることを見出した。
DISCLOSURE OF THE INVENTION The inventors of the present invention have made diligent studies in order to eliminate variations in the treatment of the surface of a semiconductor wafer in the heating process, such as variations in film formation due to the warp of the semiconductor wafer in the above heating process. As a result of
By forming an oxide film made of SiO 2 etc. on the back surface of the semiconductor wafer, a compressive force that cancels the tensile force of thermal stress due to the rough surface works on the back surface side, and the warp of the semiconductor wafer hardly occurs during heating. It was found that a uniform film thickness can be obtained in the central portion and the peripheral portion of the semiconductor wafer even in the film forming process of the CVD method, for example.

【0007】本発明の半導体装置の製法は、半導体ウェ
ハに少なくともCVD法による成膜工程を含む処理を施
して半導体素子を形成し、該半導体素子が形成された半
導体ウェハをダイシングして半導体装置を製造する方法
であって、前記半導体ウェハの表面に少なくとも最初の
CVD法による成膜を行う工程の前に前記半導体ウェハ
の裏面に該半導体ウェハ材料の酸化膜を形成し、該半導
体ウェハ裏面の酸化膜を少なくとも最後のCVD法によ
る成膜工程のあとまでそのまま残存させることを特徴と
する。
According to the method of manufacturing a semiconductor device of the present invention, a semiconductor device is formed by subjecting a semiconductor wafer to a process including at least a film forming step by a CVD method, and dicing the semiconductor wafer on which the semiconductor device is formed to form a semiconductor device. A method of manufacturing, wherein an oxide film of the semiconductor wafer material is formed on the back surface of the semiconductor wafer before at least the first step of forming a film by the CVD method on the front surface of the semiconductor wafer, and the back surface of the semiconductor wafer is oxidized. It is characterized in that the film is left as it is at least until after the last film forming step by the CVD method.

【0008】前記半導体ウェハの裏面の前記酸化膜を前
記半導体ウェハの表面にマスクとして形成する酸化膜と
同時に熱酸化法により形成することが、特別の成膜工程
を必要とせず、エッチング時などは保護膜を裏面の酸化
膜に付着しておくだけでよいため、沢山の加熱プロセス
があるばあいでもその都度裏面の酸化膜を設ける必要が
なく好ましい。
When the oxide film on the back surface of the semiconductor wafer is formed simultaneously with the oxide film formed as a mask on the front surface of the semiconductor wafer by the thermal oxidation method, no special film forming step is required, and when etching or the like is performed. Since it is only necessary to attach the protective film to the oxide film on the back surface, even if there are many heating processes, it is not necessary to provide the oxide film on the back surface each time, which is preferable.

【0009】[0009]

【作用】本発明によれば、半導体ウェハの粗面である裏
面に酸化膜を形成しているため、粗面による熱応力に基
づく半導体ウェハ裏面の引張力と、シリコンなどからな
る半導体ウェハおよびSiO2 などからなる酸化膜との
熱膨脹係数の差に基づく酸化膜の圧縮力とが相殺されて
CVD工程などの加熱プロセスにおける高温時に半導体
ウェハの反りがなくなる。
According to the present invention, since the oxide film is formed on the back surface which is the rough surface of the semiconductor wafer, the tensile force on the back surface of the semiconductor wafer based on the thermal stress due to the rough surface and the semiconductor wafer made of silicon or the like and the SiO film are formed. The compressive force of the oxide film based on the difference in thermal expansion coefficient from the oxide film of 2 or the like is offset, so that the semiconductor wafer does not warp at a high temperature in a heating process such as a CVD process.

【0010】その結果、たとえばCVD工程などで成膜
するときでも、半導体ウェハは全面でサセプタに接触
し、温度が均一になるとともに、周囲の反応ガスの流動
状況も均一になり、均一な膜厚で成膜することができ
る。
As a result, even when a film is formed in, for example, a CVD process, the semiconductor wafer comes into contact with the susceptor over the entire surface, the temperature becomes uniform, and the flow state of the surrounding reaction gas becomes uniform, so that the uniform film thickness is obtained. Can be used to form a film.

【0011】[0011]

【実施例】つぎに図面を参照しながら本発明の半導体装
置の製法について説明する。図1は本発明の半導体装置
の製法のCVD工程の概略説明図、図2は半導体ウェハ
の裏面に酸化膜を設けたときの酸化膜の厚さと反りとの
関係を示す図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a method of manufacturing a semiconductor device of the present invention will be described with reference to the drawings. FIG. 1 is a schematic explanatory view of a CVD process in a method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a diagram showing a relationship between the thickness of an oxide film and a warp when the oxide film is provided on the back surface of a semiconductor wafer.

【0012】前述のように、本発明者らはCVD法によ
る成膜工程の膜厚などが均一にならない原因について調
べた結果、400℃程度の高温で成膜する際に図3に示
されるように、半導体ウェハ1の周囲が反り上がり、半
導体ウェハ1の周縁の温度が低下し、さらに雰囲気の反
応ガスも反応領域が狭くなって充分でないことに基因し
ていることを見出した。本発明者らは成膜時にこの反り
をなくするため、さらに鋭意検討を重ねた結果、反りの
原因が半導体ウェハの表裏面の粗さの差に基づくもので
あることを見出し、半導体ウェハの裏面に該半導体ウェ
ハの材料より熱膨張係数が小さくなる酸化膜を設けるこ
とにより、半導体ウェハの裏面には粗面に基づく引張力
と熱膨張係数の小さい酸化膜に基づく圧縮力とが働き、
両者が相殺されて加熱時の半導体ウェハの反りを抑制で
きることを見出した。
As described above, the inventors of the present invention have investigated the cause of non-uniformity of the film thickness in the film forming process by the CVD method, and as a result, when forming a film at a high temperature of about 400 ° C., as shown in FIG. It was also found that the reason is that the circumference of the semiconductor wafer 1 is warped, the temperature of the peripheral edge of the semiconductor wafer 1 is lowered, and the reaction gas in the atmosphere is not sufficient because the reaction region is narrowed. In order to eliminate this warpage during film formation, the present inventors have conducted further diligent studies, and as a result, found that the cause of the warpage is due to the difference in roughness between the front and back surfaces of the semiconductor wafer, and By providing an oxide film having a thermal expansion coefficient smaller than that of the material of the semiconductor wafer, the tensile force based on the rough surface and the compression force based on the oxide film with a small thermal expansion coefficient work on the back surface of the semiconductor wafer,
It has been found that the two are offset and the warp of the semiconductor wafer during heating can be suppressed.

【0013】加熱時の半導体ウェハの反りを測定するこ
とはできないが、従来の5インチウェハを用いて400
℃程度でPSG膜をCVD法により成膜するするばあ
い、反応管の外から肉眼で見て明らかに周囲が反り上が
っているのを確認することができ、1〜2mm程度はサ
セプタから反り上がっていた。一方、図1に示されるよ
うに、半導体ウェハ1の裏面に酸化膜1aを設け、その
厚さを種々変えて成膜したときの半導体ウェハ1の反り
を調べた結果、図2に示す結果がえられた。すなわち、
酸化膜1aは半導体ウェハ1のプロセスの初期に次工程
のパターニングのため半導体ウェハ1の表面にSiO2
などの酸化膜を1000〜1200℃程度で熱酸化法に
より形成するが、その際に裏面に形成された酸化膜1a
をあとのエッチング工程などのときにレジストなどを塗
布して保護することにより除去されないようにして残す
もので、この熱酸化の時間を制御することにより酸化膜
の厚さを変えたものである。図2(a)は酸化膜1aを
形成したのち、常温においての半導体ウェハ1の反りを
測定して酸化膜1aの厚さに対する関係を示したグラフ
で、図2(b)は、酸化膜の厚さを変えたとき400℃
程度でPSG膜を成膜するCVD工程における半導体ウ
ェハ1の反りを、反応管の外からの目視による観察によ
り傾向として図に示したものである。
Although it is not possible to measure the warp of a semiconductor wafer during heating, 400
When the PSG film is formed by the CVD method at about ℃, it can be confirmed visually that the surrounding area is warped from the outside of the reaction tube, and about 1 to 2 mm is warped from the susceptor. Was there. On the other hand, as shown in FIG. 1, an oxide film 1a is provided on the back surface of the semiconductor wafer 1, and the warp of the semiconductor wafer 1 when the film is formed with various thicknesses is examined. As a result, the results shown in FIG. I got it. That is,
The oxide film 1a is formed on the surface of the semiconductor wafer 1 by SiO 2 on the surface of the semiconductor wafer 1 for patterning in the next step at the beginning of the process.
An oxide film such as is formed by a thermal oxidation method at about 1000 to 1200 ° C., but the oxide film 1a formed on the back surface at that time is formed.
Is applied and protected by a resist or the like in a later etching step so as not to be removed, and the thickness of the oxide film is changed by controlling the time of this thermal oxidation. FIG. 2A is a graph showing the relationship between the thickness of the oxide film 1a by measuring the warp of the semiconductor wafer 1 at room temperature after forming the oxide film 1a, and FIG. 400 ℃ when changing the thickness
The warp of the semiconductor wafer 1 in the CVD step of forming the PSG film in a certain degree is shown in the figure as a tendency by visual observation from outside the reaction tube.

【0014】前述のように、酸化膜1aの形成は熱酸化
法により、1000℃程度の高温で形成されているた
め、常温では酸化膜1aの厚さが0.6μm程度以上で
は酸化膜1aの方が半導体ウェハ1より収縮が小さく、
下側が凸になるようにわん曲する。一方、酸化膜1aの
薄い方では酸化膜1aの収縮力は働かず、上側に凸とな
るようにわん曲する。この半導体ウェハ1をCVD法で
成膜するため400℃程度に上げると、図2(b)に示
されるように、酸化膜1aが薄いときは下に凸の反りが
大きく現われるが、酸化膜1aの厚さが0.6μm程度
以上では肉眼で見て反りがほとんど観察されず、平らな
半導体ウェハ1の状態で成膜することができる。
As described above, since the oxide film 1a is formed by the thermal oxidation method at a high temperature of about 1000 ° C., the oxide film 1a is formed when the thickness of the oxide film 1a is about 0.6 μm or more at room temperature. Shrinkage is smaller than the semiconductor wafer 1,
Bend it so that the bottom is convex. On the other hand, when the oxide film 1a is thinner, the contraction force of the oxide film 1a does not work, and the oxide film 1a is bent so as to be convex upward. When this semiconductor wafer 1 is heated to about 400 ° C. to form a film by the CVD method, as shown in FIG. 2B, when the oxide film 1a is thin, a large downward warp appears, but the oxide film 1a When the thickness is about 0.6 μm or more, almost no warp is observed with the naked eye, and a film can be formed in a flat semiconductor wafer 1.

【0015】本発明の半導体装置の製法は以上の知見に
基づいて行われたもので、つぎに具体的に説明する。
The method of manufacturing the semiconductor device of the present invention was carried out on the basis of the above findings, and will be specifically described below.

【0016】図1は本発明のCVD工程など熱プロセス
における半導体ウェハ1の説明図である。図1において
1は、たとえばシリコンなどからなる厚さが200〜2
50μm、5インチの半導体ウェハで、その裏面には、
たとえばSiO2 などからなる酸化膜1aが0.7〜
1.0μmの厚さに形成されている。
FIG. 1 is an explanatory view of a semiconductor wafer 1 in a thermal process such as a CVD process of the present invention. In FIG. 1, 1 has a thickness of 200 to 2 made of, for example, silicon.
It is a semiconductor wafer of 50 μm and 5 inches.
For example, the oxide film 1a made of SiO 2 has a thickness of 0.7 to
It is formed to a thickness of 1.0 μm.

【0017】酸化膜1aが形成される前の半導体ウェハ
1は前述のように、インゴットから切り出されたのち、
表面は鏡面になるように研磨され、裏面はそれより粗く
研磨されている。また酸化膜1aは0.7〜1.0μm
の厚さに形成されている。この酸化膜1aの形成は、前
述の半導体ウェハ1が洗浄されたのち、次工程のマスキ
ングのため、1000〜1200℃のO2 またはO2
2 の混合雰囲気で50分〜100分間熱処理をするこ
とにより、表面および裏面を含む全面に形成される酸化
膜を用いることができるが、別の工程で熱酸化法または
CVD法などにより形成されてもよい。
The semiconductor wafer 1 before the oxide film 1a is formed is cut out from the ingot as described above,
The front surface is polished to be a mirror surface, and the back surface is rougher. The oxide film 1a has a thickness of 0.7 to 1.0 μm.
Is formed to a thickness of. In order to form the oxide film 1a, after the semiconductor wafer 1 is cleaned, heat treatment is performed at 1000 to 1200 ° C. in O 2 or a mixed atmosphere of O 2 and H 2 for 50 to 100 minutes after masking in the next step. By doing so, an oxide film formed on the entire surface including the front surface and the back surface can be used, but it may be formed by a thermal oxidation method or a CVD method in another step.

【0018】そののち表面側の酸化膜をパターニングす
るため、レジストの塗布、露光、現像処理ののち酸化膜
のエッチングが行われるが、そのエッチングの際裏面の
酸化膜1aの全面にレジストなどを塗布しておきエッチ
ング液で除去されないようにする。その後の工程におい
ても酸化膜1aが処理液で除去される工程があるときは
除去されないように保護膜を設けて、少なくとも最終的
なCVD法による成膜工程が終了するまで裏面の酸化膜
1aを保持する。
After that, in order to pattern the oxide film on the front surface side, the oxide film is etched after the resist is applied, exposed and developed. At the time of the etching, a resist or the like is applied on the entire surface of the oxide film 1a on the back surface. Set it aside so that it is not removed by the etching solution. Also in the subsequent steps, if there is a step of removing the oxide film 1a with the processing liquid, a protective film is provided so as not to remove the oxide film 1a, and the oxide film 1a on the back surface is removed at least until the film forming step by the final CVD method is completed. Hold.

【0019】半導体のウェハプロセスにおいて、前述の
熱酸化工程の後、エッチング工程、拡散工程などを経
て、たとえば保護膜およびケッタリングのためのPSG
膜をCVD法により成膜する工程があるが、この成膜の
際、前述の半導体ウェハ1の裏面に酸化膜1aが形成さ
れた状態でサセプタ2上に載置して図示しない反応管内
に設置し、サセプタ2を400℃程度に加熱して反応ガ
ス3であるSiH4 とO2 をドーパントガスとともに導
入することによりガスが反応して半導体ウェハ1の表面
上に成膜される。この際、半導体ウェハ1の裏面に酸化
膜1aが0.7〜1.0μmの厚さに形成されているた
め、前述の図2(b)に示されるように、400℃程度
に加熱された状態で反りはほとんど発生せず、均一厚さ
のPSG膜が成膜された。実際に成膜後の半導体ウェハ
内で周縁部と中心部のあいだで5カ所の測定点により成
膜厚さを測定した結果、0.01〜0.02μmの範囲
に納まり、従来の0.1〜0.2μmのバラツキに対し
て格段の改良がみられた。そののち、通常の半導体の製
造プロセスを続け、コンタクトのエッチング工程時に裏
面の酸化膜も除去し、裏面研削したのちダイシングし、
各チップに分離してリードフレームにボンディングし、
モールドすることにより半導体装置がえられる。
In the semiconductor wafer process, after the above-mentioned thermal oxidation step, through an etching step, a diffusion step, etc., for example, a protective film and PSG for kettering.
There is a step of forming a film by a CVD method. At the time of this film formation, the oxide film 1a is formed on the back surface of the semiconductor wafer 1 and placed on the susceptor 2 and installed in a reaction tube (not shown). Then, the susceptor 2 is heated to about 400 ° C. and SiH 4 and O 2 which are reaction gases 3 are introduced together with the dopant gas, whereby the gases react with each other to form a film on the surface of the semiconductor wafer 1. At this time, since the oxide film 1a was formed on the back surface of the semiconductor wafer 1 to a thickness of 0.7 to 1.0 μm, it was heated to about 400 ° C. as shown in FIG. 2B. In the state, almost no warpage occurred, and a PSG film having a uniform thickness was formed. As a result of actually measuring the film-forming thickness at five measuring points between the peripheral portion and the central portion in the semiconductor wafer after the film-forming, it was within the range of 0.01 to 0.02 μm, Significant improvement was observed for variations of up to 0.2 μm. After that, the normal semiconductor manufacturing process is continued, the oxide film on the back surface is also removed during the contact etching step, the back surface is ground, and then dicing,
Separated into each chip and bonded to the lead frame,
A semiconductor device is obtained by molding.

【0020】以上の説明ではCVD法による成膜工程に
おいて半導体ウェハ1の裏面の酸化膜1aの効用につい
て述べたが、CVD法以外の熱反応による成膜工程など
においても同様に処理時の半導体ウェハ1の反りを防止
することができ、効果がある。ただし、この処理時の温
度により適切な酸化膜1aの厚さに選定するのが好まし
い、すなわち処理温度が高くなる程厚い方が好ましく、
低い温度になれば薄い方が好ましい。しかし、熱プロセ
スの中でもとくに問題となるのはCVD工程であり、そ
のCVD行程の温度である400℃程度に好適な酸化膜
の厚さ、すなわち0.7〜1.0μm程度に形成するの
が最も好ましい。
In the above description, the effect of the oxide film 1a on the back surface of the semiconductor wafer 1 in the film forming process by the CVD method has been described, but the semiconductor wafer at the time of processing is similarly applied to the film forming process by a thermal reaction other than the CVD method. It is possible to prevent the warp of No. 1 and it is effective. However, it is preferable to select an appropriate thickness of the oxide film 1a according to the temperature at the time of this processing, that is, the thicker the processing temperature is, the thicker it is.
The lower the temperature, the better the thinness. However, the CVD process is particularly problematic in the thermal process, and it is preferable to form the oxide film with a thickness suitable for the temperature of the CVD process of about 400 ° C., that is, about 0.7 to 1.0 μm. Most preferred.

【0021】また、半導体ウェハ1が薄くなると反りが
激しくなり酸化膜1aの厚さも厚くする必要があり、酸
化膜形成前の半導体ウェハ(サブウェハ)1の厚さが、
たとえば150〜200μm程度になると前述の400
℃程度の熱処理工程においても1.0〜1.3μm程度
の酸化膜1aを形成することにより、均一厚さの成膜を
することができる。
Further, when the semiconductor wafer 1 becomes thin, the warp becomes severe, and the thickness of the oxide film 1a needs to be made thick. The thickness of the semiconductor wafer (sub-wafer) 1 before the oxide film is formed is
For example, when it becomes about 150 to 200 μm, the above 400
By forming the oxide film 1a having a thickness of about 1.0 to 1.3 μm even in the heat treatment step at about ° C, it is possible to form a film having a uniform thickness.

【0022】[0022]

【発明の効果】本発明によれば、半導体ウェハの裏面に
酸化膜を形成しているので、CVD工程など熱処理プロ
セスにおける半導体ウェハの反りが問題とならず、均一
厚さの成膜など熱処理プロセスを半導体ウェハ表面の全
面で均一に行うことができる。その結果、製品歩留りが
向上するとともに品質が一定した半導体装置がえられ
る。また、この傾向はとくに半導体ウェハが薄くなるに
つれて顕著となる。
According to the present invention, since the oxide film is formed on the back surface of the semiconductor wafer, the warp of the semiconductor wafer in the heat treatment process such as the CVD process does not become a problem, and the heat treatment process such as film formation with a uniform thickness is performed. Can be performed uniformly on the entire surface of the semiconductor wafer. As a result, a product yield is improved and a semiconductor device having a constant quality can be obtained. In addition, this tendency becomes more remarkable as the semiconductor wafer becomes thinner.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製法のCVD工程におけ
る説明図である。
FIG. 1 is an explanatory diagram in a CVD process of a method for manufacturing a semiconductor device of the present invention.

【図2】半導体ウェハの裏面に設けられる酸化膜の厚さ
と反りの関係を示す図である。
FIG. 2 is a diagram showing the relationship between the thickness and the warp of an oxide film provided on the back surface of a semiconductor wafer.

【図3】従来の製法のCVD工程における説明図であ
る。
FIG. 3 is an explanatory diagram in a CVD process of a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

1 半導体ウェハ 1a 酸化膜 2 サセプタ 3 反応ガス 1 semiconductor wafer 1a oxide film 2 susceptor 3 reaction gas

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェハに少なくともCVD法によ
る成膜工程を含む処理を施して半導体素子を形成し、該
半導体素子が形成された半導体ウェハをダイシングして
半導体装置を製造する方法であって、前記半導体ウェハ
の表面に少なくとも最初のCVD法による成膜を行う工
程の前に前記半導体ウェハの裏面に該半導体ウェハ材料
の酸化膜を形成し、該半導体ウェハ裏面の酸化膜を少な
くとも最後のCVD法による成膜工程のあとまでそのま
ま残存させることを特徴とする半導体装置の製法。
1. A method of manufacturing a semiconductor device by subjecting a semiconductor wafer to a treatment including at least a film-forming step by a CVD method to form a semiconductor element, and dicing the semiconductor wafer on which the semiconductor element is formed, An oxide film of the semiconductor wafer material is formed on the back surface of the semiconductor wafer before at least the first step of forming a film on the front surface of the semiconductor wafer by the CVD method, and the oxide film on the back surface of the semiconductor wafer is at least the last CVD method. A method for manufacturing a semiconductor device, which is characterized in that the film is left as it is after the film formation step.
【請求項2】 前記半導体ウェハの裏面の前記酸化膜を
前記半導体ウェハの表面にマスクとして形成する酸化膜
と同時に熱酸化法により形成する請求項1記載の半導体
装置の製法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film on the back surface of the semiconductor wafer is formed simultaneously with the oxide film formed on the front surface of the semiconductor wafer as a mask by a thermal oxidation method.
JP24636194A 1994-10-12 1994-10-12 Manufacturing for semiconductor device Pending JPH08111409A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24636194A JPH08111409A (en) 1994-10-12 1994-10-12 Manufacturing for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24636194A JPH08111409A (en) 1994-10-12 1994-10-12 Manufacturing for semiconductor device

Publications (1)

Publication Number Publication Date
JPH08111409A true JPH08111409A (en) 1996-04-30

Family

ID=17147416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24636194A Pending JPH08111409A (en) 1994-10-12 1994-10-12 Manufacturing for semiconductor device

Country Status (1)

Country Link
JP (1) JPH08111409A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6767782B2 (en) 2001-05-11 2004-07-27 Renesas Technology Corp. Manufacturing method of semiconductor device
JP2014216474A (en) * 2013-04-25 2014-11-17 コバレントマテリアル株式会社 Nitride semiconductor substrate
JP2019504490A (en) * 2015-12-16 2019-02-14 オステンド・テクノロジーズ・インコーポレーテッド Method for improving wafer flatness and bonded wafer assembly made by the method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6767782B2 (en) 2001-05-11 2004-07-27 Renesas Technology Corp. Manufacturing method of semiconductor device
JP2014216474A (en) * 2013-04-25 2014-11-17 コバレントマテリアル株式会社 Nitride semiconductor substrate
US9536955B2 (en) 2013-04-25 2017-01-03 Coorstek Kk Nitride semiconductor substrate
JP2019504490A (en) * 2015-12-16 2019-02-14 オステンド・テクノロジーズ・インコーポレーテッド Method for improving wafer flatness and bonded wafer assembly made by the method
JP2022008584A (en) * 2015-12-16 2022-01-13 オステンド・テクノロジーズ・インコーポレーテッド Method for improving wafer flatness and joined wafer assembly created thereby

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