JPS62243344A - Multilayer interconnection electrode film structure semiconductor device - Google Patents
Multilayer interconnection electrode film structure semiconductor deviceInfo
- Publication number
- JPS62243344A JPS62243344A JP8649586A JP8649586A JPS62243344A JP S62243344 A JPS62243344 A JP S62243344A JP 8649586 A JP8649586 A JP 8649586A JP 8649586 A JP8649586 A JP 8649586A JP S62243344 A JPS62243344 A JP S62243344A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode film
- wiring electrode
- semiconductor device
- interlayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 238000010884 ion-beam technique Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241000244317 Tillandsia usneoides Species 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、多層配線電極膜構造を有する半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring electrode film structure.
従来の技術
従来、多層配線電極膜構造を有する半導体装置は、概略
、第２図に示す断面形状の構成である。2. Description of the Related Art Conventionally, a semiconductor device having a multilayer wiring electrode film structure has a cross-sectional configuration roughly shown in FIG.
２ベーノ
上部配線電極膜２と下部配線電極膜４は、層間膜３と直
接、接触していることが多い。そして、この層間膜３に
よって、上部２と下部４の配線電極膜が絶縁されている
。The two-vane upper wiring electrode film 2 and the lower wiring electrode film 4 are often in direct contact with the interlayer film 3. The interlayer film 3 insulates the upper 2 and lower 4 wiring electrode films.
発明が解決しようとする問題点
上で述べたように、層間膜と上部あるいは下部配線電極
膜とは直接、接触しているため、以後の半導体製造プロ
セスにおいて、たとえば、層間膜や配線電極膜のシンタ
ーなど熱処理工程を経た際に、層間膜と配線電極膜の熱
膨張率の違いから生じた応力によって、配線電極膜に断
線が生じ、デバイスを不良に至らしめる結果となる。本
発明は、このような問題点を解決することを目的として
いる。Problems to be Solved by the Invention As mentioned above, since the interlayer film and the upper or lower wiring electrode film are in direct contact with each other, in the subsequent semiconductor manufacturing process, for example, the interlayer film or the wiring electrode film may When subjected to a heat treatment process such as sintering, the stress generated due to the difference in thermal expansion coefficient between the interlayer film and the wiring electrode film causes disconnection in the wiring electrode film, resulting in a defective device. The present invention aims to solve these problems.
問題点を解決するだめの手段
前記の問題点を解決するために本発明は、層間絶縁膜が
配線電極膜と同一又は近似の熱膨張率を有する事を特徴
とする多層配線電極膜構造半導体装置を提供する。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a multilayer wiring electrode film structure semiconductor device characterized in that the interlayer insulating film has the same or similar coefficient of thermal expansion as the wiring electrode film. I will provide a.
作 用
３ヘーノ
層間膜を加工し、層間膜に接触する配線電極膜と類似あ
るいは、近い熱膨張率をもった層間膜に変質させること
により、熱膨張率の違いから生じた応力のために、配線
電極膜が断線するというデバイスの致命的な不良を排除
することができる。Effect 3 By processing the Heno interlayer film and transforming it into an interlayer film with a coefficient of thermal expansion similar to or close to that of the wiring electrode film that contacts the interlayer film, stress caused by the difference in coefficient of thermal expansion, It is possible to eliminate fatal device defects such as disconnection of the wiring electrode film.
実施例
第１図に、本発明実施例を説明する多層配線電極膜の断
面図を示す。下層配線電極膜４としてアルミニューム（
Ａｔ）膜を形成した後、層間膜３として、プラズマシリ
コンナイトライド膜を成長させる。その後、プラズマシ
リコンナイトライド膜に、直径１μｍφ以下、長さがプ
ラズマシリコンナイトライド膜厚と同じか短かい穴を、
細く絞ったイオンビーム、あるいは、レーザービームを
プラズマシリコンナイトライド膜に照射し、形成する。Embodiment FIG. 1 shows a cross-sectional view of a multilayer wiring electrode film explaining an embodiment of the present invention. Aluminum (
After forming the At) film, a plasma silicon nitride film is grown as the interlayer film 3. After that, a hole with a diameter of 1 μm or less and a length equal to or shorter than the plasma silicon nitride film thickness is inserted into the plasma silicon nitride film.
It is formed by irradiating a plasma silicon nitride film with a narrowly focused ion beam or laser beam.
その後、上層配線電極膜２を形成し、通常の半導体製造
プロセスを経て、デバイスを製作する。Thereafter, an upper wiring electrode film 2 is formed, and a device is manufactured through a normal semiconductor manufacturing process.
又この様にして形成された穴に単二又は複数種類の不純
物イオンを充填する事によっても同様の効果が得られる
。このようにして得られた半導体装置を製造プロセスを
経て熱処理工程を通過した後に、光学顕微鏡等で観察あ
るいは、電気的測定を行なった。それらの結果からは、
配線電極膜の断線による不良の発生は検知出来なかった
。A similar effect can also be obtained by filling the holes formed in this manner with single or multiple types of impurity ions. After the semiconductor device thus obtained was subjected to a manufacturing process and a heat treatment step, it was observed using an optical microscope or the like, or electrical measurements were performed. From those results,
No defects due to disconnection of the wiring electrode film could be detected.
発明の効果
本発明によれば、眉間膜に形成した複数の穴によって層
間膜と配線電極膜との接触面積が減少すると共に、穴そ
のものによって熱処理工程を通過する際、又は通過した
後に生じる応力を緩和減少させ、その層間膜と直接接触
した配線電極膜に影響を与えず、配線電極膜の断線を防
止したものである。このことにより、半導体デバイス製
造の歩留を高め、品質の向上を計ることが出来た。Effects of the Invention According to the present invention, the contact area between the interlayer film and the wiring electrode film is reduced by the plurality of holes formed in the glabellar film, and the stress generated during or after passing through the heat treatment process is reduced by the holes themselves. This reduces relaxation, does not affect the wiring electrode film that is in direct contact with the interlayer film, and prevents disconnection of the wiring electrode film. This made it possible to increase the yield of semiconductor device manufacturing and improve quality.
第１図は、本発明実施例を説明する多層配線電極膜の断
面爾す＃＃ 第２図は、従来例を説明する断面図τ゛
品う。
１・・・・・・表面保護膜、２・・・・・・上層配線電
極膜、３・・・・・・層間絶縁膜、４・・・・・・下層
配線電極膜、６・・・・・・半導体基板、６・・・・・
・穴あるいは、不純物層。FIG. 1 is a cross-sectional view of a multilayer wiring electrode film for explaining an embodiment of the present invention. FIG. 2 is a cross-sectional view for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Surface protection film, 2... Upper wiring electrode film, 3... Interlayer insulating film, 4... Lower wiring electrode film, 6... ...Semiconductor substrate, 6...
- Hole or impurity layer.
Claims (3)
率を有する事を特徴とする多層配線電極膜構造半導体装
置。(1) A multilayer wiring electrode film structure semiconductor device characterized in that the interlayer insulating film has the same coefficient of thermal expansion as or similar to that of the wiring electrode film.
有する特許請求の範囲第１項記載の多層配線電極膜構造
半導体装置。(2) A multilayer wiring electrode film structure semiconductor device according to claim 1, wherein the interlayer insulating film has a plurality of holes having a desired shape and size.
を１種類以上の不純物で充填した特許請求の範囲第１項
記載の多層配線電極膜構造半導体装置。(3) A multilayer wiring electrode film structure semiconductor device according to claim 1, wherein a plurality of holes of a desired shape and size in an interlayer insulating film are filled with one or more types of impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8649586A JPS62243344A (en) | 1986-04-15 | 1986-04-15 | Multilayer interconnection electrode film structure semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8649586A JPS62243344A (en) | 1986-04-15 | 1986-04-15 | Multilayer interconnection electrode film structure semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62243344A true JPS62243344A (en) | 1987-10-23 |
Family
ID=13888559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8649586A Pending JPS62243344A (en) | 1986-04-15 | 1986-04-15 | Multilayer interconnection electrode film structure semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62243344A (en) |
-
1986
- 1986-04-15 JP JP8649586A patent/JPS62243344A/en active Pending
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