JPS6130060A - Manufacture of semiconductor fuse element - Google Patents
Manufacture of semiconductor fuse elementInfo
- Publication number
- JPS6130060A JPS6130060A JP15060484A JP15060484A JPS6130060A JP S6130060 A JPS6130060 A JP S6130060A JP 15060484 A JP15060484 A JP 15060484A JP 15060484 A JP15060484 A JP 15060484A JP S6130060 A JPS6130060 A JP S6130060A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- fuse
- film
- forming
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体とスーズ素子の製造方法に関し、特に半
導体記憶装置の冗長回路及びアナログ系の半導体集積回
路装置のトリミング回路に適する半導体ヒユーズ素子の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor and a fuse element, and in particular to a semiconductor fuse element suitable for a redundant circuit of a semiconductor memory device and a trimming circuit of an analog semiconductor integrated circuit device. Regarding the manufacturing method.
（従来技術）
近年、半導体集積回路装置においてはその高密度化、高
集積化の進歩が著しい。この高密度化。(Prior Art) In recent years, there has been remarkable progress in increasing the density and integration of semiconductor integrated circuit devices. This densification.
高集積化は回路構成技術、製造技術の進歩により可能と
なったものではめるが、そのチップ面積は使用素子寸法
の縮小に助けられながらも次第に増加してきている。公
知の如く、半導体集積回路装置の製造においては、チッ
プ面積の増加は同時に製品歩留の低下を伴なうものであ
り、この歩留低下の補償を行なうことが重要な課題とな
りつつある。例えば、半導体記憶回路装置においては、
その不良原因の一要素として記憶セルの１個又は２個の
不良による場合が挙げられるが、この場合、前記不良の
記憶セルを良品の記憶セルと代替することにより不良チ
ップを良品チップにすることが可能な訳である。即ち、
必要な記憶セル以外に予備の記憶セルを準備しておき、
前記不良の記憶セルを含む行又は列の記憶セル対を予備
の良品記憶セル対と置き換えるという冗長回路の概念が
提案されている。この置き換えは、アドンスデコーダ回
路中にヒユーズ素子を挿入しておき、そのヒユーズ素子
を溶断あるいは非溶断とすることにより論理を変更する
こと等により行なわれる。High integration has become possible due to advances in circuit configuration technology and manufacturing technology, but the chip area has gradually increased, aided by the reduction in the size of the elements used. As is well known, in the manufacture of semiconductor integrated circuit devices, an increase in chip area is accompanied by a decrease in product yield, and compensating for this decrease in yield is becoming an important issue. For example, in a semiconductor memory circuit device,
One of the causes of the defect is the case where one or two memory cells are defective. In this case, the defective chip can be made into a non-defective chip by replacing the defective memory cell with a non-defective memory cell. is possible. That is,
Prepare spare memory cells in addition to the memory cells you need.
A redundant circuit concept has been proposed in which a pair of memory cells in a row or column containing the defective memory cell is replaced with a pair of spare good memory cells. This replacement is performed by inserting a fuse element into the admit decoder circuit and changing the logic by making the fuse element blown or not blown.
又、アナログ系の半導体集積回路装置においては、その
装置の製造終了後に製造工程のバラツキによる特性の変
化を補正することが必要となる場合がある。前記補正は
１例えば、増幅器の利得調整やオフセットの８節等であ
るが、この補正は演算増幅器の帰還回路として抵抗とヒ
ユーズ素子との並列接続対より成るトリミング回路を利
用し、前記ヒユーズ素子のいくりかを溶断することによ
り行なわルる。前記冗長回路及びトリミング回路に使用
するヒユーズ素子は通常多結晶シリコン層或は、アルミ
ニウム層で形成され、その溶断はレーザー光の照射エネ
ルギーによって或はヒユーズ素子の両端に電圧を印加す
ることにより発生するジュール熱によって行なわれる。Furthermore, in analog semiconductor integrated circuit devices, it may be necessary to correct changes in characteristics due to variations in the manufacturing process after the device has been manufactured. The above-mentioned correction is, for example, the gain adjustment of the amplifier and the 8th node of the offset. This correction uses a trimming circuit consisting of a parallel-connected pair of a resistor and a fuse element as a feedback circuit of the operational amplifier, and adjusts the fuse element. This is done by fusing some parts. The fuse element used in the redundant circuit and trimming circuit is usually formed of a polycrystalline silicon layer or an aluminum layer, and the fuse element is blown by the irradiation energy of a laser beam or by applying a voltage across the fuse element. It is carried out by Joule heat.
次に、従来のヒユーズ素子の構造に関し、多結晶シリコ
ン層を溶断部の材料とする半導体ヒユーズ素子を例に挙
げて、図面を用いて説明する。第２図（ａ）〜第２図（
ｅ）は、従来の半導体ヒユーズ素子を説明するための平
面図および断面図である。Next, the structure of a conventional fuse element will be described with reference to the drawings, taking as an example a semiconductor fuse element in which a polycrystalline silicon layer is used as the material for the blowing part. Figure 2 (a) - Figure 2 (
e) is a plan view and a cross-sectional view for explaining a conventional semiconductor fuse element.
以下同一の部分に対しては同一の番号を使用して説明を
行なう。Hereinafter, the same parts will be described using the same numbers.
先ず、半導体シリコ／基板１上に第一の絶縁膜２となる
二酸化シリコン膜が形成される。この第一の絶縁膜２は
、通常、トランジスタ、抵抗等の複数の回路素子間を電
気的に分離するために形成する分離絶縁膜で１、二酸化
ンリコ／膜の場合には、９００〜１１００℃のＨ２−０
２雰囲気中における熱酸化により ６０００〜１０００
０人の膜厚に形成される。First, a silicon dioxide film, which will become the first insulating film 2, is formed on the semiconductor silicon/substrate 1. This first insulating film 2 is usually an isolation insulating film formed to electrically isolate multiple circuit elements such as transistors and resistors. H2-0
6000-1000 by thermal oxidation in 2 atmosphere
Formed to a film thickness of 0.
次いで、前記第一の絶縁膜２上に、公知の減圧気相成長
法によりＳｉＨ４等の熱分解を行って、多結晶シリコン
層が２０００〜６０００人の膜厚に形成される。該多結
晶シリコン層は、その成し時に上記８ｉＨ４等を含む反
応ガス中にリン、ホウ素或はヒ素等の不純物を含むガス
を混入することにより。Next, a polycrystalline silicon layer is formed on the first insulating film 2 to a thickness of 2,000 to 6,000 wafers by thermally decomposing SiH4 or the like using a known low-pressure vapor deposition method. The polycrystalline silicon layer is formed by mixing a gas containing impurities such as phosphorus, boron, or arsenic into the reaction gas containing 8iH4 and the like.
又は、成長後に前記不純物を拡散或はイオン注入するこ
とにより、不純物添加され、１０？−２０００／［１の
層抵抗を呈するようにされる。次いで、前記多結晶シリ
コン層は公知のフォトリングラフィ法によりパターニン
グされ、溶断部３ａとその両端に位置する接続部３ｂと
を有する多結晶シリコンヒユーズ３が形成される。次い
で多結晶シリコンヒユーズ３上に層間絶縁膜４が５ｏｏ
ｏ〜１２０００人の膜厚に形成される。この層間絶縁膜
４は通常、常圧気相成長法により形成された二酸化シリ
コン膜であり、パックベーショ／のために微量のリンが
添加されている。公知の如く、常圧気相成長法により形
成された二酸化シリコン膜はピンホール等の欠陥を有し
ており、このままでは良好な絶縁性を得ることが困難で
あるため１通常、成長後に９００〜１１００℃のＮ２−
０．雰囲気中にて、熱処理を行ない、膜質を改善する。Alternatively, the impurity is added by diffusing or ion-implanting the impurity after growth, and 10? It is made to exhibit a layer resistance of -2000/[1. Next, the polycrystalline silicon layer is patterned by a known photolithography method to form a polycrystalline silicon fuse 3 having a fusing part 3a and connection parts 3b located at both ends thereof. Next, an interlayer insulating film 4 is formed on the polycrystalline silicon fuse 3 by 5mm.
It is formed to a thickness of 12,000 to 12,000 people. This interlayer insulating film 4 is usually a silicon dioxide film formed by normal pressure vapor phase growth, and a trace amount of phosphorus is added for pack-vation. As is well known, silicon dioxide films formed by normal pressure vapor phase growth have defects such as pinholes, and it is difficult to obtain good insulation properties. ℃N2-
0. Heat treatment is performed in an atmosphere to improve film quality.
この時、多結晶シリコンヒユーズ３上には、層間絶縁膜
４中を通過した酸素により酸化され、二酸化シリコン膜
５が形成される。次いで、フォトリングラフィ法を用い
て。At this time, polycrystalline silicon fuse 3 is oxidized by oxygen passing through interlayer insulating film 4, and silicon dioxide film 5 is formed. Then, using the photophosphorography method.
前記層間絶縁膜４に多結晶シリコンヒエーズ３の接続部
３ｂに至る接続孔６及び溶断部３ａに至る開孔７が形成
される。この接続孔６及び開孔７の形成には７ツ化水素
酸を用いたウェットエツチング又は四７）化炭素等のガ
スをプラズマ状態で利用するドライエツチングが用いら
れる。次いで、アルミニウム等より成る配線金属層８が
、同じくフォトリングラフィ法を用いて形成され、更に
、配線金属層８上には保護絶縁膜９が形成される。A connection hole 6 reaching the connection portion 3b of the polycrystalline silicon oxide 3 and an opening 7 reaching the fusing portion 3a are formed in the interlayer insulating film 4. In order to form the connection hole 6 and the opening 7, wet etching using hydrochloric acid or dry etching using a gas such as carbon tetrachloride in a plasma state is used. Next, a wiring metal layer 8 made of aluminum or the like is formed using the same photolithography method, and a protective insulating film 9 is further formed on the wiring metal layer 8.
この保護絶縁膜９は前記層間絶縁膜４と同様の方法で形
成されたリンの添加された二酸化シリコン膜、或は、こ
の二酸化シリコン膜上にプラズマ気相成長された窒化ン
リコン膜を積層した複合膜が利用される。This protective insulating film 9 is a silicon dioxide film doped with phosphorus formed in the same manner as the interlayer insulating film 4, or a composite film in which a silicon nitride film deposited by plasma vapor phase growth is laminated on this silicon dioxide film. A membrane is utilized.
前記開孔７は、１述の如き各種の熱処理により多結晶シ
リコンヒーーズ３の表面が酸化されてできる二酸化ンリ
コ／膜５を除去するだめのもので、半導体ヒーーズ素子
の溶断時のエネルギーを半減させる事に効果があり、従
って、溶断部３ａ近傍での前記エネルギーによる歪の発
生、クラックの発生の低減を行なうものである。The openings 7 are for removing the silicon dioxide/film 5 that is formed when the surface of the polycrystalline silicon heaters 3 is oxidized by the various heat treatments mentioned above, and reduces the energy when the semiconductor heater element is blown out by half. This is effective in reducing the occurrence of strain and cracking caused by the energy in the vicinity of the fused portion 3a.
前記開孔７の形成は゛前述の如く、前記接続孔６の形成
と同時に行なうこともできるが、配線金属１１１ｉ８の
形成時におけるエツチング処理が四フフ化炭素等のガス
をプラズマ状態で利用するドライエツチングで行なう場
合には、ウェットエツチングに比較して、配線金属層７
と多結晶シリコンヒユーズ３との選択比を大きくする事
が困難であり。The formation of the opening 7 can be performed simultaneously with the formation of the connection hole 6 as described above, but the etching process when forming the wiring metal 111i8 may be dry etching using a gas such as carbon tetrafluoride in a plasma state. Compared to wet etching, the wiring metal layer 7
It is difficult to increase the selection ratio between the polycrystalline silicon fuse 3 and the polycrystalline silicon fuse 3.
多結晶シリコンヒユーズ３の膜減りの危険があるため、
個別の工程で、フッ化水素酸を利用するウェットエツチ
ングにより形成するのが一般的でろる。Due to the risk of thinning of the polycrystalline silicon fuse 3,
It is generally formed by wet etching using hydrofluoric acid in a separate step.
前記構成の半導体ヒーーズ素子においては、多 ゛
結晶シリコンヒーーズ３０表面及び側面が酸化されてで
きる二酸化シリコン膜５を完全に除去するため、第２図
（ｂ）に示す如く前記開孔７は、前記接続孔６と異なり
、その幅が多結晶ンリコｙヒエーズ３の溶断部３ａの幅
よりも広くなるよう形成される。従って、第一の絶縁膜
２が二酸化ン・リコン膜の場合には、前記開孔７の形成
時、即ち、前記層間絶縁膜４及び前記多結晶シリコンが
酸化されてできる二酸化シリコン膜のエツチング時に、
第２図（Ｃ）に示す如く、多結晶シリコンヒユーズ３の
下の第一の絶縁膜にアンダーカットを生じることとなる
。このアンダーカットが過度の場合には開孔７の位置に
おいて、多結晶シリコンヒエーズは宙釣り状態となり、
機械的衝撃により破損する場合があり、又、過度となら
ない程度のアンダーカットの場合でも、その後の保護絶
縁膜９のカバレッジが不良となり、共に信頼性を低下さ
せることとなる。In the semiconductor heating element having the above structure, in order to completely remove the silicon dioxide film 5 formed by oxidizing the surface and side surfaces of the polycrystalline silicon heating element 30, the opening 7 is formed in the connection area as shown in FIG. 2(b). Unlike the hole 6, the hole 6 is formed so that its width is wider than the width of the fusing portion 3a of the polycrystalline honey 3. Therefore, when the first insulating film 2 is a silicon dioxide film, at the time of forming the opening 7, that is, when etching the silicon dioxide film formed by oxidizing the interlayer insulating film 4 and the polycrystalline silicon. ,
As shown in FIG. 2(C), an undercut occurs in the first insulating film under the polycrystalline silicon fuse 3. If this undercut is excessive, the polycrystalline silicon layer will be suspended in the air at the position of the opening 7.
Damage may occur due to mechanical impact, and even if the undercut is not excessive, the subsequent coverage of the protective insulating film 9 will be poor, both of which will reduce reliability.
（発明の目的）
本発明の目的は、上記の従来技術の欠点を除去し、信頼
性の改善された半導体ヒユーズ素子の製造方法を提供す
ることにある。(Object of the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor fuse element with improved reliability by eliminating the above-mentioned drawbacks of the prior art.
（発明の構成）
本発明の半導体ヒユーズ素子の製造方法は、中結晶シリ
コン基板とに第一の絶縁膜を形成する工程と、該第一の
絶縁膜上に第二の絶縁膜を形成する工程と、該第二の絶
縁膜上にリン、ホウ素或はヒ素等を含む多結晶シリコン
より成り、溶断部とその両端に位置する接続部とより成
る多結晶シリコンヒユーズを形成する工程と、該多結晶
シリコンヒーーズ上に層間絶縁膜を形成する工程と、該
層間絶縁膜に前記接続部に達する接続孔を形成する工程
と、前記層間絶縁膜に前記溶断部に達する開孔を形成す
る工程と、前記層間絶縁股上に前記接続孔を介して前記
多結晶シリコンヒユーズに接続される配線金属層を形成
する工程と、該配線金属層上に保護絶縁膜を形成する工
程とを有し、前記第二の絶縁膜が前記第一の絶縁膜のエ
ツチング材に対して実質的にエツチングされない材料で
構成されるものである。(Structure of the Invention) The method for manufacturing a semiconductor fuse element of the present invention includes a step of forming a first insulating film on a medium-crystalline silicon substrate, and a step of forming a second insulating film on the first insulating film. a process of forming a polycrystalline silicon fuse made of polycrystalline silicon containing phosphorus, boron, arsenic, etc. on the second insulating film, and comprising a fusing part and connection parts located at both ends thereof; a step of forming an interlayer insulating film on the crystalline silicon heater; a step of forming a connection hole in the interlayer insulating film reaching the connection portion; a step of forming an opening in the interlayer insulating film reaching the fusing portion; forming a wiring metal layer connected to the polycrystalline silicon fuse through the connection hole on the interlayer insulation crotch; and forming a protective insulating film on the wiring metal layer; The insulating film is made of a material that is not substantially etched by the etching material for the first insulating film.
（実施例）
μ下、本発明の実施例につき図面を参照して詳細に説明
する。(Example) Below, examples of the present invention will be described in detail with reference to the drawings.
１図（ａ）、（ｂ）は、それぞれ本発明の一実施例の半
導体ヒスーズ素子の製造方法を説明するための平面図及
び断面図士ある。第１図（ａ）、（ｂ）に示すように、
従来例として説明した方法と同一の手段で、単結晶シリ
コン基板１上に二酸化シリコン膜等より成る第一の絶縁
膜２を形成する。次いで第一の絶縁膜の所定領域上に第
２の絶縁膜１ｏを形成する。第２の絶縁膜としては、例
えば、減圧気相成長法により、８ｒＨ４ガスとＮ２ガス
との反応に利用した窒化７リコ／膜等が利用できる。こ
の第２の絶縁膜として窒化シリコン膜を利用する場合に
は約２００〜８００λの膜厚に形成される。次いで従来
例に示したと同じ様に、多結晶シリコン膜の成長、不純
物添加、及びフォトリングラフィ法によるバターニング
が行なわれて、多結晶シリコンヒユーズ３が形成される
。更に多結晶シリコンヒユーズ３上にリンの添加された
二酸化シリコン膜等の層間絶縁膜４が形成され、従来例
に示した同様の熱処理工程を経ることにより、同様に多
結晶シリコンヒユーズの表面に、該多結晶シリコンが酸
化されてできる二酸化シリコン膜５が形成される。次い
で、７オトリングラフイ法を用いて層間絶縁Ｍ４に多結
晶シリコンヒーーズ３の接続部３ｂに至る接続孔６が形
成され、更にアルミニウム等の金属層の被着後、同じく
フォトリングラフィ法により配線金属１ｉｉ８がバター
ニングされ、多結晶シリコンヒ二−ズ３は、接続孔５を
介して、配線金属層８により外部回路へ接続される。FIGS. 1A and 1B are a plan view and a cross-sectional diagram, respectively, for explaining a method of manufacturing a semiconductor fuse element according to an embodiment of the present invention. As shown in FIGS. 1(a) and (b),
A first insulating film 2 made of a silicon dioxide film or the like is formed on a single-crystal silicon substrate 1 using the same method as described as the conventional example. Next, a second insulating film 1o is formed on a predetermined region of the first insulating film. As the second insulating film, for example, a nitride 7lico/film used in the reaction of 8rH4 gas and N2 gas by low pressure vapor phase growth method can be used. When a silicon nitride film is used as the second insulating film, it is formed to have a thickness of about 200 to 800λ. Next, in the same manner as shown in the conventional example, a polycrystalline silicon film is grown, impurities are added, and patterning is performed by photolithography to form a polycrystalline silicon fuse 3. Furthermore, an interlayer insulating film 4 such as a silicon dioxide film doped with phosphorus is formed on the polycrystalline silicon fuse 3, and by going through the same heat treatment process as shown in the conventional example, the surface of the polycrystalline silicon fuse is A silicon dioxide film 5 is formed by oxidizing the polycrystalline silicon. Next, a connection hole 6 leading to the connection part 3b of the polycrystalline silicon heater 3 is formed in the interlayer insulation M4 using the 7-otrinography method, and after a metal layer such as aluminum is deposited, a wiring metal 1ii8 is formed using the same photolithography method. The patterned polycrystalline silicon heather 3 is connected to an external circuit via a wiring metal layer 8 through a connection hole 5.
続いて、フォトリングラフィを利用し、前記層間絶縁膜
４に多結晶シリコンヒエーズ３の溶断部３ａに至る開孔
７が形成される。この開孔７の形成は、前記層間絶縁膜
４が二酸化シリコン膜の場合には前述の如く、フッ化水
素酸が利用され、層間絶縁膜４と同時に、前記多結晶シ
リコンヒエーズ３の表面が酸化されてできる二酸化シリ
コン膜５もエツチングされる。この開孔７の形成時には
。Subsequently, using photolithography, an opening 7 is formed in the interlayer insulating film 4 to reach the fused portion 3a of the polycrystalline silicon oxide 3. When the interlayer insulating film 4 is a silicon dioxide film, hydrofluoric acid is used to form the opening 7, as described above, and the surface of the polycrystalline silicon oxide 3 is formed at the same time as the interlayer insulating film 4. The oxidized silicon dioxide film 5 is also etched. When forming this opening 7.
第一の絶縁膜２となる単結晶シリコン基板１を酸化して
得た二酸化シリコン膜は第二の絶縁膜１０により保護さ
れているため、エツチングされることなく、従って、多
結晶シリコンヒユーズ３の溶断部３ａの下にアンダーカ
ットを生じることがない。前記第二の絶縁膜１０は、前
記開孔７形成時のエツチング阻止層となるためのもので
あるから。The silicon dioxide film obtained by oxidizing the single crystal silicon substrate 1, which becomes the first insulating film 2, is protected by the second insulating film 10, so it is not etched, and therefore the polycrystalline silicon fuse 3 is not etched. Undercuts do not occur under the fusing portion 3a. This is because the second insulating film 10 serves as an etching prevention layer when the opening 7 is formed.
半導体ヒ工−ズ素子全体の下にある必要はなく、前記開
ロアより適度に広く形成すればよｉ０引き続き、配線金
属層８上に保護絶縁膜９が形成されるが、本発明の実施
例では、多結晶ンリコンヒューズ３の溶断部３ａにおけ
るアンダーカットがないため核部における保護絶縁膜９
のカバレッジも良く、高い信頼性を得ることができる。It does not need to be under the entire semiconductor fuse element, but may be formed to be appropriately wider than the open lower layer.Subsequently, the protective insulating film 9 is formed on the wiring metal layer 8, but according to the embodiments of the present invention In this case, since there is no undercut in the blown part 3a of the polycrystalline silicon fuse 3, the protective insulating film 9 in the core part is
The coverage is good and high reliability can be obtained.
尚、本発明の実施例中における各種製造工程のほとんど
は、半導体ヒユーズ素子μ外の他の回路素子の製造と同
時に行なわれることは言うまでもない。It goes without saying that most of the various manufacturing steps in the embodiments of the present invention are performed simultaneously with the manufacturing of other circuit elements other than the semiconductor fuse element μ.
又１本発明の第二の絶縁膜として使用した窒化シリコン
膜は１例えば、ダイナミック動作型のＭＯ８記憶装置で
は一層目の多結晶ンリコ／電極と、二層目の多結晶シリ
コン電極との間の絶縁に使用される場合もあり、特殊な
工程追加を行わずに本発明の半導体ヒユーズ素子を製造
することも可能である。In addition, the silicon nitride film used as the second insulating film of the present invention is, for example, in a dynamic operation type MO8 memory device, between the first layer of polycrystalline silicon/electrode and the second layer of polycrystalline silicon electrode. It is sometimes used for insulation, and it is also possible to manufacture the semiconductor fuse element of the present invention without adding any special process.
（発明の効果）
以上、詳細に説明したように、本発明の半導体ヒエーズ
素子の製造方法によれば第二の絶縁膜？設けることによ
り、半導体ヒユーズ素子の下の絶縁膜のアンダーカット
が起らず信頼性を容易に高めることが可能となる。(Effects of the Invention) As described above in detail, according to the method for manufacturing a semiconductor HiAze device of the present invention, the second insulating film ? By providing this, undercutting of the insulating film under the semiconductor fuse element does not occur, making it possible to easily improve reliability.
第１図（ａ）、（ｂ） は本発明の一実施例の平面図
及びＡ−に断面図、第２図（ａ）−（Ｃ）は従来の半導
体ヒユーズ素子の平面図並びにＢ −８’及びＣ−Ｃ’
の断面図である。
１り・・・・単結晶シリコン基板、２・・・・・・第一
の絶縁膜、３・・・・・・多結晶シリコンヒユーズ、３
ａ・・・・・・溶断部、３ｂ・・・・・・接続部、４・
・・・・・層間絶縁膜、５・・・・・・二酸化シリコン
膜、６・・・・・・接続孔、７・・・・・・開孔、７８
・・・・・・配線金属層、９・・・・・・保護絶縁膜、
ｌＯ・・・・・・第二の絶縁膜。FIGS. 1(a) and (b) are a plan view of an embodiment of the present invention and a sectional view at A-8, and FIGS. 2(a)-(C) are a plan view of a conventional semiconductor fuse element and B-8. 'and C-C'
FIG. 1... Single crystal silicon substrate, 2... First insulating film, 3... Polycrystalline silicon fuse, 3
a... Fusing part, 3b... Connection part, 4.
...Interlayer insulating film, 5...Silicon dioxide film, 6...Connection hole, 7...Opening hole, 78
...Wiring metal layer, 9...Protective insulating film,
lO...Second insulating film.
Claims (2)
工程と、該第一の絶縁膜上の所定領域に第二の絶縁膜を
形成する工程と、該第二の絶縁膜上にリン、ホウ素或は
ヒ素等を含む多結晶シリコンより成り、溶断部とその両
端に位置する接続部とより成る多結晶シリコンヒューズ
を形成する工程と、該多結晶シリコンヒューズ上に層間
絶縁膜を形成する工程と、該層間絶縁膜に前記接続部に
達する接続孔を形成する工程と、前記層間絶縁膜に前記
溶断部に達する開孔を形成する工程と、前記層間絶縁膜
上に前記接続孔を介して前記多結晶シリコンヒューズに
接続される配線金属層を形成する工程と、該配線金属層
上に保護絶縁膜を形成する工程とを有し、前記第二の絶
縁膜が前記第一の絶縁膜のエッチング材に対して実質的
にエッチングされない材料で構成されることを特徴とす
る半導体ヒューズ素子の製造方法。(1) A step of forming a first insulating film on a single crystal silicon substrate, a step of forming a second insulating film in a predetermined area on the first insulating film, and a step of forming a second insulating film on the second insulating film. A step of forming a polycrystalline silicon fuse made of polycrystalline silicon containing phosphorus, boron, arsenic, etc. and consisting of a fusing part and connection parts located at both ends thereof, and forming an interlayer insulating film on the polycrystalline silicon fuse. forming a contact hole in the interlayer insulating film that reaches the connection portion; forming an opening in the interlayer insulating film that reaches the fusing portion; and forming the contact hole on the interlayer insulating film. forming a wiring metal layer connected to the polycrystalline silicon fuse through the wiring metal layer; and forming a protective insulating film on the wiring metal layer, wherein the second insulating film is connected to the first insulating film. A method for manufacturing a semiconductor fuse element, characterized in that it is made of a material that is not substantially etched by an etching material for a film.
絶縁膜が窒化シリコン膜であることを特徴とする特許請
求の範囲第（１）項記載の半導体ヒューズ素子の製造方
法。(2) The method for manufacturing a semiconductor fuse element according to claim (1), wherein the first insulating film is a silicon dioxide film and the second insulating film is a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15060484A JPS6130060A (en) | 1984-07-20 | 1984-07-20 | Manufacture of semiconductor fuse element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15060484A JPS6130060A (en) | 1984-07-20 | 1984-07-20 | Manufacture of semiconductor fuse element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6130060A true JPS6130060A (en) | 1986-02-12 |
Family
ID=15500513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15060484A Pending JPS6130060A (en) | 1984-07-20 | 1984-07-20 | Manufacture of semiconductor fuse element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6130060A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2723663A1 (en) * | 1994-08-10 | 1996-02-16 | Motorola Semiconducteurs | SEMICONDUCTOR FUSE DEVICES |
| WO2002058147A3 (en) * | 2000-12-28 | 2003-03-27 | Infineon Technologies Corp | Method and structure to reduce the damage associated with programming electrical fuses |
| JP2013058524A (en) * | 2011-09-07 | 2013-03-28 | Fujitsu Semiconductor Ltd | Semiconductor device and manufacturing method thereof |
-
1984
- 1984-07-20 JP JP15060484A patent/JPS6130060A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2723663A1 (en) * | 1994-08-10 | 1996-02-16 | Motorola Semiconducteurs | SEMICONDUCTOR FUSE DEVICES |
| EP0697708A1 (en) * | 1994-08-10 | 1996-02-21 | Motorola Semiconducteurs S.A. | Semiconductor fuse devices |
| WO2002058147A3 (en) * | 2000-12-28 | 2003-03-27 | Infineon Technologies Corp | Method and structure to reduce the damage associated with programming electrical fuses |
| JP2013058524A (en) * | 2011-09-07 | 2013-03-28 | Fujitsu Semiconductor Ltd | Semiconductor device and manufacturing method thereof |
| US9024410B2 (en) | 2011-09-07 | 2015-05-05 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing semiconductor device |
| US9349685B2 (en) | 2011-09-07 | 2016-05-24 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing semiconductor device |
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