JPH09232116A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which enables adjustment of resistance value without causing any increase in temperature of a resistor and without generating excessive current concentration and microcrack in the resistor due to trimming, and manufacture thereof. SOLUTION: After an impurity diffusion layer 2 is formed on the surface of a single crystal silicon substrate 1, a silicon oxide film 3 is deposited on the impurity diffusion layer 2 and the single crystal silicon substrate 1. A contact hole is formed in the silicon oxide film 3 on the impurity diffusion layer 2 by photolithography and etching techniques, and a wiring layer 5 is formed in the contact hole 4. Then, the wiring layer 5 is irradiated with laser beams for trimming while the resistance value of a resistance element is measured. The contact resistance value is increased by reducing the contact area between the impurity diffusion layer 2 and the wiring layer 5, so that the resistance value is adjusted to a desired value. Finally, a protective film 6 is formed thereon except for at least part of the wiring layer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a resistance element and a method of manufacturing the same, and more particularly to a method of adjusting the resistance value of the resistance element.

[0002]

2. Description of the Related Art FIG. 2 is a schematic view showing a resistance element according to a conventional example, (a) is a schematic plan view showing a state viewed from the upper surface, and (b) is a schematic sectional view taken along the line AB. It is a figure. The resistance element is composed of a resistor 7 on the silicon oxide film 3 as an interlayer insulating film.
And the wiring layer 5 is formed on both ends of the resistor 7. Then, in order to adjust the resistance value of the resistance element, the resistance is corrected by forming (trimming) the cut portion 8 on the resistor 7 using a laser.

[0003]

However, when trimming is performed using a laser as described above, heat is generated in the resistor 7 itself due to the irradiation of the laser, and the temperature rises to adjust the resistance value. There has been a problem that the resistance value of the element changes, excessive current concentration occurs in a portion where the resistor is trimmed, and microcracks occur.

The present invention has been made in view of the above points, and an object of the present invention is to prevent excessive temperature concentration and micro cracks in the resistor due to trimming without temperature rise of the resistor. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same that can adjust the resistance value without causing the occurrence.

[0005]

According to the first aspect of the present invention,
A semiconductor substrate having an impurity diffusion layer as a resistor on its surface, an insulating film formed on the surface of the semiconductor substrate, a contact hole formed in the insulating film on the impurity diffusion layer, and the inside of the contact hole. In a semiconductor device having a wiring layer formed on the wiring layer, the resistance value is adjusted by reducing the contact area between the impurity diffusion layer and the wiring layer by trimming the wiring layer. It is characterized by.

According to a second aspect of the present invention, after forming an impurity diffusion layer as a resistor on the semiconductor substrate, an insulating film is formed on the surface of the semiconductor substrate on which the impurity diffusion layer is formed, In the method of manufacturing a semiconductor device, wherein a contact hole for making a connection with the impurity diffusion layer is formed in the insulating film on the diffusion layer, and a wiring layer is formed in the contact hole, the wiring layer is trimmed. Thus, the resistance value is adjusted by reducing the contact area between the impurity diffusion layer and the wiring layer.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a manufacturing process diagram showing a resistance element according to an embodiment of the present invention. First, the impurity diffusion layer 2 as a resistor is formed on the surface of the single crystal silicon substrate 1.
On the impurity diffusion layer 2 and the single crystal silicon substrate 1
A silicon oxide film 3 as an interlayer insulating film is deposited on the surface where the impurity diffusion layer 2 is formed by a plasma CVD method or the like, and a photolithography technique and an etching technique are applied to the silicon oxide film 3 on the impurity diffusion layer 2. Using contact hole 4
To form As an example of the method of forming the impurity diffusion layer 2, boron (B) can be formed by ion implantation into the single crystal silicon substrate 1 and thermal diffusion. Also,
In the present embodiment, the contact hole 4 is formed in a square shape having a side length of α (= 10 μm). Further, in this embodiment, the impurity diffusion layer 2 is formed in advance so as to have a value smaller than a desired resistance value.

Then, a resistance element is manufactured by forming a wiring layer 5 for inter-element wiring in the contact hole 4 (FIG. 1A). As an example of a method of forming the wiring layer 5, an aluminum layer is formed by sputtering aluminum (Al) as a target, and is patterned into a predetermined shape using a photolithography technique and an etching technique. it can.

Then, while measuring the resistance value of the resistance element, the wiring layer 5 is irradiated with a laser for trimming to reduce the contact area between the impurity diffusion layer 2 and the wiring layer 5 (in the present embodiment, the contact area). Length of α (= 10 μm) × β (=
5 μm)) to increase the contact resistance value (in this embodiment, the contact resistance value is twice the resistance value before trimming), and the contact resistance value is adjusted to a desired resistance value (FIG. 1B).

Finally, the wiring layer 5 is made of silicon resin or the like.
The protective film 6 is formed by removing at least a part of
(C)).

Therefore, in this embodiment, the wiring layer 5
Since the protective film 6 is formed of silicon resin or the like that does not need to be subjected to high-temperature heat treatment, the impurity diffusion layer 2 as a resistor does not rise in temperature and the temperature rises. It is possible to prevent the accompanying change in resistance value. Further, since the wiring layer 5 is laser-trimmed, excessive current concentration and microcracks do not occur in the impurity diffusion layer 2.

[0012]

The invention according to claim 1 or 2 is
A semiconductor substrate having an impurity diffusion layer as a resistor on its surface, an insulating film formed on the surface of the semiconductor substrate, a contact hole formed in the insulating film on the impurity diffusion layer, and a contact hole formed in the contact hole. Since the contact area between the impurity diffusion layer and the wiring layer is reduced by trimming the wiring layer in the semiconductor device including the wiring layer, it is possible to increase the resistance value. The resistance value can be adjusted and the wiring layer is trimmed so that the temperature of the resistor does not rise and the resistance value does not cause excessive current concentration or microcracks in the resistor due to trimming. It was possible to provide a semiconductor device and a manufacturing method thereof capable of adjusting the above.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram showing a resistance element according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a resistance element according to a conventional example,
(A) is a schematic plan view showing a state viewed from the top,
(B) is a schematic sectional view taken along a line AB.

[Explanation of symbols]

 1 Single Crystal Silicon Substrate 2 Impurity Diffusion Layer 3 Silicon Oxide Film 4 Contact Hole 5 Wiring Layer 6 Protective Film 7 Resistor 8 Notch

Claims (2)

[Claims] 1. A semiconductor substrate having an impurity diffusion layer as a resistor on its surface, an insulating film formed on the surface of the semiconductor substrate, and a contact hole formed in the insulating film on the impurity diffusion layer. In a semiconductor device having a wiring layer formed in the contact hole, the resistance value is adjusted by reducing the contact area between the impurity diffusion layer and the wiring layer by trimming the wiring layer. A semiconductor device characterized in that. 2. After forming an impurity diffusion layer as a resistor on a semiconductor substrate, an insulating film is formed on the surface of the semiconductor substrate on which the impurity diffusion layer is formed, and the insulation on the impurity diffusion layer is formed. In a method of manufacturing a semiconductor device, wherein a contact hole for making a connection with the impurity diffusion layer is formed in a film, and a wiring layer is formed in the contact hole, the impurity diffusion layer is formed by trimming the wiring layer. And a resistance value is adjusted by reducing a contact area between the wiring layer and the wiring layer.