JPH0344062A - Integrated circuit having improved soluble link - Google Patents

Abstract

PURPOSE: To melt a fuse at a low energy level by selectively etching a dielectric layer covering the fuse composed of a soluble link to expose the fuse and covering the fuse with a thin protective dielectric material. CONSTITUTION: On a semiconductor substrate 10a dielectric layer 11 and dielectrics 12, 13 are formed. By a known pattern-forming technique a soluble link 14 is formed on the layer 13. A dielectric layer 15 formed on the link 14 is pref. an SiO2 deposited at a lower temp. The inter-level dielectric 15 is removed from the patterned link 14. A protective dielectric material layer 30 is formed on the exposed uppermost surface of an integrated circuit precursor. Since such protective dielectric 30 thinner than the inter-level dielectric 15 is used, the link 14 is thoroughly and cleanly molten by applying a laser energy.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to techniques for fabricating integrated circuits with improved fusible conductive links.

Prior art integrated circuits often contain fusible conductive links ("fuses") that can be made non-conductive (or "cut") by applying laser energy. For example, in dynamic or static memory chips, defective A memory cell may be replaced by cutting its associated fuse and leaving a spare column or row of cells in use by also cutting the fuse. Logic circuits may be repaired by cutting the fuse. For example, it is known to first create a comprehensive logic chip with a large number of interconnected logic gates.Then, in the final process step, the logic circuit is Chips are customized to perform desired logic functions by cutting unnecessary logic elements by melting fuses to interconnect them to the desired circuit. Applications of laser melting of fuses are also possible. be.

Reliability in melting fuses is important, especially when a large number of fuses must be reliably fused in order for the integrated circuit to function properly. The limiting factor in reliably melting the fuse is the minimum laser energy required to melt the fuse. That is, if the laser energy is not high enough,
Some of the fuses that are to be fused do not actually become non-conductive. Changes in fuse thickness, width, and laser energy per irradiation can affect the reliability of fuse melting. On the other hand, the debris created by ensuring links are melted creates reliability problems of its own. That is, if conductive link material (typically polysilicon, metal silicide, or metal) is redeposited on the chip after the fuse has been fused, it falls into the second area of reliability (41). For example, melted link material can redeposit to short two conductors on the same or different levels of the chip.

One technique for improving the reliability of melting fuses with radiant (e.g., laser) energy is disclosed in U.S. patent application Ser.
4531. As described therein, the dielectric material covering the fuse is partially etched away to reduce the thickness of the fuse formed in the underlying conductor level. This allows the fuse to melt more easily (ie, at a lower energy level) than if the entire thickness were left intact.

SUMMARY OF THE INVENTION A technique has been invented that improves the reliability of melting metal fuses in solid state devices. In one embodiment, a dielectric Jt'l covers the fuse.

Selectively etch away to expose the fuse. A controlled thickness of protective dielectric material is then formed to cover the links prior to melting the fuse. The thickness of the protective dielectric is less than the thickness of the dielectric etched from the fuse. In another embodiment, the fuse is fused before forming the protective dielectric layer and then depositing the final cap dielectric layer.

The following detailed description relates to improved techniques for forming integrated circuit fuses. Referring to FIG. 1, the first embodiment is a semiconductor substrate on which a dielectric layer 1 is formed]
, O. The substrate is silicon in this example and the dielectric layer is typically grown or deposited silicon dioxide. Above the dielectric layer is shown a first conductor which, if present, is typically doped polysilicon, although it may be provided as needed as far as the present invention is concerned. In addition, part or all of the conductor top 2 may contain metal silicide. Conductor 12”
Second, a dielectric layer 13 is formed, typically a flowable glass such as borophosphosilicate glass (BI). Layer 13 is made of spin-on glass or tetraethoxysilane (TE0) according to principles well known to those skilled in the art.
1) or various precursor gases including silane (S i H4). Dielectric layer 13 is typically formed subsequent to the formation of active device regions, including sources and trains, for example to gate 1, which may be fabricated in a manner well known to those skilled in the art.

Fusible links 14 are formed on [13] by depositing and patterning a metal layer by techniques well known to those skilled in the art. The metal is aluminum for current silicon technology, gold for current III-III technology, and other metals are possible including refractory metals. The fusible link may be a target area of the metal runner with the same shape (@ and height) as the remaining runners. Alternatively, the fusible link may be part of a metal runner with an improved reduced cross-sectional area to facilitate fusing by laser irradiation. One technique for partially reducing the height of the metal runners in the fusible link section is to first deposit a metal layer of a given thickness in a conventional manner. Next, windows are etched into the metal layer in the open areas that will form the fuses. Next, a thin metal layer is deposited. The two metal layers are patterned to form the desired metal runner with a thickness that includes both layers, while leaving a reduced thickness fusible link in the area of the window. This optional melt forming technique is further described in commonly assigned US patent application Ser. No. 07/374,423, filed June 30, 1989. In most cases, metal reflects laser energy better than polysilicon or metal silicide, so the problem of reliably fusing metal links is greater than fusing fuses made of these other materials.

The fusible link has a dielectric layer 5 formed thereon, which will be referred to herein as an "interlevel" dielectric. N15 is typically silicon dioxide deposited at relatively low temperatures and may be deposited from TE01 or other precursor gases. In embodiments, a second level of metal conductor is optionally deposited and patterned to
It is formed on the interlevel dielectric layer 5. This may be done similarly to the first level metal. In an example process used for CMO8 integrated circuits formed with a minimum linewidth of 1.25 microns, the first level metal runners are 500 nanometers (5000 angstroms) thick and 1.7 microns thick.
It is aluminum with a width of 5 microns. The interlevel dielectric is a soluble link of two'600 nanometers (600 nanometers)
Phosphorus-doped TE with a thickness of 0 angstroms
It is O8.

Referring to FIG. 2, the interlevel dielectric has been etched away from the patterned fusible links 1-4.

In this example, the etched region extends 10 microns along the length of the fusible link (perpendicular to the page) and 8 microns laterally. This may be done by conventional phosphorography and etching techniques. For example, in this example, a ↓micron thick photoresist N (not shown) is deposited on the interlevel dielectric 15 (and second level metal conductors 16 and 17) - and the soluble link 14 A pattern is formed using normal gluing lithography technique to expose the wafer. The interlevel dielectric is then etched away from the soluble links using reactive ion etching, which is well known to those skilled in the art. To ensure removal of the interlevel dielectric from the fusible links, an overetch is performed, as shown, such that about 300 nanometers (3000 Å x 1 loam) of the glass layer 13 are also removed. Note that the photoresist acts as an etch mask to prevent removal of interlevel dielectric from areas adjacent to the fusible links. After etching, the photoresist etch mask is removed using conventional techniques.

Referring to FIG. 3, a layer of protective dielectric material 30 is formed (as shown) over the exposed top surface of the integrated circuit precursor.

The protective dielectric may be formed by deposition as in the embodiment. Thus, the exposed portion of fusible link 14, the second
level metal runners 16.17, interlevel dielectric 15
, the portion of the glass N-work 3 adjacent to the fusible link is covered by a protective dielectric 30. The thickness of the protective dielectric layer is
It is smaller than that of the interlevel dielectric, typically less than one-half the thickness of one interlevel dielectric. However, the thickness of the protective dielectric layer is typically at least 0 nanometers (100 Angstroms) to provide adequate protection. In an embodiment, the protective dielectric layer is a low temperature oxide (TE01) having a thickness of 200 nanometers (2000 Angstroms). A protective dielectric layer is maintained over the active device areas of the integrated circuit. However, in order to allow the electrical connection to be made to the bond pads,
~It is typically removed from the pad by standard phosphorography and etching techniques.

By using a protective dielectric with a reduced thickness (compared to the interlevel dielectric), the fusible links are melted more consistently and cleanly than if the entire thickness of the interlevel dielectric layer 15 remained. Ru. This is because the protective dielectric layer redeposited or grown over the fusible link has much better control over its thickness than is typically possible with interlevel dielectrics. That is, the process of forming an interlevel dielectric typically includes not only a deposition step, but also at least -times of etch bank steps followed by another time of deposition steps. The objective is to obtain a void-free interlevel dielectric with a relatively flat surface. However, the etch-back process is not as easily controlled on the surface of the wafer, and multiple depositions add variation, and the final thickness of the interlevel dielectric varies over a relatively wide range. For example, thickness variations are typically greater than plus or minus 25%, and in some two-level metal processes in 0.9 micron technology, the interlevel dielectric thickness is nominally near 000 nanometers (7000 angstroms). ), it is approximately plus or minus 50 percent. On the other hand, the redeposited protective dielectric, in the current process, has a PJ value controlled within plus or minus i,obarsen 1.

The grown dielectric also has a relatively well-controlled thickness.

Using this technique, the dielectric layer is removed more uniformly and the melted (or vaporized) link material is more consistently ejected.

Referring to FIG. 4, the fusible link region is shown after being melted by application of laser energy. For the soluble link shown above, a NiODIz YAG laser with a wavelength of 1064 nanometers and an energy, 45 nanosecond half-width (FWI(M)) pulse of approximately 1.25 microjoules melts the link. As is evident in the examples, possible debris 40-42 is prevented from contacting adjacent conductive areas by the protective dielectric. It is clear that various first and second level metal conductors can easily be shortened to the same level or another metal level. After the link melting operation,
The integrated circuit wafer is desirably cleaned in a commercially available cleaning solution (eg, PR31000) to remove unbound debris. A final "cap" layer, typically silicon nitride or silicon dioxide, is usually deposited over the surface of the integrated circuit for protection, according to principles well known to those skilled in the art.

The previous example showed a fusible link in the bottom metal level in a two-metal level structure, where the dielectric removed from the fuse is an "interlevel" dielectric. However, the fuse may also be located in the top metal level, eg 16.17, which is usually covered with a relatively thick silicon dioxide or silicon nitride "cap layer" (not shown). In that case, the cap layer may be selectively etched to expose the fuse, and a protective layer may be formed prior to the fuse melting operation. Optionally, a final camp layer may be deposited to ensure protection of the device if desired. Alternatively, a protective dielectric layer may be formed first over the metal layer and the fuse may be fused before the final cap layer is deposited. In that case, non-selective etching of the cap layer is required. Even more metal levels are possible by using a protective dielectric according to the technique of the present invention, which is applicable in the case of J-shaped fuses in any patterned metal level.

Although the above embodiments discuss silicon dioxide as the protective dielectric, other dielectrics can be used. For example, silicon nitride and silicon oxynitride may be used. It is also possible to use a grown (instead of deposited) protective dielectric. For example, the desired thickness of A
To obtain the protective dielectric surface layer of Q201, the aluminum conductor may be oxidized on its surface. This is conveniently accomplished by introducing oxygen into the plasma generating device (eg, a reactive ion etchant 6-4°) previously used to etch the pattern into the aluminum layer. However, the grown dielectric is formed only on the exposed surfaces (most 2 and sides) of the patterned conductor levels, e.g. 14° 16 and 17, and the interlevel dielectric
Note that the second is not formed. Other metals used to form the patterned metal levels containing fusible links may include oxides, nitrides, or other dielectric layers grown thereon.

In addition to the advantages mentioned above regarding reliability and ease of link melting, the use of a protective dielectric prevents contamination from reaching the active areas of the integrated circuit board. This allows the laser process to be performed under non-clean atmospheric conditions and helps prevent damage to the integrated circuit.

[Brief explanation of drawings]

Figure 2 shows the integrated circuit after etching the interlevel dielectric from the fusible links. , FIG. 3 shows the protective dielectric covering the fusible link, and FIG. 4 shows the debris resulting from melting the potential link. [Explanation of symbols of main parts]

Claims (1)

Claims: 1. at least one conductive fusible link (e.g. 14) formed on a first layer of dielectric material (e.g. 13) overlying the patterned metal level; A method of manufacturing an integrated circuit comprising a patterned metal level having a second layer of dielectric material (e.g. 15) of a given thickness, the second layer being etched from the fusible links; A method of manufacturing an integrated circuit comprising forming a protective dielectric layer (e.g. 30) having a thickness less than the given thickness above. 2. The manufacturing method according to claim 1, wherein the protective dielectric is formed by deposition. 3. The manufacturing method according to claim 1, wherein the protective dielectric is silicon dioxide. 4. The method of claim 1, wherein the protective dielectric is grown on the fusible link. 5. The manufacturing method according to claim 1, wherein the fusible link is aluminum. 6. The manufacturing method according to claim 1, wherein the fusible link is a heat-resistant metal. 7. Additional patterned metal levels (e.g. 16, 1
7), further comprising the step of forming said second layer of dielectric material.
2. The method of claim 1, wherein the layer is an interlevel dielectric. 8. The method of claim 1, wherein the patterned metal level containing the at least one conductive fusible link is a top metal level of the integrated circuit. 9. The method of claim 1, wherein the protective dielectric layer has a thickness less than half of the given thickness. 10. The method of claim 1, wherein the protective dielectric layer has a thickness of at least 10 nanometers.