JPH0316169A - Writable link structure enabling plasma metal etching - Google Patents

Abstract

PURPOSE: To form a highly reliable small-sized fuse, by forming a layer carrying a pattern composed of a masking material in a fuse area and a metallized layer on the surface of a device, and appropriately removing the undesired part of the metallized layer. CONSTITUTION: A layer 21 of a fuse material is formed on the surface of a substrate 20, and a masking layer 22 is formed and patterned in a fuse area. Then, a metallized layer 24 is formed on the entire surface of a device, and a metal mask is formed on the device. In addition, the undesired part of the layer 24 is removed so as to leave a desired metallized wiring pattern on the device. The masking layer 22 works as an enchant barrier while the metallized layer 24 is subjected to plasma etching and masks a fuse element form a plasma enchant. Therefore, a highly reliable meltable link can be formed in an integraged circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention generally relates to an integrated circuit device, which includes:
More particularly, the present invention relates to methods of forming fusible links in integrated circuit devices and resulting fusible link structures.

Conventional technology Integrated circuits using fusible links are known in the art.

Such fusible links are useful, for example, for programming in the field after the device has been manufactured and assembled by the manufacturer and delivered to the customer.

For example, programmable read-only memories (FROM) and field programmable logic arrays (FPLA) are expensive and time-consuming tools for integrated circuit manufacturers to program devices during manufacturing. Instead of having to manufacture sets of masks, a fusible link is used to allow the customer to electrically write to the device.

A number of techniques are used to manufacture fusible links. For example, polycrystalline silicon, tungsten (W)
, titanium tungsten (TiW), and nichrome have been used as fusible link materials in integrated circuits.

In modern fusible link constructions, a single layer of TiW acts as both the fuse link and the metallization barrier to avoid undesirable alloying of the aluminum metallization with silicon.
are using. In practice, a metallization layer, such as aluminum, is formed over the layer of fusible material, and using suitable masking techniques, the metallization layer is patterned to form the desired electrical wiring pattern. Form. Then, using another mask,
The exposed portions of the layer of fusible material are etched to form individual fusible links. Both tungsten and titanium tungsten can be etched using suitable wet etching techniques to pattern the layer of fusible material into individual fusible links and provide good etch selectivity. It is. That is, it etches tungsten or titanium tungsten at a good rate and does not etch too much metallization. Similarly, metallization layers such as aluminum can be wet etched using, for example, phosphoric acid to pattern the metallization layer into the desired electrical wiring pattern without etching much of the fusible material. It is.

Separate steps of wet etching of metallization and fuse material have been used to form electrical wiring patterns and individual fusible links because of the good etch selectivity with respect to metallization relative to fusible material.

As the density of integrated circuits has increased further, plasma etching has replaced wet etching. This is because plasma etching allows smaller geometries to be etched with less undercutting and lateral etching. However, for example Cfl2. Plasma environments suitable for etching aluminum, such as ccf)a or combinations thereof, do not provide good selectivity for etching tungsten and titanium-tungsten. Therefore, plasma etching is not readily adaptable to form the fusible link structure, and wet etching techniques are used when patterning the first layer of metallization and the layer of fusible material. This was a common practice. 1 The prior art uses a second plasma etch step to etch the aluminum layer for an insufficient time to etch the underlying fusible material; A subsequent wet etch step is used to pattern the fusible material. Although this prior art technique theoretically provides the desired selectivity between the etching of the aluminum metallization and the underlying meltable material, it is a two-step process and It is accompanied by difficulties.

This is because excessive plasma etching can cause undesired etching of not only the aluminum but also the underlying fuse material.

A typical conventional fuse device and its manufacturing method are described in Section 1a.
It is shown in FIGS. As shown in Figure 1a,
The semiconductor substrate 10 has active areas such as transistors. A titanium tungsten layer 11 is formed on the upper surface of substrate 10 to a thickness of about 70 OA. Then,
An aluminum metallization layer 12 is formed on the titanium-tungsten layer 11 and the desired metallization is performed using, for example, phosphoric acid which etches the aluminum layer 12 but hardly attacks the underlying titanium-tungsten layer 11. Form a pattern on the wiring pattern. As shown in FIG. 1a, each end of the fuse 14 (FIG. 1c) to be formed later has a metallization layer 1.
2 separate parts with a gap 15 formed between them.

Referring to FIG. 1b, a masking layer 13, such as photoresist, is formed to define the portions of the titanium-tungsten layer 11 that remain in the areas not covered by the remaining portions of the aluminum metallization layer 12 and thus act as individual fuses. do.

Referring to FIG. 1C, the titanium tungsten layer 1 is then
The exposed portions of aluminum metallization layer 12 are removed, for example, by a wet etch, such as H202, which does not substantially attack the remaining portions of aluminum metallization layer 12. The masking material 13 is then removed and a bowtie-shaped fuse 14 is formed, each end of which is in electrical contact with a portion of the patterned metallization wiring layer 12.

Importantly, the conventional structure of FIGS. 1a-1c, including metallization wiring layer 12 and fuse 14, must be fabricated using wet etching. This is because a plasma atmosphere that may be used to etch aluminum layer 12 into the desired pattern may also undesirably etch titanium-tungsten layer 11, and vice versa. Of course, the aluminum layer 12 is coated with a photoresist layer 13 for protection during the etching of the fusible material layer 11.
It is possible to coat parts of the material that are to remain intact. However, this requires very tight alignment or makes the ultimate dimensions of the final formed fuse larger to accommodate misalignment between masking layer 13 and aluminum metallization layer 12. must be set to something.

However, once the overlying aluminum is removed, the desired portions of the aluminum metallization layer 12 can be reliably removed from plasma etching with little damage to the portions of the underlying titanium tungsten layer l1. It is impossible to hold and protect it.

Another problem associated with the prior art shown in FIGS. 1a-1c is that the titanium-tungsten layer 11 not only acts as a fuse material, but also serves as a bond between the aluminum metallization layer 12 and the diffusion region in the substrate. It also acts as a barrier material to prevent alloying that would cause electrical shorts between the two.

This means that the thickness of titanium-tungsten layer 11 must be sufficient to prevent alloying and the current required to open or blow fuse 14 during programming. and that it is not possible to reduce the thickness to less than this desired thickness in order to reduce the voltage.

Yet another drawback of this prior art is the reflections from the sidewalls of the aluminum layer 12 during the patterning of the photoresist layer 13, which necessitates the use of a bowtie shape as a fuse rather than a rectangular shape fuse. shall be. As is conventionally known, such reflections from the sidewalls of the aluminum layer 2 cause the fuse 14 to overexpose a portion of the photoresist layer due to such reflections, as shown in FIG. 1d. This causes an undesired notch 17.

Such notches occur in close proximity to the metallization layer 12 that serves as the electrical connection to the fuse 14. During a write period, it is desirable that the fuse be blown near the center of the fuse rather than at the ends of the fuse. However, the problem with the notch shown in FIG.
The fuse is blown in the vicinity of 2, causing reliability problems.

OBJECTS The present invention has been made in view of the above points, and provides a method for forming an improved fusible link in an integrated circuit device and a method for forming an improved fusible link in an integrated circuit device, which overcomes the drawbacks of the prior art as described above. The purpose of the present invention is to provide an integrated circuit purchasing body having the following features.

CONSTRUCTION In accordance with the present invention, a novel fuse structure and method of manufacturing the same is provided, which allows the use of plasma etching of metallization material without undesirably etching the fuse material. In one embodiment of the invention, a layer of fuse material, such as tungsten, is formed on a substrate surface that is patterned into a fuse element.

A masking layer is formed and patterned in the fuse area to define the fuse element to be subsequently formed, and a barrier material such as titanium tungsten is then formed over all surfaces of the device for subsequent formation. act as a barrier metal between the aluminum metallization and the substrate. A metallization layer is then formed over the entire surface of the device. A metal mask is then formed over the device and undesired portions of the metallization layer are removed to leave the desired metallization wiring pattern. At the same time, the layer of fuse material is partially removed in areas not protected by the remaining portions of the metallization layer or by the masking layer covering the desired fuse.

This masking layer acts as an etchant barrier during plasma etching of the metallization, masking the fuse element from the plasma etchant.

In another embodiment of the invention, the tungsten layer described above is replaced with a layer of titanium tungsten that acts as both a fuse element and a barrier metal. In this embodiment, a subsequent titanium tungsten layer is not required.

EXAMPLES Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figures 2a-2e illustrate one embodiment of a fusible link construction constructed in accordance with the present invention and one embodiment of a method of manufacturing such a construction. As shown in Figure 2a, substrate 20 has one or more active areas containing elements such as transistors. Substrate 20
On top is formed a layer 21 of a meltable material, such as tungsten, titanium tungsten or nichrome.

Although not shown in FIGS. 2a to 2e, the substrate 20 is
A layer of fusible material 21 comprises a semiconductor layer on which an insulating layer is formed, such that it is insulated from the underlying semiconductor material by the insulating layer. Layer 21 is typically formed to a thickness within the range of about 200 Å to 800 Å, for example, by known sputtering techniques. Of course, it should be understood that the same applies regardless of the type of meltable material used, its thickness, or the method of its formation.

Referring to FIG. 2a, a layer 22 of masking material, for example consisting of an oxide, a nitride, or a combination thereof.
A fuse is formed on layer 21 in the area where it is to be formed. In one embodiment of the invention, masking layer 22 is formed by oxide CVD to a thickness within the range of approximately 1000 Å to 200 OA. Using defined photolithographic and etching techniques, the masking layer 22 is
is patterned as shown in FIG. 2a to protect the portion of layer 21 that is to remain as a fuse.

Referring to Figure 2b, a barrier layer 23 is formed on the surface of the device. The barrier layer 23 has a thickness of approximately 1000 Å to 200 Å.
It is formed from sputtered titanium tungsten to a thickness in the range of 0A. Of course, any other suitable barrier material, thickness and method of formation may be used, and the layer of barrier material may be omitted if desired.

Referring to Figure 2c, a metallization layer 24 is then formed on the surface of the device. Metallization layer 2
4 is typically aluminum, aluminum alloy,
or formed from a multilayer grooved body with a final layer acting as an anti-reflective coating.

The metallization layer 24 is typically formed to a thickness of about 5000 Å to 1500 Å, for example, by sputtering techniques.
It is formed to a thickness within the range of A.

Referring to FIG. 2d, a layer of masking material 25, such as photoresist, is then formed over the metallization layer 24 to mark various active areas within the substrate 20, fuses to be subsequently formed, and higher level electrical wiring (
exposing the portions of the metallization layer 24 that are to be removed in order to cause the metallization layer 24 to generate a desired pattern for providing electrical interconnections between the metallization layer 24 and the metallization layer 24 (not shown). As shown in FIG. 2d, the patterned masking material 25 leaves an opening 26 above the two fuse devices to be subsequently formed and exposes other areas of the metallization layer 24 to be removed.

Referring to FIG. 2e, then, for example, CD2. C.C.
Q4. The unmasked portions of the metallization layer 24 are removed by plasma etching in an atmosphere or a combination thereof. In addition to removing the unmasked portions of metallization layer 24, this etch forms a trench 27 that etches through the portion of barrier layer 23 that is two fuse devices above.
And depending on the etching characteristics of the masking layer 28,
Etching is performed not through the entire masking layer 28, but somewhat into it.

The masking layer 22 is hardly etched during this period due to the relatively high etch selectivity with respect to the materials forming the metallization layer 24, the barrier layer 23, and the fusible material of the layer 21. This etching also removes undesired portions of the barrier layer 23 and the fusible material layer 21 outside the fuse area, if these portions have been exposed by removing the overlying metallization. . In this way, an etch that is not selective with respect to the metallization material of metallization layer 24, the barrier material of barrier layer 23, and the fuse material of fuse layer 21 is used to simultaneously remove undesired portions of each of these three layers. 2, while desired portions of metallization layer 24 are protected by masking layer 25 and desired portions of fuse layer 21, such as fuse device 29, are protected by masking layer 28.

In accordance with the present invention, the embodiment of FIG. 2e uses a separate barrier layer 23 of arbitrary thickness, thereby creating undesired alloying between the metallization layer 24 and the substrate 20. This allows the thickness of the fuse layer 21 to be as thin as practically possible, for example within the range of 200 to 50 OA. fuse material layer 2
By allowing 1 to be as thin as practicable, it is possible to reduce the fusing voltages and currents required during programming.

In another embodiment of the invention, as shown in FIG.
The single layer 31 is used either as a layer of a fusible material, such as tungsten, or as a layer that acts as both a fusible material and a barrier metal, such as titanium tungsten. In this embodiment, no further layers, such as layer 23 in FIG. 2e, are required.

According to the present invention, either the structure of FIG. 2e or the structure of FIG. 3 can be used to form a bar-shaped fuse having a rectangular shape in plan view instead of the bow-tie-shaped fuse of FIG. 1c. It is possible to use it for According to the present invention, the fuse pattern is defined in the masking layer 22 prior to patterning the metallization layer 24, so that the photoresist layer used to define the fuse layer is free from the metallization layer. It is not affected by distortion or reflections. Thus, the present invention allows for the creation of smaller fuses with higher reliability than was previously possible.

Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course it is.

[Brief explanation of the drawing]

FIGS. 1a to 1C are illustrations showing a typical prior art fuse element and its manufacturing method, and FIG. 1d is an illustration showing the problem of notching caused by reflection from the sidewalls of the metallization layer. Figures 2a to 2e are explanatory diagrams at each stage of a method of manufacturing a fuse element according to an embodiment of the present invention, and Figure 3 is a construction based on another embodiment of the present invention. FIG. (Explanation of symbols) 20: 21: 22: 23: 24: 27 = 29; Substrate Melting material layer Masking material layer Barrier layer Metallization layer structure Fuse device

Claims (1)

[Claims] 1. A method of forming a fuse in an integrated circuit, comprising forming a layer of a fusible material on the surface of a substrate, and adding remaining portion of the layer of fusible material to act as a fuse. forming a patterned layer of a masking material over the portion to be removed; forming a metallization layer on the surface of the device; exposing the portion of the metallization layer to be removed with an etchant; A method comprising the steps of removing undesired portions of a masking layer, the etchant not etching through the layer of masking material. 2. A method according to claim 1, characterized in that the layer of meltable material comprises tungsten or titanium tungsten. 3. The method of claim 1, wherein the layer of masking material comprises an oxide, a nitride, or a combination of an oxide and a nitride. 4. A method according to claim 1, characterized in that the metallization layer comprises aluminum, an aluminum alloy, or a multilayer composition comprising an anti-reflection coating. 5. The method of claim 1, wherein the etchant is capable of etching the metallization and the fusible material without significant selectivity. 6. The method according to claim 5, wherein the etchant is a plasma. 7. In claim 6, the plasma comprises:
Cl_2, CCl_4, or a combination thereof. 8. The method of claim 1, wherein the layer of fusible material comprises tungsten formed to a thickness within the range of about 200 Å to 500 Å. 9. The method of claim 1, wherein the layer of fusible material comprises titanium tungsten formed to a thickness within the range of approximately 200 Å to 500 Å. 10. Claim 1, further comprising the step of forming a layer of barrier material on the surface of the layer of meltable material and the patterned layer of masking material. how to. 11. The method of claim 10, wherein the layer of masking material comprises an oxide, a nitride, or a combination of an oxide and a nitride. 12. The method of claim 10, wherein the metallization layer comprises aluminum, an aluminum alloy, or a multilayer composition comprising an anti-reflection coating. 13. The method of claim 10, wherein the etchant is capable of etching the metallization, the fusible material, and the barrier material without significant selectivity. 14. The method of claim 13, wherein the etchant is a plasma. 15. The method of claim 13, wherein the plasma comprises Cl_2, CCl_4, or a combination thereof. 16. The method of claim 13, wherein the layer of fusible material comprises tungsten and the layer of barrier material comprises titanium tungsten. 17. The method of claim 16, wherein the tungsten layer is formed to a thickness within the range of approximately 200 Å to 500 Å. 18. The method of claim 16, wherein the titanium tungsten layer is formed to a thickness within the range of about 1000 Å to 2000 Å. 19. The method of claim 1, wherein the fuse is substantially rectangular in plan view. 20. In an integrated circuit arrangement, a semiconductor substrate having a top surface, a layer of meltable material formed on the top surface of the substrate, a layer of meltable material formed on the top surface of the substrate, the meltable material in a pattern defining the location of one or more fuses; a layer of a masking material formed on the layer of meltable material, a metallization layer formed on the upper surface of the substrate, the layer of meltable material, and the layer of masking material. An integrated circuit structure, wherein the metallization layer is patterned into a desired electrical wiring pattern. 21. The integrated circuit structure of claim 20, wherein the layer of meltable material comprises tungsten or titanium tungsten. 22. The integrated circuit structure of claim 20, wherein the layer of masking material comprises an oxide, a nitride, or a combination of an oxide and a nitride. 23. The integrated circuit structure of claim 20, wherein the metallization layer comprises aluminum, an aluminum alloy, or a multilayer structure comprising an antireflective coating. 24. The integrated circuit structure of claim 20, wherein the layer of fusible material comprises tungsten formed to a thickness within the range of approximately 200 Å to 500 Å. 25. The integrated circuit structure of claim 20, wherein the layer of fusible material comprises titanium tungsten formed to a thickness within the range of approximately 200 Å to 500 Å. 26. Claim 20, further comprising a layer of barrier material formed between the metallization layer and the layer of meltable material and the patterned layer of masking material. An integrated circuit structure characterized by: 27. The integrated circuit structure of claim 26, wherein the layer of masking material comprises an oxide, a nitride, or a combination of an oxide and a nitride. 28. The integrated circuit structure of claim 26, wherein the metallization layer comprises aluminum, an aluminum alloy, or a multilayer structure comprising an antireflective coating. 29. The integrated circuit arrangement of claim 26, wherein the layer of meltable material comprises tungsten and the layer of barrier material comprises titanium tungsten. body. 30. The integrated circuit structure of claim 29, wherein the tungsten layer is formed to a thickness within the range of approximately 200 Å to 500 Å. 31. The integrated circuit structure of claim 29, wherein the titanium tungsten layer is formed to a thickness within the range of approximately 1000 Å to 2000 Å.