JP2560030B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2560030B2 JP2560030B2 JP62112967A JP11296787A JP2560030B2 JP 2560030 B2 JP2560030 B2 JP 2560030B2 JP 62112967 A JP62112967 A JP 62112967A JP 11296787 A JP11296787 A JP 11296787A JP 2560030 B2 JP2560030 B2 JP 2560030B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- wiring
- stress
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔概要〕 本発明は、半導体ウェハに多層配線を形成するとき、
層間絶縁膜の表面にイオン打ち込み技術（以下I.I技術
という。）によりイオンを打ち込んでストレスを緩和す
ることを特徴としている。これにより層間絶縁膜のクラ
ックを防止したり、これを起因とする金属配線の断線を
防止することが可能となる。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention provides:
The feature is that ions are implanted into the surface of the interlayer insulating film by an ion implantation technique (hereinafter referred to as II technique) to reduce the stress. This makes it possible to prevent cracks in the interlayer insulating film and prevent breakage of metal wiring due to the cracks.
本発明は半導体装置の製造方法であって、更に詳しく
言えば半導体ウェハ上に層間絶縁膜を形成する方法に関
するものである。The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an interlayer insulating film on a semiconductor wafer.
第３図は従来例に係る半導体ウェハの層間絶縁膜を形
成する方法を説明する断面図および上面図である。FIG. 3 is a sectional view and a top view illustrating a method of forming an interlayer insulating film of a semiconductor wafer according to a conventional example.
まず半導体ウエハ１の上部に所定回路パターンに従っ
て第１層目のAl配線２を形成し、次に第１層目のAl配線
２の上部に層間絶縁膜としてPSG膜３を形成する。次い
で所定の回路パターンに従って第２層目のAl配線４を形
成し、PSG膜５を形成して絶縁する。このようにして層
間絶縁膜を金属配線毎に積層して順次形成する（同図
（ａ））。First, the first-layer Al wiring 2 is formed on the semiconductor wafer 1 according to a predetermined circuit pattern, and then the PSG film 3 is formed as an interlayer insulating film on the first-layer Al wiring 2. Next, the second-layer Al wiring 4 is formed according to a predetermined circuit pattern, and the PSG film 5 is formed and insulated. In this way, the interlayer insulating film is laminated on each metal wiring and sequentially formed (FIG. 9A).
ところで、第３図（ｂ）および（ｃ）に示すように、
従来例によればPSG膜３の上にAl配線４を形成する場合
や、Al配線４の上にPSG膜５を形成する場合に、先に形
成されたPSG膜３に熱処理等によるストレス（応力）が
加わることがある。これによりAl配線４に歪を生じて断
線部分７の発生を誘発したり、PSG膜５にクラック６を
発生させることがある（同図（ｂ）は断面図であり、
（ｃ）は上面図である。）。By the way, as shown in FIGS. 3 (b) and 3 (c),
According to the conventional example, when the Al wiring 4 is formed on the PSG film 3 or when the PSG film 5 is formed on the Al wiring 4, stress (stress) due to heat treatment or the like is applied to the PSG film 3 previously formed. ) May be added. As a result, strain may be generated in the Al wiring 4 to induce the generation of the disconnection portion 7, or cracks 6 may be generated in the PSG film 5 (the same figure (b) is a sectional view,
(C) is a top view. ).
また、これを起因とするAl配線に突起が生じたり、あ
るいは陥没したりして、電気的特性に悪影響を及ぼすと
いう問題がある。In addition, there is a problem that a protrusion is generated in the Al wiring or a depression is caused due to this, which adversely affects the electrical characteristics.
本発明はかかる従来例の問題に鑑みて創作されたもの
であり、層間絶縁膜のストレスを緩和してAl配線の断線
の防止を可能とする半導体装置の製造方法の提供を目的
とする。The present invention was created in view of the problems of the conventional example, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of relieving stress in an interlayer insulating film and preventing disconnection of an Al wiring.
本発明の半導体装置の製造方法は、半導体ウエハの上
部に第１の金属配線を形成する工程と、前記第１の金属
配線を形成した半導体ウエハの全面に絶縁膜を形成する
工程と、前記絶縁膜の表面から不活性イオンを打ち込ん
で予め該絶縁膜の表面に欠陥層を形成して残留させる工
程と、前記欠陥層を残留させた絶縁膜の上部に第２の金
属配線を形成する工程とを有することを特徴とする。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first metal wiring on a semiconductor wafer, a step of forming an insulating film on the entire surface of the semiconductor wafer on which the first metal wiring is formed, A step of implanting inert ions from the surface of the film to form a defect layer on the surface of the insulating film and leaving the defect layer in advance; and a step of forming a second metal wiring on the insulating film in which the defect layer remains. It is characterized by having.
本発明に係る製造方法において、前記絶縁膜がPSG膜
又はBPSG膜であり、前記不活性イオンがAr+またはN+イ
オンであることを特徴とし、上記目的を達成する。In the manufacturing method according to the present invention, the insulating film is a PSG film or a BPSG film, and the inactive ions are Ar + or N + ions, and the above object is achieved.
本発明の製造方法によれば、第１の金沿配線が形成さ
れた半導体ウエハの全面に絶縁膜を形成し、この絶縁膜
の表面から不活性イオンを打ち込むことにより、予め絶
縁膜の表面に欠陥層を形成して残留させているので、第
２の金属配線の絶縁工程等で受ける熱ストレスが、この
欠陥層によって吸収できる。熱ストレスが緩和されるこ
とで、絶縁膜と配線の熱膨張率が相違することによるク
ラックや断線が防止できる。According to the manufacturing method of the present invention, an insulating film is formed on the entire surface of the semiconductor wafer on which the first gold wiring is formed, and inert ions are implanted from the surface of the insulating film, so that the surface of the insulating film is previously formed. Since the defect layer is formed and left, the thermal stress received in the insulating step of the second metal wiring or the like can be absorbed by the defect layer. Since the thermal stress is relieved, cracks and breaks due to the difference in thermal expansion coefficient between the insulating film and the wiring can be prevented.
また、本発明の製造方法では、絶縁膜にPSG膜又はBPS
G膜を用いているのでで、上述の欠陥層によって、熱ス
トレスを吸収する上で、第１の金属配線と第２の金属配
線との間の絶縁膜（層間絶縁膜）にPSG膜又はBPSG膜等
の無機絶縁膜を用いることにより、ポリイミド絶縁膜
（有機絶縁膜）等の分極作用を原因とする電気的な欠点
を無くすことができる。In addition, in the manufacturing method of the present invention, a PSG film or BPS is used as the insulating film.
Since the G film is used, the PSG film or the BPSG film is formed on the insulating film (interlayer insulating film) between the first metal wiring and the second metal wiring in absorbing the thermal stress by the above-mentioned defect layer. By using an inorganic insulating film such as a film, it is possible to eliminate electrical defects caused by the polarization effect of the polyimide insulating film (organic insulating film).
なお、本発明ではAr+またはN+イオン等の不活性イオ
ンを用いているので、絶縁膜中においてイオン再結合を
招くことなく、格子間に熱ストレス吸収用の空孔（欠陥
層）を形成することができる。In the present invention, since inert ions such as Ar + or N + ions are used, vacancies (defect layers) for absorbing thermal stress are formed between lattices without causing ionic recombination in the insulating film. can do.
次に図を参照しながら本発明の実施例について説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の実施例に係る半導体ウェハの層間絶
縁膜を形成する方法を説明する図である。FIG. 1 is a diagram illustrating a method of forming an interlayer insulating film of a semiconductor wafer according to an embodiment of the present invention.
まず、半導体ウェハ11の上部に所定回路パターンに従
って第１層目のAl配線12を形成する（同図（ａ））。First, the first-layer Al wiring 12 is formed on the semiconductor wafer 11 in accordance with a predetermined circuit pattern (FIG. 10A).
次に、第１層目のAl配線12のパターンの全面に層間絶
縁のためのPSG膜（厚さ0.5〜1.0μｍ）13を熱処理して
形成する（同図（ｂ））。Next, a PSG film (thickness of 0.5 to 1.0 μm) 13 for interlayer insulation is formed on the entire surface of the pattern of the first-layer Al wiring 12 by heat treatment (FIG. 2B).
次いで、PSG膜13の表面の全域にI.I技法によってAr+
またはN+イオン14を打ち込んで欠陥層15を形成する（同
図（ｃ））。Then, Ar + is applied to the entire surface of the PSG film 13 by the II technique.
Alternatively, N + ions 14 are implanted to form a defect layer 15 (FIG. 7C).
次いで、欠陥層15を形成したPSG膜13の上部に第２層
目のAl配線16を所定の回路パターンに従って形成する
（同図（ｄ））。Next, the second-layer Al wiring 16 is formed on the PSG film 13 on which the defect layer 15 is formed in accordance with a predetermined circuit pattern (FIG. 7D).
第２図は発明者らの実験データに基づく本発明の実施
例に係るI.I技法によるPSG膜のストレスの緩和を説明す
る図である。図において横軸はPSG膜の表面にイオンを
打ち込むエネルギー、縦軸はイオン打ち込みをしないPS
G膜のストレスに対するI.I後のストレスの比（ストレス
比）である。FIG. 2 is a diagram for explaining stress relief of the PSG film by the II technique according to the embodiment of the present invention based on the experimental data of the inventors. In the figure, the horizontal axis is the energy for implanting ions on the surface of the PSG film, and the vertical axis is the PS without ion implantation.
It is a ratio of stress after II to stress of G membrane (stress ratio).
なお、ストレス比が“0"に近づく程、PSG膜のストレ
スは緩和される。たとえば同図に示すようにイオン打ち
込みエネルギーを80KeVから160Kevに強めることによっ
てストレス比は7/10になる。すなわちPSG膜のストレス
は明確に減少している。なお、打ち込みエネルギーを更
に強めることによって、ストレスをより減少させること
ができると予想される。The stress of the PSG film is alleviated as the stress ratio approaches “0”. For example, as shown in the figure, by increasing the ion implantation energy from 80 KeV to 160 Kev, the stress ratio becomes 7/10. That is, the stress on the PSG membrane is clearly reduced. It is expected that the stress can be further reduced by further increasing the implantation energy.
このようにして、PSG膜を形成する毎にI.I技法により
イオンを打ち込んで該PSG膜の表面に欠陥層を形成す
る。これにより、PSG膜のストレスを緩和してAl配線の
断線を防止し、PSG膜のクラックを防止し、Al配線の突
起や陥没を防止することができる。In this way, every time the PSG film is formed, ions are implanted by the II technique to form a defect layer on the surface of the PSG film. As a result, stress in the PSG film can be relieved to prevent breakage of the Al wiring, cracks in the PSG film can be prevented, and protrusions and depressions of the Al wiring can be prevented.
なお実施例ではPSG膜について説明したが、BSG膜等の
他の層間絶縁膜についても適用できることは勿論であ
る。Although the PSG film has been described in the embodiment, it is needless to say that it can be applied to other interlayer insulating films such as a BSG film.
以上説明したように、本発明によれば層間絶縁膜のス
トレスを緩和することができる。これにより層間絶縁膜
のクラックを防止すること、Al配線の突起、陥没および
断線を防止することが可能となる。As described above, according to the present invention, the stress of the interlayer insulating film can be relieved. This makes it possible to prevent cracks in the interlayer insulating film and to prevent protrusions, depressions and breaks in the Al wiring.
また本発明によれば、電気的特性の良好な多層配線構
造を形成できるので、信頼性の高い半導体装置を製造す
ることが可能となる。Further, according to the present invention, since a multilayer wiring structure having good electric characteristics can be formed, it is possible to manufacture a highly reliable semiconductor device.
第１図は本発明の実施例に係る半導体装置の製造方法を
説明する図、 第２図は本発明の実施例に係るI.I技法による層間絶縁
膜のストレスの緩和を説明する図、 第３図は従来例の半導体装置の製造方法を説明する図で
ある。 （符号の説明） 1,11……半導体ウェハ、 2,12……第１層目のAl配線、 3,5,13……PSG膜、 4,16……第２層目のAl配線、 ６……クラック、 ７……断線部分、 14……Ar+またはN+イオン、 15……欠陥層。FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining stress relief of an interlayer insulating film by a technique II according to the embodiment of the present invention, and FIG. FIG. 6 is a diagram illustrating a method of manufacturing a conventional semiconductor device. (Explanation of symbols) 1,11 ... Semiconductor wafer, 2,12 ... Al wiring of the first layer, 3,5,13 ... PSG film, 4,16 ... Al wiring of the second layer, 6 …… Crack, 7 …… Disconnection, 14 …… Ar + or N + ions, 15 …… Defect layer.
フロントページの続き (56)参考文献 特開 昭58−101439（ＪＰ，Ａ) 特開 昭53−105390（ＪＰ，Ａ) 特開 昭58−168263（ＪＰ，Ａ) 特開 昭62−49644（ＪＰ，Ａ) 特開 昭62−60242（ＪＰ，Ａ) 特開 昭60−132345（ＪＰ，Ａ)Continuation of the front page (56) Reference JP-A-58-101439 (JP, A) JP-A-53-105390 (JP, A) JP-A-58-168263 (JP, A) JP-A-62-49644 (JP , A) JP 62-60242 (JP, A) JP 60-132345 (JP, A)
Claims (2)
成する工程と、前記第１の金属配線を形成した半導体ウ
エハの全面に絶縁膜を形成する工程と、前記絶縁膜の表
面から不活性イオンを打ち込んで予め該絶縁膜の表面に
欠陥層を形成して残留させる工程と、前記欠陥層を残留
させた絶縁膜の上部に第２の金属配線を形成する工程と
を有することを特徴とする半導体装置の製造方法。1. A step of forming a first metal wiring on a semiconductor wafer, a step of forming an insulating film on the entire surface of the semiconductor wafer on which the first metal wiring is formed, and The method further comprises the steps of implanting active ions to form a defect layer on the surface of the insulating film and leaving the defect layer in advance, and forming a second metal wiring on the insulating film having the defect layer left. And a method for manufacturing a semiconductor device.
記不活性イオンがAr+またはN+イオンであることを特徴
とする特許請求の範囲１記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is a PSG film or a BPSG film, and the inactive ions are Ar + or N + ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62112967A JP2560030B2 (en) | 1987-05-09 | 1987-05-09 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62112967A JP2560030B2 (en) | 1987-05-09 | 1987-05-09 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63278258A JPS63278258A (en) | 1988-11-15 |
| JP2560030B2 true JP2560030B2 (en) | 1996-12-04 |
Family
ID=14600026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62112967A Expired - Lifetime JP2560030B2 (en) | 1987-05-09 | 1987-05-09 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2560030B2 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58101439A (en) * | 1981-12-12 | 1983-06-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58168263A (en) * | 1982-03-30 | 1983-10-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6092633A (en) * | 1983-10-26 | 1985-05-24 | Sony Corp | Manufacture of semiconductor device |
| US4535528A (en) * | 1983-12-02 | 1985-08-20 | Hewlett-Packard Company | Method for improving reflow of phosphosilicate glass by arsenic implantation |
| JPS6249644A (en) * | 1985-08-29 | 1987-03-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6260242A (en) * | 1985-09-09 | 1987-03-16 | Nec Corp | Manufacture of semiconductor device |
-
1987
- 1987-05-09 JP JP62112967A patent/JP2560030B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63278258A (en) | 1988-11-15 |
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|---|---|---|---|
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