JPH02170420A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH02170420A JPH02170420A JP32523188A JP32523188A JPH02170420A JP H02170420 A JPH02170420 A JP H02170420A JP 32523188 A JP32523188 A JP 32523188A JP 32523188 A JP32523188 A JP 32523188A JP H02170420 A JPH02170420 A JP H02170420A
- Authority
- JP
- Japan
- Prior art keywords
- film
- opening
- depositing
- conductive layer
- opening part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001678 irradiating effect Effects 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 239000010425 asbestos Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052895 riebeckite Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子の製造方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
第２図に従来例を示す。同図はＳｉ基板１及び該基板１
上の絶縁１模３内に形成した第１の導゛１セＭ２と、第
２の導電層４にそれぞれ達する開口部を絶縁膜３に設け
て、ＡｌＱ１０て２つの導電層２，４を結線した例であ
る。FIG. 2 shows a conventional example. The figure shows a Si substrate 1 and the substrate 1.
Openings reaching the first conductive layer M2 formed in the upper insulation layer 1 pattern 3 and the second conductive layer 4 are provided in the insulating film 3, and the two conductive layers 2 and 4 are connected using AlQ10. This is an example.
上記構造によるときには、２つの導電層２，４のそれぞ
れに、開口部（コンタクト孔）を作製しなければならな
いので１面積効率が悪い。また、開口部と深さの比、す
なわちアスベスト比が大きくなると、第２図左側の開口
部に示すように、 Ａｌ膜が開口部下端で断線する可能
性がある。When using the above structure, since openings (contact holes) must be formed in each of the two conductive layers 2 and 4, the per-area efficiency is poor. Furthermore, if the ratio of the opening to the depth, that is, the asbestos ratio becomes large, there is a possibility that the Al film will break at the lower end of the opening, as shown in the opening on the left side of FIG.
したがって、今後の半導体素子動向を考えるとき、素子
の微細化は必須であり、かつ、開口部のサイズは小さく
なり、また、開口部数は太くなるのは必至である。した
がって、開口部の数が多いことや、アスベスト比が大き
いことは今後のＬＳＩにとって改善すべき大きな課題と
なっている。Therefore, when considering future trends in semiconductor devices, miniaturization of devices is essential, and it is inevitable that the size of openings will become smaller and the number of openings will increase. Therefore, the large number of openings and the large asbestos ratio are major issues that need to be improved for future LSIs.
本発明の目的は上記；ｉｇを解決した半導体素子の製造
方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above problems.
上記目的を達成するため、本発明による半導体素子の製
造方法においては、Ｓｉ基板表面に第１の導電層を形成
した後、第１の絶縁膜を堆積する工程と、半導体層を堆
積し、第２の導電層を前記半導体層中に形成した後、第
２の絶縁膜を堆積する工程と、前記第１の絶縁膜と半導
体層と第２の絶縁膜とを貫通し、第１の導電層にとどく
開口部を設ける工程と、第２の半導体膜を堆積した後、
Ａｌ膜を堆積する工程と、その後エネルギー光で照射す
る工程とを含むものである。In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive layer on the surface of a Si substrate and then depositing a first insulating film; a step of depositing a second insulating film after forming a second conductive layer in the semiconductor layer; After the step of forming the opening and depositing the second semiconductor film,
This method includes a step of depositing an Al film and a subsequent step of irradiating with energetic light.
以下にこの発明について図面を参照して詳細に説明する
。The present invention will be explained in detail below with reference to the drawings.
実施例はＳｉ基板中の１９拡散層とｐｏｌｙ −Ｓｉに
よるｐ＋拡散層の接続を例にとり説明する。The embodiment will be explained by taking as an example a connection between a 19 diffusion layer in a Si substrate and a p+ diffusion layer using poly-Si.
第１図（ａ）はＳｉ基板１に第１の導電層（ｎ＋拡散層
）２を作製した状態である。このｎ′拡散層はｐ又はＡ
ｓのイオン注入又は熱拡散によって形成できる。FIG. 1(a) shows a state in which a first conductive layer (n+ diffusion layer) 2 is formed on a Si substrate 1. As shown in FIG. This n' diffusion layer is p or A
It can be formed by ion implantation or thermal diffusion of s.
次に第１図（ｂ）のように絶縁膜３としてＬＰＣＶＤ−
３ｉＯ□を約１ｔ１ｍ堆積し、さらに第２の導電層４と
してｐｏｌｙ −Ｓｉを約０．５．、 ＬＰＣＶＤ法に
より堆積する。実施例ではボロンをイオン注入又は熱拡
散により導入し、第２の導ｔ１ｉｋ４４をρ００拡散と
した。第１図（ｃ）において、第２の導電層４の上に５
０００人ＬＰＣＶＤ−５ｉＯ□を堆積し、これを絶縁膜
５とした。Next, as shown in FIG. 1(b), as the insulating film 3, LPCVD-
3iO□ was deposited for about 1t1m, and poly-Si was further deposited for about 0.5m as the second conductive layer 4. , deposited by LPCVD method. In the embodiment, boron was introduced by ion implantation or thermal diffusion, and the second conductor t1ik44 was ρ00 diffusion. In FIG. 1(c), 5
000 LPCVD-5iO□ was deposited, and this was used as the insulating film 5.
次に、ＰＲ工程とドライエッチ技術とを用いて。Next, using a PR process and dry etch technology.
第１図（ｄ）に示すように第１の導電層２に達する開口
部９を形成した。その後、ＬＰＣＶＤ法によりＳｉ膜６
を４００人形成し、その上に１−厚のＡｌＱ１０スパッ
タ法により形成した。この状態では図示のようにＡｌＱ
１０開口部９内で一部が断線していることがある。その
後、第１図（ｄ）のようにＰＲ工程とドライエッチとに
より、開口部９内及びその周辺のＡｌＱ１０Ｓｉ膜６を
残して、他の絶縁ＩＩ ５上のＡｌＱ１０Ｓｉ膜６とを
除去した。第１図（ｅ）において、レーザ光などのエネ
ルギー光をウェハ上に照射し、ＡｌＱ１０溶融させる。As shown in FIG. 1(d), an opening 9 reaching the first conductive layer 2 was formed. After that, the Si film 6 was formed by LPCVD method.
400 layers were formed, and 1-thick AlQ10 was formed thereon by sputtering. In this state, AlQ
10 A part of the wire may be broken within the opening 9. Thereafter, as shown in FIG. 1(d), the AlQ10Si film 6 on the other insulating layer 5 was removed by a PR process and dry etching, leaving the AlQ10Si film 6 in and around the opening 9. In FIG. 1(e), energy light such as laser light is irradiated onto the wafer to melt AlQ10.
これにより、Ａｌ１−３ｉ膜８が形成され、且つＡｌＱ
１０表面が平坦に均られて開口部内の下端のＡｌＱ１０
断線が接続される。As a result, an Al1-3i film 8 is formed, and an AlQ
10 surface is flattened and the lower end inside the opening is AlQ10
Disconnected wires are connected.
以上実施例では、第１の導電層としてｎｏ、第２の導電
層としてｐ３としたが、この組み合せに特に制限はない
。In the above embodiments, No is used as the first conductive layer, and P3 is used as the second conductive layer, but there is no particular restriction on this combination.
以上のように本発明によるときは、２つの導電層の接続
を１つの開口部のみで行うので、素子の密度を上昇させ
ることができ、また、開口部のアスペクト比が大きくな
っても、Ａｌのリフローを使用するため、断差に起因す
る断線を防止できる効果を有する。As described above, according to the present invention, since the two conductive layers are connected only through one opening, the density of the element can be increased, and even if the aspect ratio of the opening becomes large, the Al Since it uses reflow, it has the effect of preventing wire breakage caused by a difference in line.
第１図（ａ）〜（ｅ）は本発明を示す実施例を工程順に
示す断面図、第２図は従来例を示す断面図である。FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing a conventional example.
Claims (1)
の絶縁膜を堆積する工程と、半導体層を堆積し、第２の
導電層を前記半導体層中に形成した後、第２の絶縁膜を
堆積する工程と、前記第１の絶縁膜と半導体層と第２の
絶縁膜とを貫通し、第１の導電層にとどく開口部を設け
る工程と、第２の半導体膜を堆積した後、Ａｌ膜を堆積
する工程と、その後エネルギー光で照射する工程とを含
むことを特徴とする半導体素子の製造方法。(1) After forming the first conductive layer on the surface of the Si substrate,
a step of depositing a second insulating film after depositing a semiconductor layer and forming a second conductive layer in the semiconductor layer; and a step of depositing a second insulating film between the first insulating film and the semiconductor layer. a step of providing an opening that penetrates the and second insulating film and reaching the first conductive layer; a step of depositing an Al film after depositing the second semiconductor film; and a step of irradiating with energetic light. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32523188A JPH02170420A (en) | 1988-12-22 | 1988-12-22 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32523188A JPH02170420A (en) | 1988-12-22 | 1988-12-22 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02170420A true JPH02170420A (en) | 1990-07-02 |
Family
ID=18174491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32523188A Pending JPH02170420A (en) | 1988-12-22 | 1988-12-22 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02170420A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110759A (en) * | 1988-12-20 | 1992-05-05 | Fujitsu Limited | Conductive plug forming method using laser planarization |
| US5219790A (en) * | 1991-07-17 | 1993-06-15 | Sharp Kabushiki Kaisha | Method for forming metallization layer of wiring in semiconductor integrated circuits |
| US5288664A (en) * | 1990-07-11 | 1994-02-22 | Fujitsu Ltd. | Method of forming wiring of semiconductor device |
-
1988
- 1988-12-22 JP JP32523188A patent/JPH02170420A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110759A (en) * | 1988-12-20 | 1992-05-05 | Fujitsu Limited | Conductive plug forming method using laser planarization |
| US5288664A (en) * | 1990-07-11 | 1994-02-22 | Fujitsu Ltd. | Method of forming wiring of semiconductor device |
| US5219790A (en) * | 1991-07-17 | 1993-06-15 | Sharp Kabushiki Kaisha | Method for forming metallization layer of wiring in semiconductor integrated circuits |
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