JPS6161444A - Multilayer interconnection - Google Patents

Abstract

PURPOSE:To enable the electric connection can be easily performed even if the diameter of a hole becomes small, by a method wherein the surface of under layer metal at the area containing just under part of the hole is made protruded type. CONSTITUTION:A metallic wiring 203 of the under layer is formed on a silicon oxide film 202 which is formed on a silicon substrate 201. Next, a metallic patch 204 is formed by the same material with the under layer metal or the third metal which connects well electrically the metallic wires of under layer and upper layer. Next, a flattened insulating film 205 is formed by the spin-on method or etch back method and the like. Finally, a hole 206 and metallic wiring 207 of the upper layer are formed. Since the hole 206 is opened at the thin part because the insulating film 205 is flattened, the second metallic wiring 207 will not break out at the side of the hole.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a multilayer wiring method, and particularly to a multilayer wiring method that requires fine wiring.

Conventional integrated circuit devices have become denser and a large number of elements are integrated on a single substrate, making the wiring between these elements more complex. For this reason, a method of wiring in multiple layers is used as a multilayer wiring method. In this wiring method, the lower layer metal wiring and the upper layer metal wiring are separated spatially and electrically by an insulator, and a hole is formed in the insulator between the lower layer and the upper layer wiring. Make an electrical connection through this hole. At this time, specifically, first, a lower metal wiring is formed, and an insulating film such as a silicon oxide film or a silicon vacancy film is grown on it to a thickness of about 1 μm, and then a 7-hole photoresist is used. Then, holes are made in the insulator by etching, and then a metal film is grown on the entire surface of the wafer to form an upper metal wiring layer (by etching or etching). At this time, the electrical connection between the lower wiring layer and the upper wiring layer is established by the upper layer metal filling the hole made in the insulating film. However, as the density of integrated circuits increases, the pattern size becomes smaller, and the holes formed in the insulating film are required to have a diameter of 1 μm or less. When the diameter of the hole becomes large in this way, depending on the growth method, it becomes difficult for the upper layer metal to penetrate into the hole, and the electrical connection between the lower layer metal and the upper layer metal becomes difficult. There was a big problem: it was difficult.

OBJECTS Accordingly, the present invention provides a multilayer wiring method that eliminates the above-mentioned problems.

Structure The multilayer wiring method of the present invention includes a step of forming a lower layer metal wiring, a step of increasing the thickness of the lower layer metal wiring in a lower region including a portion connecting the lower layer metal wiring and the upper layer metal wiring,
The structure consists of a step of forming a flattened insulating film on the lower layer metal wiring, a step of making holes in the insulating film on the area where the lower layer metal wiring is thick, and a step of forming the upper layer metal wiring. .

Effects According to the multilayer wiring method of the present invention, holes for electrical connection are formed in the thick portions of the lower metal wiring, so the depth of the holes is small and the diameter of the holes is 1 μm or less. Even if it is small, it has the great advantage that electrical connections can be easily made.

DESCRIPTION OF THE PRIOR ART Next, in order to better understand the present invention, the present invention will be explained using the drawings. FIG. 1 shows a conventional multilayer wiring method. As shown in (a)K above, a lower metal film Na1O3t- is formed on a silicon oxide film 102 formed on a silicon substrate 101, and then An insulating film 104 is formed. Next is insulating film 10
4 is anisotropically etched using plasma using a photoresist as a mask to form a hole 105. Finally, an upper layer metal film #11106 is grown and patterned usually by vacuum evaporation or sputtering. In this conventional multilayer wiring method, the upper layer metal wiring 106 is passed through the hole 105.
An electrical connection cannot be established unless the metal wiring 103 is connected to the underlying metal wiring 103. However, when the hole 105 becomes smaller than 1 μm, the thickness of the insulating film 104 is usually 1 μm or more.
There was a big problem that the side parts of the wire were not thin and could even break.

Embodiment FIG. 2 is a sectional view for explaining the first embodiment of the present invention. First, as shown in FIG. 3A, a lower metal film a203 is formed on the silicon oxide film 202 formed on the silicon substrate 201. Next, as shown in figure (b), the same material as the lower layer metal or the lower and upper layer metal wiring is electrically applied to the area where the hole for electrical connection between the lower layer metal wiring and the upper layer metal wiring is to be formed in the subsequent process. A second metal bi' 204 is formed by the third metal that is well connected to the third metal. Next K
(d) As shown in the figure, a flattened amorphous film 205 is formed by a spin-on method, an etch-back method, or the like. Finally, holes 206 and upper layer metal wiring 207 are formed to obtain the multilayer wiring method of the first embodiment of the present invention. According to the first embodiment, the hole 206 connecting the lower metal wiring 203 and the upper metal wiring 207 is formed in a thinner part of the insulating film 205 because it is flattened. The metal wiring 207 has the advantage of not being disconnected on the side surface of the hole, and this advantage is particularly effective in VLSIs where the hole diameter is 1 μm or less.

FIG. 3 is a sectional view for explaining a second embodiment of the present invention. First, silicon substrate 301 and silicon substrate 302
A lower layer metal wiring 303 is formed on a substrate consisting of the following, and then a metal 304 for connection between the lower layer metal wiring 302 and an upper layer metal wiring to be formed later is formed. Next, as shown in the figure (b), the metal 304 for the connection is anisotropically etched using a mask to form a patterned metal pad 306. Next, as shown in figure (C),
d) Form a flattened insulating film 307 as shown in the figure.

Upper layer metal interconnection #J308 is formed. M2 of this invention
In this embodiment, the connection between the lower layer metal wiring 303 and the upper layer metal wiring 308 is made by a metal pad 306, and this metal pad 306 is formed before the insulating film 307 is formed. This method has the great advantage that there is no need to worry about wire breakage as in conventional methods. Furthermore,
It is said that if a metal such as W, which is resistant to electromagnetic radiation, is used as the metal of the metal pad 306, disconnection due to concentration of current flowing between the lower metal wiring 303 and the upper layer metal wiring 11iI 308 at the connection part can be prevented. It also has major advantages.

FIG. 4 is a sectional view showing a third embodiment of the present invention. Components that are the same as those in the second embodiment are designated by the same numbers, but in this second embodiment, after forming the lower layer metal wiring 303, an energy beam 401 such as a laser beam or an electron beam is applied to a reaction under reduced pressure. A metal bat 402 is formed in gas 403 by applying it perpendicularly to the metal wiring 303 in the lower layer. After that, multilayer wiring is formed by the same steps as in the second embodiment.

In the third embodiment, there is no need for an etching mask for making a connection hole between the lower layer metal wiring and the upper layer metal wiring or for forming the metal pad 401, and the metal of the metal pad can be adjusted to its position. This has the great advantage of allowing you to select any option.

2 to 4 are sectional views for explaining the present invention in detail.

101, 201, 301 in the lap. ...Silicon substrate, 102,202,302 ...Silicon oxide film, 103,106,203,204,20
7,303°306.307,402...Metal, 104,205°307...Insulating film, 10
5,206...hole for connection, 401...
... Energy beam, 403 ... Reactant gas.

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Claims (3)

[Claims] (1) In the multilayer wiring method, an insulating film is interposed between the lower layer metal wiring and the upper layer metal wiring, and the lower layer metal wiring and the upper layer metal wiring are electrically connected through holes made in the insulating film. A multilayer wiring method comprising the step of making the surface of the lower metal in a region immediately below the hole convex. (2) In a multilayer wiring method, an insulating film is interposed between a lower metal wiring and an upper metal wiring, and the lower metal wiring and the upper metal wiring are electrically connected through holes made in the insulating film. A multilayer wiring method characterized by forming a metal for connecting the upper layer and lower layer metal wiring before forming an insulating film. (3) The multilayer wiring method according to claim (2), characterized in that the metal for connecting the lower layer metal wiring and the upper layer metal wiring is formed by selective growth using an energy beam.