JPS6224330A - Fault detecting system for multi-processor - Google Patents

Abstract

PURPOSE:To detect the fault of a processor at an opposite side by providing an action display area for processors to a common memory and making each processor refer to said display area to reset the display patterns with each other. CONSTITUTION:A working state display area ST for processors and a fault code display area FC are provided in a specific address of a common memory CM set between processors 1 and 2. Both processors 1 and 2 refers periodically to the area ST to write their own numbers. Thus it is possible to inform the processor of the remote side that the processor of its own side is working normally. While a fault code is written to the area FC if the processor of its won side has a fault. Thus the contents of the generation of the fault can be delivered to the processor of the remote side. Here it is decided that the processor of the remote side has no working if the area FC is not rewritten for two periods by the processor of the opposite side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a tightly coupled multiprocessor system having a common memory, and more particularly to a mutual processor monitoring method suitable for detecting processor failures.

[Background of the invention]

Known methods for detecting processor failures include a program runaway detection method using a watchdog timer and a processor stop detection method using clock interruption detection.These methods are also used in the case of multiprocessors, but it is difficult to realize these methods. requires dedicated circuitry. (Iso et al., “A Study on Microprocessor System Redundancy Configuration”, Institute of Electronics and Communication Engineers Technical Research Report + Vol-84t Nα, 212
, 5E84-78, November 1984) [Object of the Invention] An object of the present invention is to provide a multiprocessor system having a common memory as described above, in which processors can communicate with each other without providing any additional mechanism other than the common memory. The objective is to provide a function that can detect abnormalities in the other processor.

[Summary of the invention]

A feature of the present invention is that in the multiprocessor system described above, an area for displaying processor operations is provided at a specific address on the common memory, each processor periodically refers to this area, and each other's processors display information in this area. By resetting the patterns that have been created, it is possible to detect an abnormality in the partner processor.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows the configuration of a multiprocessor system that implements the present processor failure detection method. 1st
In the figure, PL and P2 each indicate a processor, and C
M is the common memory between PL and P2, ST is the processor operating status display area in CM, FC is the fault code display area, LMI and LM2 are the local memories of PL and P2, respectively, and CNTl and CNT2 are the local memories of PL and P2, respectively. PL each.

It shows the number of times the Japanese processor failure detection counter of P2 is shown.

FIG. 2 shows an operation flow for displaying the processor operation of the processor p1 shown in FIG. 1 and detecting a fault in the other processor. The process shown in FIG.
If indicates the partner processor number, it is assumed that the partner processor is operating. $i<FC In the determination step 22, F
If C indicates that a failure has occurred, proceed to failure processing step 29;
If it indicates normal operation, the process moves to operation state determination step 23. In step 23, the operating state of the own processor is determined, and if no fault has occurred, the process immediately moves to step 25 to display that the own processor is operating, and if a fault has occurred, the fault code setting step 24 is carried out to respond to the details of the fault. After setting the fault code to FC, the process moves to step 25. In the own processor operation display step 25, the S
The own processor number is written in T, and the fault detection counter is cleared to O in the continuation < CNTi clear step 26, and the process ends.

On the other hand, if the ST continues to indicate its own processor number in ST determination step 21, then continue < CNTi determination step 27
If CNTi is 0, it is assumed that the other processor may have stopped operating, and the
In the NTi increment step 28, 1 is added to CNTi in preparation for the next cycle of activation. Furthermore, if CNT i is 1 in step 27, it indicates that the partner processor has not been operating for two cycles. 1. For example, in the case of a single-system system, failure processing is collected and initial settings for restart are performed, and in the case of a dual-system system, failure information is collected and system switching is performed. Furthermore, when CNTi is determined in step 27, CNTi=
1, that is.

The reason why it is assumed that the partner processor has stopped for the first time when the partner processor has not been operating for two consecutive cycles is to prevent excessive failure detection due to the program execution cycle error between the processors.

Furthermore, if a fault code can be exclusively assigned between processors, the fault code can also be displayed on the ST and the FC can be deleted.

In the above, the example in which there are two processors has been shown in this embodiment, but when there are three or more processors, the common memory C
nC (n is the number of processors) STs and F in M
In addition, n-1 processor failure detection counters are provided in the local memory L M i of each processor Pi, and the processors Pi mutually monitor the operating status of the other n-1 processors. realizable.

However, when the number of processors increases, the number of STs and FCs also becomes too large to be monitored. In that case, an ST corresponding to the processor is provided, and each processor periodically increments the value of the ST corresponding to its own processor by 1 (in case of overflow, returns it to 0), so that the other processors can know the operation of its own processor. Another possible method is to display the .

〔Effect of the invention〕

According to the present invention, in a multiprocessor system having a common memory, each processor can detect each other's faults simply by periodically accessing the operating status display area provided in the common memory. It has the effect of reducing

[Brief explanation of drawings]

Figure 1 is a block diagram of a tightly coupled multiprocessor system that implements this multiprocessor failure detection method, and Figure 2 is a flowchart of the failure detection processing procedure. 2nd hard

Claims (1)

[Claims] In a multiprocessor system having a common memory, an area for displaying the operating status of the processors is provided in the common memory, and a unique identification code is assigned to each processor, so that each processor refers to the above area at the same cycle and performs self-processing. By writing the identification code of the processor, it is possible to notify the other processor that the own processor is operating normally, and by writing the code assigned to the failure type, it is possible to notify the contents of the failure. A fault detection method for a multiprocessor, characterized in that if the area has not been rewritten by the other processor for a period of time, it can be determined that the other processor has stopped operating.