JPH03230254A - Fault detecting method for multiprocessor system - Google Patents

Abstract

PURPOSE:To speedily notify the generation of abnormality to another processor by making interruption on the other processor by a timer only when generating the abnormality in a processor, and activating a fault processing in each processor corresponding to this interruption. CONSTITUTION:When each processor P1 (P2) executes self diagnosis, a shared timer CWDT is reset when the processor is normal. Therefore, the other processor P2 (P1) can be concentrated in the self-processing without loading the interruption. When the fault is generated or when the processor is turned to a stop state, the shared timer CWDT is not reset, and therefore, the interruption is made on the other processor P2(P1) by operating the shared timer CWDT. Then, a fault processing is executed. Thus, the generation of the fault is speedily detected by a simple software.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of mutually monitoring the occurrence of failures in each processor of a tightly coupled multiprocessor system having a common memory.

[Conventional technology]

In a multiprocessor system, it is necessary to detect a failure as soon as possible in each of the processors that make up the system.

As such technology, for example, Japanese Patent Application Laid-Open No. 62-2433
There is an invention disclosed in Publication No. 0.

The invention disclosed in Japanese Unexamined Patent Publication No. 62-24330 operates according to the procedure shown in the flowchart of FIG. 4 in the system configuration shown in FIG.

The system configured as shown in FIG. 3 has two processors PI.
, P2 and their respective local memories LMI, LM2
and a common memory side of both processors PL and P2.

Inside the common memory side, there is a processor operating status display area ST.
and a fault code display area FC, and local memory LM of each processor Pi, P2.
I and LM2 are provided with counters CNTl and CNT2, respectively, for the number of times a partner processor failure is detected.

In the multiprocessor system of Japanese Patent Application Laid-Open No. 62-24330 with such a configuration, two processors PI
, P2, the operation of one processor Pi (for example, processor P1) and the operation of the other processor (P2) for fault detection are shown in the flowchart of FIG.

The processing shown in this fourth flowchart is periodically activated and executed in each processor.

First, in step S21, processor Pi (Pi)
is the processor operating status display area S in the common memory CFI.
Determine the contents of T. If this processor operating status display area ST shows the number of another processor (P2) (≠1=1), the other processor (P2) is operating, that is, a failure has occurred in that processor (P2). It is assumed that they have not done so.

Then, in step S22, processor Pi(P
l) determines the contents of the fault code display area FC.

As a result, if the occurrence of a failure is indicated, proceed to step S29, which will be described later; if the result is indicated to be normal, proceed to step S29.
23, respectively.

In step 323, processor Pi (Pi) determines its own operating state, and if no fault has occurred, the process immediately moves to step S25, and if a fault has occurred, in step S24, a fault corresponding to the fault content is detected. After setting the code in the obstacle court display area FC, the process moves to step 325.

In addition, in step 325, processor Pi (Pi) writes its own processor number "1 (1)" in the processor operating state display area ST in order to notify the other processor (P2) that it is operating. Next step S
26, the counter CN
Clear T i to “0”.

On the other hand, if the determination result in the processor operating state display area ST indicates its own processor number (1) in step 321 (-121), the processor Pi (PL) instructs the other processor failure detection counter CNTi in the next step S27. The value of (CNTI) is determined, and if the result is "0", it is assumed that another processor may have stopped operating. Then, processor Pi (Pl
) adds 1" to the failure detection counter CNTi (CNTI) in step S28 to prepare for the next activation.

Further, in step S27, if the partner processor failure detection counter CNTi (CNTI) is “BI”, then 2
This indicates that the other processor (P2) is not operating during the period, so in this case, the other processor (P2)
) is considered to have stopped working. And the processor Pi
(PL) performs failure processing in step S29, for example, in the case of a single-system system, collection of failure processing and initial settings for restart, and in the case of a dual-system system, collection of failure information and system switching.

Note that when determining the contents of the partner processor fault detection number counter CN'ri (CNTI) in step S27, the content of the partner processor fault detection number counter CN'ri (CNTI) is determined.
(CNTI) - "l", that is, the processor (P2) is considered to have stopped only when the other processor (P2) is not operating for two consecutive cycles. This is to avoid excessive fault detection due to an execution cycle error between the processors PI and P2 of the program shown in FIG.

Furthermore, if fault codes are exclusively assigned between processors, the fault code can also be displayed in the processor operating state display area ST, making the fault code display area FC unnecessary.

[Problems to be Solved by the Invention] In the conventional technology disclosed in Japanese Patent Laid-Open No. 62-24330 as mentioned above, only a shared memory is used for exchanging information between processors. needs to constantly monitor other processors, and if the other processors write their processor numbers to the processor operating status display area ST, even if the other processors fail and stop, their respective The occurrence of an abnormality will not be determined unless the processor rewrites the processor operating state display area ST and returns to the next routine. This causes problems such as a delay in detecting the occurrence of an abnormality and the complexity of the monitoring routine software.

The present invention was made in view of these circumstances, and
The purpose of this invention is to provide a fault detection method for a multiprocessor system that can quickly detect the occurrence of a fault using simple software.

[Means to solve the problem]

The fault detection method for a multiprocessor system according to the present invention is to provide a timer shared by each processor, each processor sequentially performs self-diagnosis, and if normal, resets the shared timer, and if a fault has occurred, the shared timer is reset. The shared timer is left without being reset, and the type of failure is written in correspondence with its own processor number in the common memory.

Then, when the shared timer completes a predetermined period of time, interrupt processing is activated for other processors.

[Effect]

In the fault detection method for a multiprocessor system of the present invention, when each processor performs self-diagnosis, if it is normal, the shared timer is reset, so other processors are not interrupted and can continue their own processing. In addition, if a failure occurs or the processor is stopped, the shared timer will not be reset, so the shared timer will work and interrupt other processors.
Failure handling is performed.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing an example of the configuration of a multiprocessor system to which a fault detection method for a multiprocessor system according to the present invention is applied.

This multiprocessor system consists of two multiprocessors PL, F2, and a common memory C? 1, a shared watchdog timer CWDT, etc.

The common memory CM is provided with operation status display areas Fl and F2 for both processors PI and F2, respectively.

It should be noted that WRI and WR2 send a signal for both processors Pi and F2 to reset the shared watchdog timer CWDT, and CWDTS2. CWDTSI is an interrupt signal given to each processor PL, F2 from the shared watchdog timer CWDT.

FIGS. 2(a) and 2(bl) are flowcharts showing the procedure of the method of the present invention implemented in the above system configuration.

The routine shown in FIG. 2+a+ is the main routine of the monitoring routine that is activated periodically in each processor.

For example, suppose that one of the two processors PL and F2, processor Pi (PI), executes this main routine.

First, processor Pi (PI) determines its own operating state in step Sll. As a result, when determining that the processor Pi (PL) is normal, the processor Pi (PL) sets a normal code in the operation status display area Fi (Fl) of the common memory CM in step S12, and also sets the normal code in step S12.
At step 13, a reset signal -Ri (WRI) is output to reset the shared watchdog timer CWDT.

If it is determined in step Sll that the processor Pi (PL) is abnormal, the processor Pi (PL) sets an abnormality code in the operating state display area Fi (Fl) in step S14. In this case, the processor Pi (PL) does not reset the shared watched timer CWDT.

Also, if processor Pi (PL) stops,
Since it is not possible to output the reset signal WRi (WRI) for resetting the shared watchdog timer CWDT, if an abnormality occurs in the processor Pi (PL), the shared watchdog timer CWDT always resets the other processor (F2). ) is interrupted.

FIG. 2 (bl is a flowchart showing the processing procedure of an interrupt routine by the shared watchdog timer CWDT).

As mentioned above, one processor Pi (PI) is shown in FIG.
If it is found that an abnormality has occurred when the monitoring routine shown in a+ is executed, the shared watchdog timer CW is activated.
Since DT is not reset, the shared watchdog timer CWDT outputs an interrupt signal IJDTSi (CWDTSI) to the other processor (F2).

The processor (F2) to which this interrupt signal (JDTSi (CWDTSI) is applied reads the contents of the operating status display area Fi (PL) in step S15, thereby identifying the type of failure that has occurred in the processor Pi (PI). Therefore, the process can be performed in the next step S16.

Note that in the above embodiment, two processors P1. I explained a multiprocessor system with P2,
Even when there are three or more processors Pi, F2...Pn, the same number of operating status display areas F1 as the number of processors (Fl, F2...Fn) of the common memory are provided,
If the shared watchdog timer CWDT interrupts all processors except the one in which a failure has occurred, 3
It is possible to mutually monitor all the processors.

〔Effect of the invention〕

As detailed above, according to the fault detection method for a multiprocessor system of the present invention, the shared timer interrupts other processors only when an abnormality occurs in a processor, and each processor responds to the fault processing. , the software configuration becomes simple and other processors can be quickly notified of the occurrence of an abnormality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a multiprocessor system in which the method for detecting a fault in a multiprocessor system according to the present invention is implemented, and FIG. Cb) is a flowchart showing the interrupt routine, FIG. 3 is a block diagram showing the conventional system configuration, and FIG. 4 is a flowchart showing the procedure of the conventional method. Pl, F2... Processor C... Common memory CWDT... Shared watchdog timer Fl,
F2...Operating state display area In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A fault detection method for a multiprocessor system having a plurality of processors and a memory common to the plurality of processors, which includes a timer that measures a predetermined period of time, and each processor performs a self-diagnosis and, as a result, is normal. If so, it resets the timer and writes information indicating that it is normal with its own identifier attached to the common memory, and if a failure has occurred, it appends its own identifier and writes information indicating that it is normal. A failure detection process is executed to write information corresponding to the type of the failure detection process into the common memory, and the timer gives an interrupt signal to each processor other than the processor executing the failure detection process when the predetermined time elapses, and each processor A fault detection method for a multiprocessor system, characterized in that when the interrupt signal is given, processing corresponding to information attached with an identifier of a processor undergoing fault detection processing is executed.