JPS62243046A - Control system for main storage device - Google Patents

Abstract

PURPOSE:To secure an error data store RAM area, and to sufficiently inquire into the cause, by providing a means for using a RAM of a part where a mounted ROM and an address are superposed, for write exclusive use, unless there is a special control. CONSTITUTION:At the time of reading a data from RAMs 11-13 in order to inquire into the cause, a forced lead signal of 1 level is outputted through a controlling circuit 20 from a CPU 10. As a result, read to ROMs 14-16 is made ineffective in AND circuits G1D-GnD through a NOT circuit 22, a read signal to the RAMs 11-13 is made effective in the circuits G1D-GnD, and read of an error data can be executed. In such a way, an error data store RAM area can be secured without being restricted by a program ROM area. Accordingly, an error data can be stored enough, and even if the program ROM area increases, the cause can be inquired into sufficiently.

Description

[Detailed Description of the Invention] [Summary] The above j1. in an electronic computer. The tX device has a RAM configuration, and a ROM that uses the same address as this address and is equipped with a means for detecting the implementation with the CPU is installed in a part of the RAM, and a part where the address overlaps with the installed RoM is installed. By providing a means to make RAM write-only unless there is special control, the part of the main memory where ROM is mounted can also be used as a write-only area. is designed to secure an area exclusively used for δ.

[Industrial application field]

The present invention relates to an improvement in a main memory control system for a data transmission device using a microcomputer that stores error data such as a telemeter system.

In the case of data transmission equipment, intermittent failures that cannot be reproduced may occur during data transmission.

In order to investigate the cause, error data is logged in the main storage device when a failure occurs, and the cause is investigated later based on the logged data.

If you do this logging, using an external storage device will result in
Main memory is used because line data is so fast that it cannot be followed.

However, the main memory has a limited area and must have a data RAM area and a program ROM jJf area, so the remaining area will be used to store error data, but the program ROM T+H area Even if the error data storage area increases, it is desirable to be able to secure a sufficient error data storage area.

[Conventional technology]

FIG. 5 is a memory map diagram of a conventional main storage device.

In the figure, 1 is the main memory, 5 is the data RAM area, 6 is the program ROM MM area, and 7 is the error data storage RAM.
Indicates the area.

As shown in FIG. 5, the conventional method of using the main memory device 1 is to store data in the data RAM a area 5. Program ROM
The remaining part used as area 6 is used to store error data R
It was set to AM area 7.

[Problem that the invention seeks to solve]

However, in this method, the program ROM area 6
When the error data storage RAM area 7 increases, the error data storage RAM area 7 becomes narrower and may not be able to store enough error data.
In this case, there is a problem that the cause cannot be fully investigated.

[Means for solving problems]

As shown in the principle block diagram of FIG. 1, the above problem is solved by using a means for detecting the implementation by the CPU, which uses the same address as the address of a part of the RAM, and uses the same address as the address of a part of the RAM. Separately implement ROM 2 with
And the RA of the part where the address overlaps with the mounted ROM2
Method 4 to make M3 write-only without special control
This problem is solved by the main storage device control method of the present invention, which provides the following.

[Effect]

According to the present invention, for example, the main storage device 1 is
When divided into M area, program ROM area, and error data storage RAM area, the program ROM area is usually a write-only RAM area that stores error data.
M area, and this part is equipped with a separate ROM2 for the program that shares the address of this part and has a means to detect the implementation by the CPU, so the error data storage area is not related to the increase in ROM2. Naku program RO
This is the sum of the MSM area and the error data storage RAM area.

Therefore, error data can be stored sufficiently, and even if the program ROM jl area increases, the cause can be sufficiently investigated.

In other words, the area normally reserved for recessing is
This is so that it can be secured regardless of the increase in M.

〔Example〕

Fig. 2 is a memory map diagram of the main memory device according to the embodiment of the present invention, Fig. 3 is a circuit diagram of the embodiment of the present invention, 1 of 1 is the main memory, 6° is the ROM for programming, and 8 is the error code. Data storage RAM area, 10 is CPU, 11 to 13 are RAM,
14 to 16 are ROMs, 17 to 19 are mounting detection units (based on the microswitch 32), 20 is a control circuit, and 21.
22 is a knot circuit, 30 is a ROMIC, 31 is an IC socket, 32 is a microsinch, CIA-GnA, GI
C-GnC, GI D-GnD is an AND circuit, GIB
-GnD4 OR circuit; the same reference numerals indicate the same functions throughout the drawings.

Figure 2 shows an example of a data transmission device, in which the main memory 1 is entirely RAM, and includes a data RAM area 5, an error data storage RAM area 7, and a read-only program ROM 6 that shares an address. The error data storage RAM areas 8 and 7 can be used exclusively for storing error data during data transmission, so a read-only program that shares the address of this area can ROM6° for
This makes it possible to implement .

As for this implementation method, error data storage RAM el
A ROMIC (for program ROM) which allows part or all of the addresses in areas 8 and 7 to be shared and shown in FIG.
In order to be able to insert multiple 30's, multiple 4th
An IC socket 31 shown in the figure is provided.

Furthermore, inside this IC socket 31, as shown in FIG.
2 is provided.

Even if the program ROM 6' increases and more ROMICs 30 are inserted into this IC module 31, the error data storage RAM will not be available. Since there is no effect on the increase or decrease in the +i areas 7 and 8, error data can be stored sufficiently.

Of course, since the error data storage r2AM area 7 can be written to and read from, it can of course be used for other purposes.

Next, the circuit in this case will be explained according to FIG.

Figure 3 shows the error data storage RAM area 8.7 in Figure 2.
and a program ROM 6', RAM II to 13 and ROM 14 to 16 are for example two words, and RAM 1l and ROM 14 are shown.
．． RAM 12 and ROM 15° RAM 13 and ROM
16 so that they share the same address.

In addition, the mounting detecting parts 17 to 19 using the microswitches 32 in FIG.
This information is sent to the CPUIO via 0, and the CPU 10 is able to recognize the error data storage RAM 5J [area 8] shown in FIG. 2, where the address is shared.

Also, at this time, an AND circuit QnC (n is 1, 2, etc.) is set so that the mounting detection section that detects the presence of the ROM does not output data when reading to the RAM at the same address as this ROM. lock it with As a result, when data is read from CPU10, the program is read from the ROM.

A RAM at an address where no ROM is mounted can be used as a RAM because it is not locked by the AND circuit GnC.

Also, since the AND circuit QnA (n is 1, 2, . . . n) is for forced read, it is normally locked by a 0 level signal from the control circuit 20, while the AND circuit Gn
D (n is 1, 2, . . . n) is not locked because the inverted level is input by the knot circuit 22.

Now, when the read signal and address signal of Lebel are sent from the CPU10, they are read out from the ROM at the address corresponding part where the ROM is mounted via the AND circuit GnD.

Of course, it is also possible to read data from a corresponding RAM in which no ROM is mounted via the AND circuit GnC and the OR circuit GnB.

Next, when the CI'UIO sends out the write number 3 and the address signal at 0 level, it is inverted by the NOT circuit 21 and becomes a write signal of the level, and data 8 is written into the RAM at the corresponding address.

This can be written to either a compatible RAM that has a ROM installed or a RAM that does not.

Next, in order to investigate the cause, when reading data from RAMII~13, a Lebel forced read signal is output from the CPU10 via the control circuit 20. The read to RAM 16 becomes invalid, and the read signal to RAM 11 to 13 becomes valid at the AND circuit GnA (n is 1, 2, . . . n), making it possible to read the error data.

By doing so, it is possible to secure the error data storage RAM3ff area without being restricted by the program ROM area.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the part of the above-mentioned device in which the ROM is mounted can also be used as a write-only area, and an area normally used for write-only is secured regardless of the increase in ROM. For example, it is possible to secure a RAM area for storing error data without being constrained by the program ROM area, and even if the program ROM area increases, the cause can be fully investigated. be.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a memory map diagram of the main storage device of an embodiment of the invention, Fig. 3 is a circuit diagram of an embodiment of the invention, and Fig. 5 is a main memory of a conventional example. FIG. 3 is a memory map diagram of the device. In the figure, °ζ, 1.1 is the main memory, and 2 is a ROM equipped with a means to detect the implementation in the CPU.
. 3 is RAM where the address overlaps with ROM. 4 is a write-only means unless there is special control; 5 is a data RAM area; 6 is a program ROM area; 6'' is a ROM for programming; 7.8 is an error data storage RAM area; 10 is a CPU. 11 to 13 are RAM. 14 to 16 are ROMs. 17 to 19 are mounted detection units, 20 is a control circuit, 21.22 is a knot circuit, and 30 is a ROMIC. 31 is an rc socket, 32 is a microsinch, GIA~GnA, GIC~GnC, GID~GnD are AND circuits, and GIB-GnB is an OR circuit. Grass 6

Claims (1)

[Claims] The main memory (1) in an electronic computer has a RAM configuration, uses the same address as the address of a part of this RAM, and is equipped with a means for detecting implementation by the CPU.
The main feature is that an OM (2) is mounted, and a means (4) is provided for making the RAM (3) in a portion where the address overlaps with the mounted ROM (2) exclusive for writing unless there is special control. Storage device control method.