JPS62120565A - Allocation control system for main storage area - Google Patents

Abstract

PURPOSE:To attain the exchange of information between two CPU over a main memory by using a boundary register update/read control circuit to control the updating and reference of the boundary register that sets the boundary between the main storage areas to be allocated to both CPU. CONSTITUTION:The addresses of a main storage device 5 given from the allocation setting address main storage control circuits 3 and 4 of a boundary register 7 are compared with each other. Then access is given exclusively to the storage device 5 via a CPU 1 or CPU 2 if the address of the storage device 5 is set within a set address. The set contents of the register 7 are referred to or updated via a boundary register update/read control circuit 6 that works in response to the CPU 1 or CPU 2. Thus the main storage area can be enlarged or reduced dynamically. In such a way, information can be transferred between both CPU over the main storage area.

Description

Detailed Description of the Invention "Field of Industrial Application" This invention is applicable to a duplex system in which two central processing units operate independently under two operating systems. This relates to a method of allocating an area of main memory for exclusive use to each central processing unit.

``Prior Art'' Conventionally, the allocation of main storage areas to each central processing unit in a duplex system has been determined by manual switch settings when installing hardware or during system initialization.

``Problems to be Solved by the Invention'' The conventional main storage area allocation method described above is fixed during system operation, so even if one central processing unit becomes inoperable due to a failure, it will not function normally. The main storage area assigned to the failed central processing unit cannot be automatically accessed from a central processing unit that has failed, and failure information cannot be carried over to the main memory.

Further, even when both central processing units are operating normally, there are cases where it is necessary to exchange information between the two central processing units. In this case as well, it is impossible to exchange information on the main memory using the conventional method, and for this purpose it is necessary to provide other means such as a magnetic disk file or a communication line.

``Means for Solving the Problems'' This invention causes a boundary register to hold the boundaries of the main storage area available to each central processing unit, and stores the main storage address requested by the central processing unit and the main storage area. The address check circuit compares the boundary address held by the boundary register and determines whether it is within the area allocated to the central processing unit. Access to the main memory is controlled based on the determination result, and the area If the access operation is outside the range, the access operation is prohibited, and this fact is reported to the main memory access control circuit of the central processing unit, and the boundary register is updated.
The reference is configured to be controlled by a boundary register update/read control circuit.

"Example" Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Central processing units 1 and 2 operate independently using areas allocated to each of main memory devices 5 through main memory access control circuits 3 and 4, respectively.

The central processing unit 1 uses the access path 11, and the central processing unit 2 uses the access path 12 to send a main memory address to be accessed and issue a data write/read request to the main memory.

The main memory access control circuits 3 and 4 send the main memory addresses received from the central processing units 1 and 2 to the address check circuit 8, which checks whether the address is within the area allocated to the central processing unit. If the address is within the area, the normal access operation to the main memory device 5 is performed, and if it is outside the area, the access operation to the main memory device 5 is not performed, and the address is recognized as being outside the area. Report to central processing unit.

Among the addresses (OL address to m address) of the main storage device 5, the address that is the boundary of the area allocated to the central processing units 1 and 2 is held in the boundary register 7, and this held value is
It can be updated and referenced from the central processing units 1 and 2 via the boundary register update/read control circuit 6.

The address currently held in the boundary register 7 is moved to the top 111. The address check circuit 8 is connected to this boundary register 7.
11 held by the central processing unit 1 or 2 is compared with the main memory address sent from the central processing unit 1 or 2 via the main memory access control circuit 3 or 4. If the address sent from central processing unit 1 is address a and the address sent from central processing unit 2 is address b, then 01. If ≦a≦11, it is determined that it is within the area; otherwise, it is determined that it is outside the area, and the determination result is returned to the main memory access control circuit 3. For the central processing unit 2, if 11<b≦m, it is determined that it is within the area, otherwise it is determined that it is outside the area, and the determination result is returned to the main memory access control circuit 4. That is, as the upper boundary of No. 111, areas below this are allocated to the central processing unit 1, and areas with addresses larger than that are allocated to the central processing unit 2, thereby preventing mutual interference.

In such a configuration, when transferring information from the central processing unit 1 to the central processing unit 2, the central processing unit 1 writes the information to be transferred from address 12+1 (lz+1 (At) to the top 111 of the main memory, and then The central processing unit 1 updates the content of the boundary register 7 to 12 via the boundary register update/read control circuit 6. As a result, the central processing unit 2 also updates the uppermost area of the main memory 5 from addresses 12+1 to 111. It can be accessed as an area.

Furthermore, when the central processing unit 1 becomes inoperable due to a failure or the like, the central processing unit 2 writes O to the boundary register 7 via the boundary register update/read control circuit 6. It becomes possible to access the area of the main storage device 5 that was allocated to 1 as its own area. As a result, the central processing unit 2 can also read the information left in the main storage device 5, and the state immediately before the central processing unit 1 became inoperable can be analyzed, and subsequent recovery processing becomes easier.

As can be seen from the above description, when information is transferred from the central processing unit 2 to the central processing unit 1, the same processing can be performed even when the central processing unit 2 falls into an inoperable state.

"Effects of the Invention" As explained above, a boundary register is provided to set the boundary of the main memory area allocated to two central processing units, and the contents of this boundary register can be referenced and accessed at any time by both central processing units. By making it possible to update, the main memory area allocated to each central processing unit can be dynamically expanded/reduced (Jν), and this allows the exchange of information between two central processing units on the main memory. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1.2: Central processing unit, 3, 4: Main memory access control circuit, 5: Main memory device, 6: Boundary register update/read control circuit, 7: Boundary register, 8 Nearest search circuit, 11, 12 + central processing Access route from the device to main storage.

Claims (1)

[Claims] (1) In a duplex system in which two central processing units operate independently under two operating systems, each using the main storage area exclusively, each of the central processing units mentioned above can be used. A boundary register that holds the address that is the boundary of the storage area of the main memory device, and a main memory address that has received an access request from each central processing unit, are compared with the boundary address of the boundary register, and the central processing unit An address check circuit determines whether or not it is within the allocated area, and based on the determination result, if it is within the area, it controls access to the main memory, and if it is outside the area, it controls the access operation. and a main memory access control circuit that prohibits and reports this to the central processing unit, and a boundary register update/reference control circuit that updates/references the boundary address of the boundary register from each of the central processing units. Features a main storage area allocation control method.