JPH1021143A - Memory interface device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely hold the security of contents which are stored it an external storage device in a memory interface device for connecting a data processor to the external storage device. SOLUTION: The device is provided with a first connecting means 11 for connecting the signal input/output lines D0-D3 of the data processor to the signal input/output lines d0-d3 of the external storage device by prescribed correspondence relation, the second connecting means 12 for connecting the signal input/output lines D0-D3 with the signal input/output lines d0-d3 by correspondence relation being different from the prescribed one and connection change-over means 13 and 14 selecting one of them so as to change-over connection between the data processor and the external storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory interface device for connecting a data processing device for processing data and an external storage device for storing data.

[0002]

2. Description of the Related Art A memory interface device is used to transmit and receive data between a data processing device such as a personal computer and an external storage device such as a PC card or a disk device. The input / output lines are connected to each other. Conventionally, in a memory interface device, signal input / output lines of a data processing device and signal input / output lines of an external storage device are connected according to a predetermined correspondence relationship.

For example, as shown in FIG. 5, four (4-bit) data lines D0 to D3 included in a data processing device are provided.
Four (4 bit) data lines d0 of the external storage device
To d3, in the memory interface device, the data line D0 and the data line d0, the data line D1 and the data line d1, and the data line D2 and the data line D2 so that the signal attributes of these data lines match each other. d2, data line D
3 and the data line d3.

[0004]

By the way, in the above-mentioned memory interface device, the data processing device and the external storage device are connected so that their signal attributes match each other, so that the data processing device and the external storage device are connected. If the signal attribute between the two is known, the stored contents can be read from the external storage device. In other words, if the signal attribute of the data processing device matches the signal attribute of the external storage device, the storage contents in the external storage device are easily analyzed, and security for data in the external storage device is reduced. You will not be able to keep it.

Accordingly, an object of the present invention is to provide a memory interface device capable of maintaining the security of contents stored in an external storage device.

[0006]

SUMMARY OF THE INVENTION The present invention is a memory interface device devised to achieve the above object,
In order to transmit and receive the data between a data processing device that processes data and an external storage device that stores the data, a plurality of signal input / output lines included in the data processing device and a plurality of input / output lines included in the external storage device And a first connection means for connecting the signal input / output line of the data processing device and the signal input / output line of the external storage device in a predetermined correspondence relationship. A second connection unit for connecting a signal input / output line of the data processing device and a signal input / output line of the external storage device with a correspondence different from the predetermined correspondence; and the first connection means. The second
Connection switching means for switching the connection between the data processing device and the external storage device by selecting one of the connection means.

[0007] According to the memory interface device having the above configuration, the connection switching means selects one of the first connection means and the second connection means. Connection switching means is the first
Is selected, the signal input / output lines are connected in a predetermined correspondence relationship between the data processing device and the external storage device. When the connection switching unit selects the second connection unit, the signal input / output lines are connected between the data processing device and the external storage device in a correspondence different from a predetermined correspondence. Therefore, the stored contents written in the external storage device when the second connection unit is selected cannot be correctly read out without passing through the second connection unit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory interface device according to the present invention will be described with reference to the drawings. However, here, a description will be given of an example of a memory interface device that connects the 4-bit data lines D0 to D3 included in the data processing device and the 4-bit data lines d0 to d3 included in the external storage device.

[First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of a memory interface device according to the present invention. In this embodiment, the data processing device is a personal computer, and the external storage device is a JEIDA (Japan Electronic Industry).
y Development Association; Japan Electronics Industry Promotion Association) /
PCMCIA (personal computer memory card intern)
It consists of a PC card with a built-in memory compliant with the International Association (Personal Computer Memory Card International Association) standard. Therefore, in the data processing device, P
It has a card slot for inserting a C card, and outputs a REG (register) signal as a control signal for accessing an attribute information storage area (attribute memory) provided in the PC card. ing.

The memory interface device 10 of the present embodiment is provided inside a data processing device, and is connected to data lines D0 to D3 on the data processing device side and an external storage device side (PC via a card slot). Connect with card)
Are connected to the data lines d0 to d3, respectively. However, the memory interface device 10 may be provided separately from the data processing device and the external storage device. This memory interface device 1
0 includes a first bidirectional buffer (hereinafter abbreviated as a first buffer) 11, a second bidirectional buffer (hereinafter abbreviated as a second buffer) 12, and an inverter 13.

First buffer 11 and second buffer 12
Has terminals 1A, 2A, 1B, and 2B, respectively, and outputs a signal input to the terminal 1A to the terminal 1B and outputs a signal input to the terminal 2A to the terminal 2B. . The same applies to the case where the input and output are reversed between the terminals 1A and 2A and the terminals 1B and 2B.

In such a first buffer 11 and a second buffer 12, the terminal 1A of the first buffer 11 and the second
The data line D3 is connected to the terminal 2A of the buffer 12, and the data line D1 is connected to the terminal 2A of the first buffer 11 and the terminal 1A of the second buffer 12. The data line d3 is connected to the terminal 1B of the first buffer 11 and the terminal 1B of the second buffer 12, and the data line d1 is connected to the terminal 2B of the first buffer 11 and the terminal 2B of the second buffer 12. Is connected. The data line D
0 and the data line D2 are respectively connected to the data line d0 and the data line d without passing through the first buffer 11 or the second buffer 12.
2 is connected directly.

Further, the first buffer 11 and the second buffer 12 each have a G terminal, and a REG signal from a data processing device is input as a conversion / non-conversion switching signal 14. . However, the REG signal is input to the G terminal of the second buffer 12 via the inverter 13. The inverter 13 outputs, for example, a negative (NO
T) circuit, and the input signal is “HIGH”
, The output signal is set to “LOW”, and when the input signal is “LOW”, the output signal is set to “HIGH”.

Next, an operation example of the memory interface device 10 configured as described above will be described. J
In an attribute memory in a PC card conforming to the EIDA / PCMCIA standard, various information on the PC card is written in a predetermined format. Therefore, when accessing the attribute memory in the PC card, the data processing device sends the RE
A G signal is output. The REG signal is a signal that becomes “LOW” when accessing the attribute memory and becomes “HIGH” when accessing another shared memory area.

The REG signal is generated by the G signal of the first buffer 11.
It is also input to the terminal and the inverter 13. At this time, R terminal is connected to the G terminal of the second buffer 12 through the inverter 13.
An EG signal is input. Therefore, G of the first buffer 11
The input to the terminal and the input to the G terminal of the second buffer 12 are contrary to each other. That is, when the REG signal is “LO
In the case of "W", the signal output of the first buffer 11 becomes valid, and the signal output of the second buffer 12 becomes invalid. Also,
When the REG signal is “HIGH”, the signal output of the first buffer 11 becomes invalid, and the signal output of the second buffer 12 becomes valid.

When the signal output of the first buffer 11 becomes valid, the data line D3 is connected to the terminal 1A of the first buffer 11,
Since the data line d3 is connected to the terminal 1B, the data line D3 and the data line d3 are connected as a result. Similarly, when the signal output of the first buffer 11 becomes valid, the data line D1 is connected to the data line d1. On the other hand, the second buffer 12
Becomes valid, the terminal 1 of the second buffer 12
Since the data line D1 is connected to A and the data line d3 is connected to the terminal 1B, the data line D1 is connected to the data line d3 as a result. Similarly,
When the signal output of the second buffer 12 becomes valid, the data line D3 is connected to the data line d1.

Therefore, in the memory interface device 10, when the REG signal is "LOW", the signal output of the first buffer 11 becomes valid, and the data lines D0 to D3 of the data processing device and the data lines of the external storage device are output. d0-d
3 are connected in accordance with a relationship in which the signal attributes of the data lines match each other, that is, a predetermined correspondence relationship. When the REG signal is “HIGH”, the signal output of the second buffer 12 is enabled, and the data lines D0 to D3 of the data processing device and the data lines d0 to d3 of the external storage device are set in a predetermined correspondence relationship. Are connected with each other in a different correspondence relationship, that is, a correspondence relationship in which data conversion is performed.

That is, the memory interface device 1
At 0, the REG signal from the data processing device functions as the conversion / non-conversion switching control signal 14 for switching the connection between the data lines D0 to D3 and the data lines d0 to d3.
Depending on whether the REG signal is “LOW” or “HIGH”, as shown in FIG. 2, the data lines D0 to D3
Is different from data input / output through the data lines d0 to d3.

Therefore, when the REG signal from the data processing device is “LOW”, the content of the data written in the external storage device is as follows when the REG signal is “LOW”.
That is, the data lines D0 to D3
Unless it is connected to the data lines d0 to d3, the data cannot be read correctly. When the REG signal from the data processing device is “HIGH”, the content of the data written in the external storage device is determined when the REG signal is “HIGH”, that is, the data line D0 through the second buffer 12. Unless the data lines d0 to d3 are connected to the data lines d0 to d3, the data cannot be read correctly.

As described above, the memory interface device 10 according to the present embodiment connects the data processing device and the external storage device via one of the first buffer 11 and the second buffer 12. With the first buffer 1
1 is a predetermined correspondence between them according to the signal attribute,
Further, the second buffer 12 is connected to each other in a correspondence relationship in which data conversion is performed.
Therefore, if data is written through the second buffer 12, even if the signal attribute between the data processing device and the external storage device is known, the content of the data in the external storage device is required without passing through the second buffer 12. Since the data cannot be read correctly, the content is not analyzed, and as a result, the security of the data content can be maintained.

Furthermore, in the memory interface device 10 of the present embodiment, since the REG signal is used as the conversion / non-conversion switching control signal 14, data access is not performed when accessing the attribute memory, and other shared memories are accessed. Sometimes data conversion is performed. As a result, the attribute information of the external storage device can be read and written as usual, so that the attribute of the external storage device can be easily recognized, and the security of the data in the shared memory is ensured. Also, since the data in the attribute memory is read out normally,
There is no analysis of the data conversion mechanism based on information about the attribute memory that is publicly disclosed.

In this embodiment, the external storage device is a PC with a built-in memory conforming to the JEIDA / PCMCIA standard.
Although the case of a card has been described, the present invention is not limited to this, and any other storage device can be used as long as it has a similar unique control signal such as a REG signal. is there.

[Second Embodiment] Next, a second embodiment of the memory interface device according to the present invention will be described. However, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted. FIG. 3 is a block diagram of a schematic configuration of the memory interface device 20 according to the second embodiment.

The memory interface device 20 uses the register 2 instead of the REG signal as the conversion / non-conversion switching signal 21 for switching the connection between the data lines D0 to D3 of the data processing device and the data lines d0 to d3 of the external storage device.
2 is used. Register 22
Is provided in the data processing device, and outputs an output signal whose output state changes according to a condition preset in the data processing device to the G terminal of the first buffer 11 and the inverter 13 It is. Specifically, the register 22 outputs the output signal to “LO” in accordance with processing of a predetermined program (software) in the data processing device.
"W" or "HIGH".

In the memory interface device 20 configured as described above, for example, when a specific ID code is designated by the data processing device, the output state of the output signal from the register 22 changes, and the data lines D0 to D3 are connected. The connection with the data lines d0 to d3 is switched. Then, data is exchanged between the data processing device and the external storage device as in the case of the above-described first embodiment.

As described above, in the memory interface device 20 of the present embodiment, since the output signal of the register 22 set by software is used as the conversion / non-conversion switching control signal 21, the operator of the data processing device or the program When desired, data conversion is performed. As a result, even if an attempt is made to read the contents of the data in the external storage device via the memory interface device 20, the contents of the data cannot be correctly read without knowing the software settings, and security can be ensured. It will be even more secure.

[Third Embodiment] Next, a third embodiment of the memory interface device according to the present invention will be described. However, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted. FIG. 4 is a block diagram of a schematic configuration of the memory interface device 30 according to the third embodiment.

The memory interface device 30 uses not a REG signal but a comparator as a conversion / non-conversion switching control signal 31 for switching the connection between the data lines D0 to D3 of the data processing device and the data lines d0 to d3 of the external storage device. In this case, an output signal from the C.32 is used.

The comparator 32 is composed of, for example, a comparison circuit. The comparator 32 compares an address signal specified by the data processing device with a preset address signal, and outputs an output signal "LOW" only when they match. If they do not match, the output signal is set to “HIGH”. Then, the comparator 32 outputs the output signal to the G terminal of the first buffer 11 and the inverter 13. Note that the comparator 32
It may be provided in the data processing device, or may be provided in the memory interface device 30.

In the memory interface device 30 configured as described above, when the same address signal as the preset address signal is designated, that is, only when an attempt is made to access a specific address in the external storage device, The connection between the data lines D0 to D3 and the data lines d0 to d3 is switched so as not to perform data conversion. Then, data is exchanged between the data processing device and the external storage device as in the case of the above-described first embodiment.

As described above, in the memory interface device 30 of the present embodiment, since the output signal of the comparator 32 for comparing the address signal is used as the conversion / non-conversion switching control signal 32, the memory interface device 30 responds to the address in the external storage device. Data conversion. With this, if data is written into the external storage device via the memory interface device 30, even if the signal attribute between the data processing device and the external storage device is known, depending on the address in the external storage device, it can be correctly written. Since the data cannot be read, the security of the data content can be maintained. Further, even if the published data is written to a specific address in the external storage device, the data conversion mechanism is not analyzed based on the published data.

In the second and third embodiments, R
Since a similar unique control signal such as the EG signal is not required, the external storage device may be other than the PC card,
For example, it may be an IC card, a RAM (Random Access Memory) disk, a hard disk device, a floppy disk device, a magneto-optical disk (MO) device, or the like.

In the first, second, and third embodiments, of the 4-bit data lines D0 to D3 and the 4-bit data lines d0 to d3, the data lines D1, D3 and the data lines d1, Although the description has been given of the case where the two bits d3 are exchanged, the present invention is not limited to this. For example, the number of bits to be exchanged is not limited, and any bits may be exchanged. Further, address lines may be replaced instead of data lines as long as the lines are used to input and output signals between the data processing device and the external storage device.

[0034]

As described above, the memory interface device of the present invention comprises: a first connection means for connecting a data processing device and an external storage device in a predetermined correspondence; The connection is made by either one of the second connection means connecting in a correspondence different from the relation. Therefore, if data is written while connected via the second connection means, even if the predetermined correspondence is known, the contents of the data in the external storage device must be passed through the second connection means. Since the data cannot be read correctly, the content is not analyzed, and as a result, the security of the data content can be maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a schematic configuration of a memory interface device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a specific example of data conversion of data transmitted and received via a memory interface device according to the present invention.

FIG. 3 is a block diagram of a schematic configuration of a second embodiment of the memory interface device according to the present invention.

FIG. 4 is a block diagram of a schematic configuration of a third embodiment of the memory interface device according to the present invention.

FIG. 5 is an explanatory diagram showing connection of data lines in a conventional memory interface device.

[Explanation of symbols]

10, 20, 30 Memory interface device 11 First bidirectional buffer 12 Second bidirectional buffer 13 Inverter D0, D1, D2, D3, d0, d1, d2, d3 Data line

Claims (4)

[Claims] A plurality of signal input / output lines included in the data processing device and a plurality of signal input / output lines included in the data processing device for transmitting and receiving the data between a data processing device that processes data and an external storage device that stores the data. A memory interface device for connecting a plurality of signal input / output lines included in a storage device, wherein a signal input / output line of the data processing device and a signal input / output line of the external storage device are connected in a predetermined correspondence relationship. First connection means, second connection means for connecting a signal input / output line of the data processing device and a signal input / output line of the external storage device with a correspondence different from the predetermined correspondence, Connection switching means for switching the connection between the data processing device and the external storage device by selecting one of the connection means and the second connection means. Characteristic memory interface device. 2. The connection switching unit according to claim 1, wherein said first connection unit and said second connection unit are based on a control signal output from said data processing device to access an attribute information storage area of said external storage device. 2. The memory interface device according to claim 1, wherein said memory interface device selects one of said connection means. 3. The first connection unit is connected to the first connection unit based on an output signal output from the data processing device and having an output state changed according to a condition preset in the data processing device. 2. The memory interface device according to claim 1, wherein the selection is made with the second connection unit. 4. The first connection unit and the second connection unit based on a result of comparing an address signal output from the data processing device with a preset address signal. 2. The memory interface device according to claim 1, wherein the memory interface device selects one of the following.