JPS62242417A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase driving current and to shorten delay time by connecting a normally ON FET to the output stage source follower side of a circuit for forming plural clock signals for timing signals and connecting a normally OFF FET to the pull-down side. CONSTITUTION:A timing signal generating circuit 51 is constituted of synchroniz ing octonary counters 302a-302c consisting of three master/ slave flip-flops and outputs six timing signals for one clock input. The timing signals are input ted to an 8:1 multiplexer 52 as state signals and light input data I0-I7 are sequentially outputted so that parallel input data are converted into serial data and outputted. In the master/ slave type FF circuit, a push-pull circuit 115 is connected to the output stage so that the normally ON FET is used for the source follower side 113 and the normally OFF FET is used for the pull- down side 114, and the outputs 111, 112 of the FF are connected to the input of the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit that handles clock signals and timing signals.

(Prior art) Integrated circuits (ICs) using Schottky gate field effect transistors (M) iSFgT) can consume less power and operate at higher speeds than those using conventional Si. It is attracting attention because of this.

In particular, due to its high speed, it can be used as an integrated circuit that handles high-speed data such as a high-speed data shift register, data multiplexer, etc. Generally, the circuit that waits for the above-mentioned functions is composed of parts that handle high-speed data such as flip-flops, latches, and multiplexers, and timing signal forming circuits such as counters that determine the operation timings of these parts. In addition, the operation timing has been adjusted to take full advantage of high speed.

Design the circuit to interact with the clock signal.

In this case, the timing signal generated by the timing signal generation section is distributed to m units that handle high-speed data, such as shift registers, latches, and multiplexers, so the wiring capacitance and fan-out capacitance connected to the timing signal output are extremely large. Become.

Logic circuits using GaAsMBSFET include normally-on logic and normally-off logic. Among these, 1) CF L (Direct Coupled F') is a representative of normally off logic.
The circuit configuration of ET Logic is shown in Figure @2. In this circuit, depletion FgT21. An enhancement FET 22 is used as a driver. The figure shows an example of a two-man power NOR circuit equipped with two driver FETs. As described above, DCFL is considered to be the best circuit to be used for high integration because it has the most single circuit configuration among GaAs logic circuits and has the lowest power consumption per gate. However, DCBL has a smaller current capacity than other logics, and has a smaller ability to drive capacitive loads due to wiring fan-out and the like. In other words, the rate of increase in delay time due to load is large. Therefore, when distributing various output pulses to a large number of circuits, such as the timing signal generation circuit in the data multiplexer and shift register mentioned above, the number of fan-outs and wiring lengths become long.
Delays caused by these capacitive loads become a problem.

Conventionally, a method has been used to drive these loads by connecting a buffer circuit with a large current driving capacity to such an abutment output stage.

As an example, a flip-flop circuit provided with a buffer circuit will be considered with reference to FIG.

Figure 3 is 1/25 of the clock), 1/4 frequency division, 178
This is a circuit that generates a frequency division timing signal. As shown in the figure, the output 30 of the normal timing signal generation circuit
1a, 301b, 3nlc, 30yud*301e.

301f is output from flip-flops 302a, 302b, and 302c due to the need to synchronize with the clock.

FIG. 4 is a diagram illustrating one of these flip-flops in more detail, and is a conventionally known circuit for further increasing the drive capability of the output section of the flip-flop. 8 N0R1?51% 401゜402.40
Master-slave type flip-flop consisting of 3,404,405,406,407,408, 1tlQ
.

During Q, buffer circuit 4.1las411b, 412
cw412b is provided.

409 is the master tone, and 410 is the slave tone.

The NOR circuit has a CFLII configuration as shown in FIG. 2, using a depressimine type F'g'l'' as a load and a secondment type FET as a driver.

For the outputs Q and Q of the slave side flip-flop.

Sum of load due to fan-out and wiring load CL (413)
exists. The buffer circuit is composed of two stages of inverters, and the gate width of the FgT constituting the inverter of the inverter 412as412b is selected to a value necessary to sufficiently drive CL (413).

The relationship between the FgT gate width and the delay time will be explained below using a formula. The delay time per inverter stage due to the load CL can be represented by the following equation as a charging time.

Dss CL: Load Δv: i Amplitude ID5s: Saturation 'i flowing to inverter load Ft2T
t style or ID5s is IDs 5saKo @ Wjl M (V# S -
VTR)!・−・−・−・(2) Ko: 1 voltage per 1 μm of gate width wp: Gate 16 of load FIT V#s: Voltage between gate and source of load FET VTR: Threshold voltage of load FET .

In the DCFL inverter, the gate and source of the load FET are shorted (see Figure 2), so V
Ils is Vlils sa □ ・・・・・・・・・・・・
・・・・・・・・・・・・・・・ (3), and (2) is ID5s KO Wf-VTax ・・・・・・・・・
It is expressed as ・・・・・・・・・・・・ 14). K
Among the three factors of o * W 9 t V T H, Ko is a single factor determined by the device structure.
Since VTH4 is limited by the condition of increasing the noise margin of the inverter, the only way to increase the ID5s and reduce the delay time is to increase the WII.

Therefore, Kamokura, who created timing signals with wiring trenches and large fan-out capacitances, made the gate width of the inverter of the buffer circuit large by non-[C] to enable high-speed operation. Problem to be solved) In integrated circuits that handle general VC high-speed data, wiring capacity 1
1 *When creating a timing signal with a large fan-out capacity, an inverter with a large gate width and large drive capacity is installed as a buffer circuit in the output stage, but this increases the size by one dimension, so high integration is required. That was the problem.

[Structure of the invention]

(Means for Solving the Problems) The present invention uses a normally-on type FET on the output stage source follower side of a circuit forming a frequency clock or a timing signal, and a normally-off type PET for the pull-down. It is characterized by a push-pull circuit.

(According to the present invention, the source follower Fg of the push-pull circuit
ToVgs is the load F of the inverter circuit using the conventional method VC.
Because it is larger than ET's VJFs (-0+v).

The drive current is large, and the delay time for the load can be greatly reduced.

(Embodiment) Figure 5 is a block diagram of a parallel-to-serial conversion circuit according to an embodiment of the present invention.
As shown in the figure, synchronous type 8 consists of three master-slave type flip-flops of 302at302bs302C.
In the digit counter, S, lji, Sl,
6 timing τ signals are output. This timing bias is applied to the 8:l multiplexer 52.
The input data I for the 8 sugar fruits, which is input as number a, is
The I-ma is sequentially outputted and the data input in parallel is converted into a missing series and output.

The 8:l multiplexer is a 4-manpower NOR circuit (601 to 608) 811a and 8-manpower NOR circuit as shown in Figure 146.
Consists of one OR circuit (609). Therefore, the output section of the timing signal generation circuit 51 needs to equally drive the four four-way NOR circuits in the multiplexer section, but since the number of fan-outs is 4 and the wiring length is long,
The master-slave type flip-flop circuit is %@1 figure [
A push-pull circuit (115
) was established.

This push-pull circuit has a source follower jllll(1
13) Pull down the 7-mullion type FIT l111 (
114), a normally-off type FfiiT is used, and the output (xlx*o2) & of the flip-flop is connected to the input.

In Figure 1(b).

In order to explain the lack of operation of the push-pull circuit, the portion A in FIG. 1a) is shown enlarged.

High No. 1 for output (Ill), output (l12) ic
Low! Let us consider the DC-like level of 1 go where @ appears. The low level (VL) of the NOR circuit at the previous stage appears in the output (111), 'lt source (118), and CvDDwtts power (112). pull down FRT
(114) is in the OFF state, so the output (116)
[C, High L/to/L/ (Vit) appears, and since VH is input to the gate of the primary stage DCFL circuit, it is cranked to the Schottky voltage φB of the gate.

Therefore, the gate-source voltage VIIS of the source follower F B T (113) is.

VHs −VDD−φB =−・Song−−−−−−
--15). At this time, using the above-mentioned (1) l21 formula, the following conditions that are commonly used are set and calculations are performed.

Setting conditions are VDD -1,5V ・・・・・・・・・・・・・・・
・・・・・・・・・(6) VH-φB = Q, 7V
・・・・・・・・・・・・・・・・・・・・・(7
)7-x 7 o 7 FET OVTH--0
, 6V −+8).

(5) , +6) , +7) j tJ, Vgs-
VDD-)g-1,5-0,7=0.8V...
・・・・・・・・・ 19) r8) , (9) to (2
) When substituted into Eq.

I d 51zKo * Wl @ (Vg 5-VT
R)”=Ko-WII・(0,8-(-0°6))!-
1.96Ko・wg・・・・・・・・・・・・・・・
...Song From (1o), △t is CL-△V CL-ΔV Yul, m - m□Song... (11)"S
*1.96Ko-Wl.

On the other hand, if the delay time due to CL in a conventional inverter circuit is found using the same Token equation, Ids, mK is obtained from equation (4).
o-WJf, VTH” TomiKo*WjF・(-0,6)Tomi=0.36 Ko @wg+m++++++++++
(12) Therefore, △[ is obtained from equation 111.

Taking the ratio of the delay time △t0 when using the push-pull circuit to the delay time △1° when there is an open phase in the inverter circuit, we get (11) - (13) 0), and CL@Δ■ 036Ko・Wfi. Delay time is small.

That is, vIIS of the source follower FgT of the push-pull circuit is different from the inverter circuit O load F according to the conventional method.
E T (D Vl 5(-0V)j, ?) 4b is large and the Sa flow is large, so the delay time with respect to the load is small.

Conversely, when compared with the same delay time, the gate width can be made smaller by the amount of current, which is advantageous in terms of higher integration.

A prototype parallel conversion circuit was fabricated using push-pull 11 circuits as the buffer of the above flip-flop.

It was confirmed that the lock cycle mantissa was 1.9 GHz''?? It was confirmed that it worked.For comparison, we prototyped a parallel-to-serial conversion circuit using an inverter circuit as a buffer as shown in Figure 4. However, its performance is limited to the operating frequency 7QQM
It was Hz. This difference can be considered to be due to the difference in delay time of the timing signal generation circuit.

The present invention can be applied to a synchronous group high-speed logic circuit in which synchronization signal simultaneity and high speed are strongly required, such as the synchronous GaAs logic collection circuit shown in the above embodiment. Although it is effective, it goes without saying that its effectiveness is not limited to GaAs integrated circuits. In addition, FETs generally have a smaller driving capacity than bipolar transistors, which have a larger driving capacity.
It works effectively when applied to circuits using V.

〔Effect of the invention〕

According to the present invention, it is possible to obtain the effect that the %m dynamic current is large and the delay time for the load can be reduced.

[Brief explanation of drawings]

Figure 1 is a diagram of a circuit in which a push-inable circuit is provided at the output stage of a master-slave type flip-flop circuit according to an embodiment of the present invention.
FIG. 3 is a diagram showing a timing signal generation circuit, FIG. 4 is a diagram showing an example in which an inverter circuit is provided at the output stage of a master-slave type flip-flop circuit, and FIG. FIG. 6 is a diagram showing an 8:l multiplexer circuit, which is a diagram showing a parallel-to-serial conversion circuit according to an embodiment of the present invention. 51...timing occurrence +? 1ilvPr, 52
-8: l multiplexer, 302a, 302b-
302c -- Synchronous octal counter, 401402t
・408...NOR circuit. 601-608... 4-man power NO method circuit. Agent Patent Attorney Ken Nori Chika Udo Kikuo Takehana

Claims (3)

[Claims] (1) It consists of a part that forms a plurality of clock signals or timing signals, and a part that operates in response to the supply of these signals, and the plurality of clock signals or timing signals each generate a signal that is complementary to them. In a semiconductor integrated circuit having a semiconductor integrated circuit, the plurality of clock signals or timing signals and signals complementary thereto are supplied through a push-pull circuit to a part that operates in response to supply of these signals. Features of semiconductor integrated circuits. (2) The semiconductor integrated circuit according to claim 1, wherein in the push-pull circuit, a normally-on type FET is used on the source follower side, and a normally-off type FET is used on the pull-down side. (3) Claims 1 and 2, characterized in that the field effect transistor is made of gallium arsenide.
Semiconductor integrated circuit described in Section 1.