JPH0621777A - Field effect transistor logic circuit - Google Patents

Abstract

PURPOSE:To facilitate the timing design while keeping the high speed performance and also to reduce th power consumption of an LSI by limiting the load driving ability of an inverter included in a feedback circuit which constructs a latch circuit. CONSTITUTION:When a clock signal phi of a high level is inputted to a clock input terminal 13, the data D applied to a data input terminal 11 is transmitted to an output terminal 42 via an inverter 21. Then the data D is positively fed back by a feedback inverter 22 and held. Under such condition, a clock input signal phi is kept at a low level and therefore the input data are not transmitted to a slave latch 3 of the next stage. When the signal phi is set at a high level, the output of a master latch 2 of the first stage is written into the latch 3. Meanwhile the signal phi is kept at a low level and therefore the latch 2 holds the hitherto data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor logic circuit, and more particularly to a field effect transistor logic circuit forming a D-type flip-flop that operates in synchronization with a clock signal.

[0002]

2. Description of the Related Art As a typical example of a conventional D-type flip-flop used in a logic LSI, FIG.
A circuit using T is shown. This circuit has a configuration using a master latch and a slave latch each including two inverters and two transfer gates. This circuit has a feature that it has a simple structure and operates at high speed. In FIG. 3, 27, 28, 37 and 38 are transfer gates, and 21, 22, 31, and 32 are inverters. Each transfer gate is a p-type M
The OSFET and the n-type MOSFET are connected in parallel, and the signal level is designed so that "threshold drop" does not occur. Current MOSFET threshold voltage is usually 1V
As described above, this method is important for ensuring the amplitude of the data signal.

In this circuit, the input data D is taken into the master latch 2 when the clock signal φ of the transfer gate 27 is at low level, and is retained when it is at high level. The slave latch 3 has a transfer gate 37.
Of the clock reverse-phase signal ▽ φ (▽ is a substitute for the upper bar, which means inversion. The same applies below), the master latch 2
The data of is captured and held at the high level. Therefore, the input data D is synchronized with the clock signal,
The output will be delayed by one clock. The transfer gates 28 and 38 are provided in the master and slave latches so that the input data and the held data do not conflict with each other.
A clock signal having a phase opposite to that of 7, 37 is input.

In the D-type flip-flop described above, C
Although the configuration using the MOSFET has been described, a circuit similar to the circuit shown in FIG. 3 can be configured with a junction gate type FET using gallium arsenide (GaAs) crystal.

Since the GaAs crystal has electron mobility several times faster than the Si crystal and a semi-insulating substrate can be easily obtained, the parasitic capacitance of the circuit can be reduced at the time of integration, and the high speed is achieved. Energetic research and development have been carried out in various places because of the idea that logical operation is possible. Although there are various basic circuit types using GaAs semiconductor elements, DCFL (Direct) using enhancement type FET (MESFET) is used.
The t CoupledFET Logic) circuit is simple in configuration, suitable for integration, and is excellent in that it does not require a high power supply voltage. A gate array with 100K gate scale integration, which is a basic circuit, is also commercially available. Has reached the end. This DCFL circuit is an NM of Si semiconductor element.
A logic circuit corresponding to an OS circuit and developed with a Si semiconductor element is also applied to the design of an LSI using a GaAs semiconductor element. In the case of a DCFL circuit using a GaAs semiconductor element, the threshold of the FET can be easily set to 0V by controlling the thickness of the epitaxial crystal layer and the impurity concentration of the ion implantation layer.
Since it can be set in the vicinity, unlike the case where the CMOSFET is used, the transfer gate can be composed of the FET1 element.

In recent years, due to improvement in semiconductor manufacturing technology,
Since a MOSFET with a threshold voltage of 1 V or less can be obtained, even in a D-type flip-flop using a CMOSFET, the "threshold drop" in the transfer gate can be suppressed to a minimum and the operating conditions of the circuit must be met. Alternatively, the transfer gate may be composed of only one NMOSFET element.

[0007]

Problem to be Solved by the Invention CMO shown in FIG.
In the D-type flip-flop having the S configuration, when the positive-phase and negative-phase clock signals φ and ▽ φ are both at the high level or at the low level, a malfunction occurs due to the competition between the data of the master latch 2 and the data of the slave latch 3. cause.
For example, when the equivalent resistance of the transfer gate when turned on is approximately regarded as 0 and the gate widths of the inverter 21 and the inverter 32 are approximately the same, the input level of the inverter 31 becomes the intermediate potential.

Also in a D-type flip-flop which is composed of a GaAs semiconductor element and whose transfer gate is an FET1 element, when both the positive-phase clock signal φ and the negative-phase clock signal ▽ φ are at a high level, the CMOS configuration is achieved. The same phenomenon occurs as in the case. On the other hand, when both the forward and reverse clock signals are low level, the outputs of the feedback inverters 22 and 32 are not fed back to the inverters 21 and 31, so that data is not retained.

In the LSI, due to the difference in the wiring length, the skew of the clock signals of the positive phase and the negative phase is deviated, and the waveform is blunted by the wiring load and the fanout load.
It is easy for the reverse two clock signals to be both low level or high level. In particular, in a large-scale logic LSI, the wiring length increases and the number of fan-outs increases, and as a result, the conventional D shown in FIG.
Timing design using type flip-flop was very difficult. Further, the conventional D-type flip-flop requires at least two clock signals for both positive and negative phases, and in some cases four clock signals, and it is necessary to design the driving capability of the clock buffer circuit for supplying the clock signal to be large. Therefore, there is a drawback that it is difficult to reduce power consumption.

In recent years, as the speed of LSIs has been increased for the purpose of improving the processing speed of EWS (engineering workstations) and ultra-high speed computers, how to cool the temperature rise due to heat generation of chips has become a big problem. There is. For this reason, there is a demand for a circuit that can easily perform timing design and reduce the power consumption of an LSI while maintaining the high-speed performance of the conventional D-type flip-flop.

An object of the present invention is to provide a field effect transistor logic circuit which can easily perform timing design while maintaining high speed performance and can reduce the power consumption of an LSI.

[0012]

According to another aspect of the present invention, there is provided a field effect transistor logic circuit, comprising: a transfer gate for receiving a data signal externally input to an input terminal in synchronization with a clock signal and outputting the data signal to an output terminal. A first inverter having an input end connected to the output end of the transfer gate, an input end connected to an output end of the first inverter, an output end connected to an input end of the first inverter, and a load A second inverter having a drive capacity smaller than the load drive capacity of the first inverter, and is configured to extract an output signal from an output terminal of the first inverter.

A field effect transistor according to a second aspect of the present invention is configured such that the above field effect transistors are connected in a two-stage vertical example, and clock signals having mutually opposite phases are applied to the field effect transistors.

According to a third aspect of the present invention, there is provided a field effect transistor logic circuit, wherein a transfer gate for fetching a data signal externally input to an input end in synchronization with a clock signal and outputting the data signal to an output end, and the transfer gate for the input end. A gate circuit connected to the output end of the first inverter, an input end connected to the output end of the gate circuit, an input end connected to the output end of the first inverter, and an output end connected to the gate A second inverter connected to the input end of the circuit and having a load driving capability smaller than the load driving capability of the gate circuit, and configured to take out an output signal from the output end of the gate circuit.

A field effect transistor according to a fourth aspect of the present invention is configured such that the field effect transistors are connected in two-stage cascades and clock signals having mutually opposite phases are applied to the field effect transistors.

[0016]

In the field-effect transistor logic circuit according to the present invention, a master latch including a transfer gate for capturing data and two inverters whose input and output are connected to each other, and a slave latch having the same configuration as the master latch It forms a D-type flip-flop. By setting the driving capability of the feedback inverter of each latch circuit to a small value, data competition is prevented and latching is ensured. According to the present invention, since only one clock signal for the transfer gate is required for each latch circuit, the timing design is relatively easy,
Further, since the fanout number of the clock buffer circuit is 1/4 to 1/2 as compared with the conventional circuit, the power consumption of the clock buffer circuit can be reduced, and as a result, the power consumption of the LSI can be reduced. It is possible to

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. Referring to FIG. 1, this embodiment has a configuration in which a master latch 2 and a slave latch 3 are connected in series. The present embodiment differs from the conventional D-type flip-flop shown in FIG. 3 in the configuration of each latch circuit.

In the master latch 2 of this embodiment, G
The source electrode of a junction gate type enhancement type FET 23 using an aAs crystal is connected to the data input terminal 11, the gate electrode is connected to the clock input terminal 13, and the drain electrode is connected to the input terminal 41 of the inverter 21. The input end 41 of the inverter 21 is connected to the drain electrode of the FET 23, and the output end 42 is connected to the input end of the feedback inverter 22. The output end of the inverter 22 is connected to the input end 41 of the inverter 21. In this master latch 2, the gate width of the FET that constitutes the feedback inverter 22 is set smaller than the gate width of the FET that constitutes the inverter 21. The reason for providing the difference in the gate widths of the inverters in this way is that data competition occurs when the driving capability of the circuit (not shown) in the preceding stage that supplies the input data is about the same as the driving capability of the inverter 22. This is to prevent it. For example, the output of the circuit in the previous stage (the potential level of the data input terminal 11) is at the high level, and the feedback inverter 2
This is because if the output of 2 is low level, the input of the inverter 21 may be at an intermediate potential and the input data may not be latched.

In this master latch 2, when the high-level clock signal φ is input to the clock input terminal 13, the data D applied to the data input terminal 11 is transmitted to the output terminal 42 via the inverter 21, and further, The data is held by being positively fed back by the inverter 22. On the other hand, when the clock input signal φ is low level, the latch circuit retains the data so far.

Also in the slave latch 3, the GaAs junction gate type enhancement FET 33, the inverter 31, and the feedback inverter 32 are connected to each other in the master latch 2.
Are connected in the same manner as in (1) to form a latch circuit.

In this embodiment, a D-type flip-flop is constructed by using the master latch 2 and the slave latch 3 as described above. The output terminal 42 of the master latch 2 is the FET 3 as the transfer gate of the slave latch 3.
3 and the output terminal of the slave latch 3 is the output terminal 15. The positive-phase cloak signal φ is input to the gate electrode of the FET 23 as the transfer gate of the master latch 2, and the negative-phase clock signal ∇φ is input to the gate electrode of the FET 33 as the transfer gate of the slave latch 3. That is, clock signals having opposite phases are input to the transfer gate of the master latch 2 and the transfer gate of the slave latch 3. This embodiment operates as follows.

Now, when the high-level clock signal φ is input to the clock input terminal 13, the data input terminal 11
The data D applied to is transmitted to the output terminal 42 via the inverter 21, and is further positively fed back by the feedback inverter 22, whereby the data is held. At this time, since the clock input signal ∇φ is low level, the input data is not transmitted to the slave latch 3 in the next stage. Next, when the clock input signal ∇φ becomes high level, the output of the master latch 2 in the first stage is written in the slave latch 3 in the next stage. On the other hand, since the clock input signal φ is at the low level, the first stage latch circuit holds the data so far.

In the present embodiment, the feedback inverter 2
The gate width of the FETs forming the inverters 2 and 32 is equal to that of the inverter 2
The width is set to be smaller than the gate width of the FETs forming 1, 31. The reason for providing the difference in the gate widths of the inverters in this way is to prevent the data contention from occurring when the driving ability of the circuit at the previous stage that supplies the input data is about the same as the driving ability of the feedback inverter at the next stage. This is because. For example, the gate width of the FET that constitutes the inverter 21 of the master latch 2 and the gate width of the FET that constitutes the feedback inverter 32 of the slave latch 3 are approximately the same, the output of the inverter 21 is high level, and the output of the feedback inverter 32 is When is low level, input data may not be latched.

This embodiment is different from the conventional D-type flip-flop shown in FIG. 3 in that feedback inverters 22 and 32 are provided.
Since a transfer gate is not required for the output of, the number of fanouts of the clock buffer can be at least halved compared to the conventional one, and there is also an advantage that the gate width of the clock buffer can be reduced, resulting in the consumption of LSI. It also has the effect of reducing power consumption. In particular, when a junction gate type FET using GaAs crystal or Si crystal is used as an element, it is possible to easily obtain a transistor with a threshold value near 0 V by controlling the thickness of the epitaxial crystal layer and the impurity concentration of the ion implantation layer. Therefore, the transfer gate is FET
Even if it is configured with only one element, attenuation of the data signal amplitude due to "threshold drop" does not pose a problem and its effect is large.

Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram of the second embodiment of the present invention.
Referring to FIG. 2, the present embodiment differs from the first embodiment shown in FIG. 1 in the circuit configuration of the master latch 2 and the slave latch 3.

In the master latch 2 of this embodiment,
The source electrode of the junction gate type enhancement type FET 23 using a GaAs crystal is used as the data input terminal 11.
The gate electrode is connected to the clock input terminal 13 and the drain electrode is connected to the input terminal 41 of the level shift type gate circuit 24. The input end 41 of the gate circuit 24 is connected to the drain electrode of the FET 23, and the output end 42 is connected to the input end of the inverter 25. The inverter 25 has an input end connected to the output end 42 of the gate circuit 24 and an output end connected to the input end 44 of the inverter 26. The inverter 26 has an input connected to the node 44 and an output end connected to the input end 41 of the gate circuit 24. In the master latch 2, the gate width of the FET forming the inverter 26 is set smaller than the gate width of the FET forming the level shift gate circuit 24. The reason for providing the difference in the gate width of the inverter in this way is to prevent the contention of the data of the output of the circuit at the previous stage for supplying the input data and the output of the feedback inverter.

In this master latch 2, when a high-level clock signal φ is input to the clock input terminal 13, an output in phase with the data D applied to the data input terminal 11 is output to the output end 42 via the gate circuit 24. Is transmitted,
Further, by being fed back by the inverters 25 and 26,
Data is retained. Next, when the clock input signal φ becomes low level, the latch circuit holds the written data. The reason why two stages of feedback inverters are used is that the voltage gain of the level shift type gate circuit 24 is 1 or less. For example, when the common mode output of the differential circuit is used instead of this gate circuit, Since the gain is 1 or more, the feedback circuit can be provided in one stage.

Also in the slave latch 3, a GaAs junction gate type enhancement FET 33, a level shift type gate circuit 34, and a two-stage inverter 3 for feedback.
5, 36 are connected in the same manner as in the master latch 2 to form a latch circuit.

In the present embodiment, the master latch 2 and the slave latch 3 as described above are used to form a D-type flip-flop. The output terminal 42 of the master latch 2 is the FET 3 as the transfer gate of the slave latch 3.
3 and the output terminal of the slave latch 3 is the output terminal 15. The positive-phase clock signal φ is input to the gate electrode of the FET 23 as the transfer gate of the master latch 2, and the negative-phase clock signal ∇φ is input to the gate electrode of the FET 33 as the transfer gate of the slave latch 3. That is, clock signals having opposite phases are input to the transfer gate of the master latch 2 and the transfer gate of the slave latch 3. This embodiment operates as follows.

In FIG. 2, when a high-level clock signal φ is input to the clock input terminal 13, an output in phase with the data D applied to the data input terminal 11 is transmitted to the output end 42 via the gate circuit 24. Then, the data is held by being fed back by the inverters 25 and 26. At this time, since the clock input signal ∇φ is low level, the input data is not transmitted to the slave latch 3 in the next stage. Next, when the clock input signal ∇φ becomes high level, the output of the master latch 2 in the first stage is written in the slave latch 3 in the next stage. On the other hand, since the clock input signal φ is low level, the master latch 2 in the first stage
Holds the data so far.

In the D flip-flop circuit of this embodiment, the gate width of the FETs forming the inverters 26 and 36 is F, which forms the level shift type gate circuits 24 and 34.
Set it smaller than the ET gate width. The reason why the drive capability of the inverter of the feedback circuit is limited in this way is to prevent the contention of the data of the output of the feedback inverter and the output of the circuit at the previous stage which supplies the input data to the respective latch circuits.

[0032]

As described above, in the field effect transistor logic circuit of the present invention, by limiting the load driving capability of the inverter in the feedback circuit forming the latch circuit, the data from the circuit of the previous stage can be saved. In order to prevent contention with the data from the feedback circuit, the transfer gate provided in the feedback circuit is made unnecessary, and only one clock signal in the latch circuit is required.

Therefore, according to the present invention, the logical L
The SI timing design can be facilitated. or,
Since the fanout number of the clock buffer circuit can be reduced to at least 1/2 that of the conventional one, the power consumption of the clock buffer circuit can be reduced and the power consumption of the LSI can be reduced. Furthermore, since the number of elements is small, an LSI having the same function can be downsized, and further large-scale integration can be achieved at the same yield.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional D-type flip-flop.

[Explanation of symbols]

2 Master Latch 3 Slave Latch 11 Data Input Terminal 13, 14 Clock Input Terminal 15 Output Terminal 21, 22, 25, 26, 31, 32, 35, 36
Inverter 23,33 FET 24,34 Gate circuit 27,28,37,38 Transfer gate 41 Input terminal 42 Output terminal

Claims (4)

[Claims] 1. A transfer gate that takes in a data signal externally input to an input terminal in synchronization with a clock signal and outputs the data signal to an output terminal, and a first inverter whose input terminal is connected to an output terminal of the transfer gate. An input terminal connected to an output terminal of the first inverter, an output terminal connected to an input terminal of the first inverter, and a load driving capacity smaller than a load driving capacity of the first inverter; And a field effect transistor logic circuit configured to extract an output signal from an output terminal of the first inverter. 2. A first transfer gate which takes in a data signal externally input to an input terminal in synchronization with a first clock signal and outputs it to an output terminal, and an input terminal which is an output terminal of the first transfer gate. A first inverter connected to the first inverter, an input end connected to an output end of the first inverter, an output end connected to an input end of the first inverter, and a load driving capability of the first inverter. A second inverter having a load driving capability smaller than that of the first inverter; and an input end connected to an output end of the first inverter, and an output signal of the first inverter having a second phase opposite to that of the first clock signal. A second transfer gate that outputs to a capture output terminal in synchronization with the clock signal of the second transfer gate, and an input terminal connected to an output terminal of the second transfer gate, and a load driving capability of the second transfer gate. A third inverter having a load capacity greater than that of the data input terminal, an input terminal connected to an output terminal of the third inverter, an output terminal connected to an input terminal of the third inverter, and a load driving capacity described above. A fourth smaller than the load driving capacity of the first inverter and the load driving capacity of the third inverter;
And a field effect transistor logic circuit configured to extract an output signal from the output terminal of the third inverter. 3. A transfer gate which takes in a data signal input from the outside to an input end in synchronization with a clock signal and outputs it to an output end, a gate circuit whose input end is connected to an output end of the transfer gate, and an input. A first inverter having an end connected to the output end of the gate circuit, an input end connected to the output end of the first inverter, an output end connected to the input end of the gate circuit, and a load driving capability A second inverter having a load driving capability smaller than that of the gate circuit; and a field effect transistor logic circuit configured to extract an output signal from an output terminal of the gate circuit. 4. A first transfer gate which takes in a data signal externally input to an input terminal in synchronization with a first clock signal and outputs it to an output terminal, and an input terminal which is an output terminal of the first transfer gate. A first gate circuit connected to the first gate circuit, a first inverter having an input terminal connected to the output terminal of the first gate circuit, an input terminal connected to the output terminal of the first inverter, and an output terminal Is connected to the input end of the first gate circuit, the load drive capability is smaller than the load drive capability of the first gate circuit, and the input end is the output end of the first gate circuit. And a second transfer gate for outputting the output signal of the first gate circuit to the output terminal in synchronization with the second clock signal having a phase opposite to that of the first clock signal, and the input terminal The second A second gate circuit connected to the output terminal of the transfer gate and having a load driving capacity larger than that of the second inverter; and an input terminal connected to the output terminal of the second gate circuit. And an input terminal connected to an output terminal of the third inverter, an output terminal connected to an input terminal of the second gate circuit, and a load driving capacity of the first gate circuit. And a fourth smaller than the load driving capability of the second gate circuit
And a field effect transistor logic circuit configured to extract an output signal from an output terminal of the second gate circuit.