JP3011595B2 - Delay flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay type flip-flop circuit (hereinafter, referred to as D-FF) in a digital circuit.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Literature; IEICE Technical Report, SSD84-115
(1985) Ichioka / Tanaka / Kakutani / Matsuura / Kawakami / Ishida, "1 GHz Low Power Consumption GaAs Variable Divider" 89-
FIG. 2 is a circuit diagram showing an example of the configuration of the D-FF used in the ultra-high-speed, low-power-consumption variable frequency divider described in the above document. The D-FF includes a data input terminal 1 for inputting data D, a clock input terminal 2 for inputting a clock CK, a first output terminal 3 for an in-phase output Q, and an anti-phase output Q
/ Output second terminals 4, and six NOR gates 11, 12, 13, 1 between input / output terminals 1-4.
4, 15, and 16 are connected. NOR gate 11,
Numeral 12 is cross-connected between the clock input terminal 2 and the first and second nodes N1 and N2. The second node N2, the clock input terminal 2, and the first node N1 are connected to the input side of the NOR gate 13, and
A third node N3 on the output side of the OR gate 13 is connected to the input side of the NOR gate 14 together with the data input terminal 1. The output side of the NOR gate 14 is connected to the first node N
1 connected. NOR gates 15 and 16 are cross-connected between the second and third nodes N2 and N3 and the first and second output terminals 3 and 4, respectively. Each of the NOR gates 11 to 16 is composed of, for example, a plurality of Schottky barrier gate field effect transistors (hereinafter referred to as M
ESFET).

Next, the operation will be described. When the clock CK and the data D are at a high level (hereinafter referred to as “H”), N
The output of the OR gate 11 is "H", and the NOR gates 12, 1
No. 3 goes low (hereinafter referred to as “L”). When the clock CK changes from “H” to “L”, the output of the NOR gate 13 changes from “L” to “H”, and the in-phase output Q of the NOR gate 15 is determined to be “H”. Clock CK
Is "H" and data D is "L", the NOR gate 14
Is "H" and the outputs of the NOR gates 11, 12, and 13 are "L". When the clock CK changes from “H” to “L”, the output of the NOR gate 12 becomes “L”. When the clock CK changes from “H” to “L”, the output of the NOR gate 12 changes from “L” to “H”, and the in-phase output Q of the NOR gate 15 is determined to be “L”. Accordingly, the in-phase output Q and the anti-phase output Q / synchronized with the clock CK are output from the output terminals 3 and 4.

[0004]

However, the conventional D-FF has the following problems. (A) In the conventional D-FF, since the critical pulse (from the time when the data D is set up and the time when the output Q and Q / changes after the falling of the clock CK) is as long as five stages, the operation speed is low. slow. (B) Two-input NOR gates 11, 12, 1 in FIG.
4, 15 and 16 are each composed of four MESFETs, and a three-input NOR gate 13 is composed of four MESFEs.
T. Since the D-FF shown in FIG. 2 includes six NOR gates 11 to 16, the number of MESFETs constituting the D-FF is 19. Since the number of constituent elements is as large as 19, high integration is difficult. (C) The D-FF is composed of six NOR gates 11 to 16 and has a large number of gates, so that power consumption is large. The present invention solves the problems of the prior art that the operation speed is slow, the number of constituent elements is large, and the power consumption is large, so that it is not suitable for high integration.
An object of the present invention is to provide a D-FF excellent in high speed and capable of high integration.

[0005]

According to a first aspect of the present invention, in order to solve the above-mentioned problems, a D-FF is connected between a clock input terminal and first and second nodes by a first D-FF. A second two-input NOR gate, an inverter having an input connected to a data input terminal, and a depletion-type field effect transistor connected between an output of the inverter and the second node and having a gate grounded ( Less than,
D-FET) and third and fourth two-input NOR gates connected crosswise between the first and second nodes and complementary first and second output terminals. are doing. According to the second invention, another D-gate having a gate grounded is provided between the data input terminal of the first invention and the first node.
FET is connected. In the third invention, the D-FET of the first invention and the other D-FET of the second invention are constituted by N-channel field effect transistors. In the fourth invention, the first, second, third and fourth two-input NOR gates of the first, second and third inventions are respectively constituted by two-input NAND gates. In the fifth invention, the D-FET of the fourth invention and the other D-FET are constituted by P-channel field effect transistors.

[0006]

According to the first aspect, since the D-FF is configured as described above, when the clock falls or rises,
A current is supplied or sucked between the output side of the inverter and the second node via the D-FET whose gate is grounded. Thus, the state of the latch circuit including the first and second NOR gates connected to each other is determined when the clock falls or rises. According to the second aspect, the D- gate having the other gate grounded is provided.
Since current is supplied or drawn between the data input terminal and the first node via the FET, the first and second NOs are supplied when the clock falls or rises.
The state of the latch circuit composed of the R gate is determined to be more stable and faster. According to the third aspect, the current is supplied or drawn between the data input terminal and the first node via the N-channel D-FET whose gate is grounded. Alternatively, at the time of rising, the state of the latch circuit including the first and second NOR gates is determined more stably and at high speed. According to the fourth aspect, at the time of falling or rising of the clock, current is supplied or sucked between the output side of the inverter and the second node via the D-FET whose gate is grounded. Will be As a result, the cross-connected first
And the state of the latch circuit composed of the second NAND gate is determined when the clock falls or rises.
According to the fifth aspect of the present invention, the P gate having the gate connected to the power supply potential is provided.
The data input terminal and the first
The current is supplied or drawn between the first and second nodes, so that the state of the latch circuit composed of the first and second NAND gates is determined more stably and faster when the clock falls or rises. . Therefore, the above problem can be solved.

[0007]

EXAMPLES First Embodiment FIG. 1 is a circuit diagram of a D-FF showing a first embodiment of the present invention. The D-FF includes a clock input terminal 20 for inputting a clock CK, a data input terminal 21 for inputting data D, a first output terminal 22 for an inverted-phase output Q /, and a second output for an in-phase output Q. The terminal 23 is provided. First and second two-input NOR gates 31 and 33 are provided between the clock input terminal 20 and the first and second nodes N11 and N12.
It is connected. That is, the clock input terminal 20 is connected to the first input terminal of the NOR gate 31 and the NOR input.
It is connected to a second input terminal of the gate 32. NOR
The output terminal of gate 31 is connected to first node N11 and NO
The first input terminal of the R gate 32 is connected, and the second input terminal of the NOR gate 31 is connected to the second node N12 and the output terminal of the NOR gate 32. First
Second nodes N11 and N12 and first and second output terminals 2
Third and fourth two-input NOR gates 33 and 34 are cross-connected between the first and second NOR gates 2 and 23, respectively. That is, the first
Is connected to the first input terminal of the NOR gate 33, and the second input terminal of the NOR gate 33 is connected to the second input terminal.
Of the NOR gate 33
Are connected to the first output terminal 22. The second node N12 is connected to a second input terminal of the NOR gate 34, a first input terminal of the NOR gate 34 is connected to the first output terminal 22, and an output terminal of the NOR gate 34 is connected to the second input terminal. 2 output terminal 23. The data input terminal 21 is connected to the input terminal of the inverter 41, and the output terminal is connected to the drain of the N-channel D-FET 42. The gate of the D-FET 42 is
It is grounded, and its source is connected to the second node N12. 2-input NOR gate 3 in D-FF
1, 32, 33, 34 and the inverter 41 are, for example, Di
It is configured using rect coupled FET logic (hereinafter, referred to as DCFL). GaAs ME as this FET
FIGS. 3 and 4 show circuit configuration examples using SFETs.

FIG. 3 shows each of the NOR gates 31 to 34 of FIG.
FIG. This NOR gate has one D-FE
T51 and two enhancement-type FETs (hereinafter, E-
52, 53). D-FET
The E-FET 51 and the E-FET 52 are connected in series between the power supply potential VDD and the ground.
-FET 53 is connected. E-FETs 52 and 53
Are the first and second input terminals IN1 and IN2, and the gate and drain of the D-FET 51 and the E-FET
The drain and the connection point of 52 are the output terminals OUT. FIG. 4 is a circuit diagram of the inverter 41 of FIG. The inverter 41 has a D-FET 61 and an E-FET 62, which are connected in series between the power supply potential VDD and the ground. The connection point between the D-FET 61 and the E-FET 62 is the output terminal OUT, and the gate of the E-FET 62 is the input terminal IN. 3 and 4, each D
-FETs 51 and 61 have a gate width W = 3 μm, a gate length L = 0.5 μm, a threshold voltage = −0.7 V, and a K value = 220.
mS / Vmm. In addition, each E-FET 52, 53,
62 denotes a gate width W = 9 μm and a gate length L = 0.5 μ.
m, threshold voltage = + 0.1 V, K value = 320 mS / Vm
m. These D-FETs 51 and 61 and E-FE
The Schottky voltage of the MESFET at T52, 53, 62 is 0.7V. In the D-FF of FIG.
The gate width W of the MESFETs constituting the NOR gates 31 and 32 is made equal, and the gate width W of the D-FET 42 is set to N
Gate width W of D-FET 51 constituting OR gate 32
To the same extent as Thus, the state of the latch circuit composed of the cross-connected NOR gates 31 and 32 is not forcibly changed by the inverter 41, and the output increases or decreases within the noise margin of the DCFL.

FIG. 5 is a diagram showing an example of operation waveforms of the D-FF shown in FIG. FIG. 6 is a timing chart of the D-FF shown in FIG. The operation of the D-FF of FIG. 1 will be described with reference to these drawings. In the following description, it is assumed that “H” takes a logical value of “1” and “L” takes a logical value of “0”. In FIG. 5, at time t1, data D is "H" and clock CK is "H". At this time,
Output nodes N11, N12 of NOR gates 31, 32
And the output of the inverter 41 is "L". At time t2, when the clock CK falls, the NOR gate 3
The output nodes N11 and N12 of the output terminals 1 and 32 try to become "H". At this time, the output of the NOR gate 32 is set to “H”.
To the inverter 41 via the D-FET 42, the output of the NOR gate 32 becomes N
It is less likely to be “H” than the OR gate 31. for that reason,
First, the output of the NOR gate 31 becomes “H”,
The output of the gate 32 becomes "L". When "L" is written to the latch circuit composed of the cross-connected NOR gates 31 and 32, the element is set so that the "L" output of the inverter 41 becomes a voltage lower than the "L" of the NOR gate 32. , More stable operation and higher speed can be realized. At this time, the inverted-phase output Q / of the NOR gate 33 becomes “L”, and the in-phase output Q of the NOR gate 34 becomes “H”.
become. At time t3, the clock CK is "L",
When the data D changes from “H” to “L”, the output of the inverter 41 becomes “H”. Then, a current flows from the inverter 41 to the output node N12 of the NOR gate 32 via the D-FET 42. As a result, although the voltage at the output node N12 of the NOR gate 32 rises, the resistance between the drain and the source of the D-FET 42 whose gate is grounded increases by the amount of the rise. Voltage rise is suppressed, and the output of the NOR gate 32 can be maintained at "L".

At time t4, the clock CK becomes "H".
And the output node N1 of the NOR gates 31 and 32
1, N12 becomes "L". At this time, the inverter 41
, The voltage of the output node N12 of the NOR gate 32 becomes
It is higher than the voltage of the output side node N11 of the NOR gate 31. At time t5, when the clock CK changes from “H” to “L”, the output nodes N11 and N12 of the NOR gates 31 and 32 try to change to “H”. At this time, the NOR supplied by the inverter 41
The output node N12 of the gate 32 becomes “H” before the output node N11 of the NOR gate 31, and the NOR
The output node N11 of the gate 31 becomes "L". Then, the in-phase output Q of the NOR gate 34 becomes “L” and the negative-phase output Q / of the NOR gate 33 becomes “H”. At time t6, when the clock CK is “L” and the data D changes from “L” to “H”, the output of the inverter 41 changes from “H” to “L”. Then, the output node N12 of the NOR gate 32 is "H", and a current flows into the inverter 41 via the D-FET42. Then, the voltage of the output side node N12 of the NOR gate 32 decreases, and the output voltage of the inverter 41 increases. The D-FET whose gate is grounded by the amount by which the output “L” of the inverter 41 rises
42, the resistance between the source and the drain increases. For this reason, the D-FET 42 can flow only about 1/3 of the current consumption of the NOR gate 32,
2 can maintain “H”.

As shown in the timing chart of FIG.
At time t2, the output of the NOR gate 31 becomes “H”, and the negative-phase output Q / of the NOR gate 33 becomes “L”.
As a result, the in-phase output Q of the NOR gate 34 becomes “H”. Further, at time t5, the output node N12 of the NOR gate 32 becomes “H”, and the in-phase output Q of the NOR gate 34 becomes “L”. Accordingly, the negative-phase output Q / of the NOR gate 33 becomes “H”. As described above, D in FIG.
The -FF operates as a falling edge trigger type flip-flop circuit (FF) in which the in-phase output Q and the anti-phase output Q / are determined according to the data D at the time of the falling edge of the clock CK. In the first embodiment, the D-FF is replaced with four NOs.
Since it is composed of the R gates 31 to 34, one inverter 41, and an N-channel D-FET 42 whose gate is grounded, the number of elements is small, it is suitable for high integration, the power consumption is small, and the setup time is small. One delay time is small and high-speed operation is possible. Therefore, a high-speed large-scale integrated circuit (LS) composed of N-channel D-FETs
It is optimal for realizing I) and the like. As an example, the following table shows a comparison between the setup time and the delay time between the conventional D-FF of FIG. 2 and the D-FF of FIG. 1 of the present embodiment.

[0012]

[Table 1] Here, τ ₀ in the setup time is the average delay time of the inverter, and the delay time is the time from when the clock CK falls until the output changes.

Second Embodiment FIG. 7 is a circuit diagram of a D-FF showing a second embodiment of the present invention, and is common to the elements in FIG. 1 showing the first embodiment and common elements. Are given. This D-FF is the first
Each of the NOR gates 31 to 34 in the embodiment of FIG.
In addition to the AND gates 71 to 74, the N-channel D-FET 42 is replaced with a P-channel D-FET 82. The gate of the D-FET 82 is connected to the power supply VDD. FIG. 8 is a circuit diagram of each of the NAND gates 71 to 74 of FIG. This NAND gate has one N-channel D-FET 91 and two N-channel enhancement FETs (hereinafter, referred to as E-FETs) 92 and 93. The D-FET 91 and the E-FETs 92 and 93 are connected in series between the power supply potential VDD and the ground. The gates of the E-FETs 92 and 93 are first and second input terminals IN1 and IN2, respectively.
The connection point between the gate and drain of the FET 91 and the drain of the E-FET 92 is the output terminal OUT.

FIG. 9 is a timing chart of the D-FF shown in FIG. With reference to this figure, the D-
The operation of the FF will be described. The output nodes N11 and N12 of the latch circuit formed by the NAND gates 71 and 72 are "H" when the clock CK is "L".
When K becomes "H", if the data D is "H", they become "H" and "L", respectively, and if the data D is "L", they become "L" and "H", respectively. After that, the clock CK becomes “H”.
Thus, even if the data changes, the current is suppressed by the D-FET 82, and the state of the latch circuit formed by the NAND gates 71 and 72 does not change. Thus, this second
In this embodiment, a rising edge trigger type D-FF is used. Here, τ ₁ is the time from when the clock CK rises to when the output of the NAND gate 72 changes. Τ ₂ is NAN after clock CK rises.
This is the time until the output of the D gate 71 changes. Further, τ ₃ is the time from when the clock CK rises to when the outputs of the NAND gates 73 and 74 change. As described above, in the second embodiment, the D-FF is configured by four NAND gates 71 to 74, one inverter 41,
And a P-channel D-FET whose gate is connected to a power supply
Since it is composed of 82, as in the first embodiment, the number of elements is small, it is suitable for high integration, the power consumption is small, the setup time is as small as the delay time of one inverter, and high-speed operation is possible. Therefore, it is optimal for realizing a high-speed LSI or the like composed of a P-channel D-FET.

Third Embodiment FIG. 10 is a circuit diagram of a D-FF showing a third embodiment of the present invention, and is common to the elements in FIG. 1 showing the first embodiment and common elements. Are given. In this D-FF,
A grounded gate N-channel D-FET 103 is newly provided, and the drain of the D-FET 103 is connected to the data input terminal 2.
1 and the source is connected to the output node N11 of the NOR gate 31. With such a configuration,
When the clock CK falls, the cross-connected N
The states of the OR gates 31 and 32 are determined more stably and faster than in the first embodiment.

Fourth Embodiment FIG. 11 is a circuit diagram of a D-FF showing a fourth embodiment of the present invention, and the elements common to those in FIG. 7 showing the second embodiment are common. Are given. In this D-FF,
P-channel type D-FET 11 whose gate is connected to a power supply
3 is newly provided, the drain of the D-FET 113 is connected to the data input terminal 21, and the source is the NAND gate 7.
1 output side node N11. With such a configuration, at the time of rising of the clock CK, the state of the cross-connected NAND gates 71 and 72 is changed to the second state.
Are determined more stably and faster than in the embodiment.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (1) In the gate-grounded N-channel D-FETs 42 and 103 shown in FIG. 1 or FIG.
The same operation and effect as those of the above embodiment can be obtained by using a P-channel type D-FET connected to. (2) The gate shown in FIG. 7 or FIG.
P-channel D-FETs 82 and 113 connected to
Even with a grounded gate N-channel D-FET, substantially the same operation and effect as in the above embodiment can be obtained.

[0018]

As described above in detail, according to the first aspect, the D-FF is made up of the first, second, third, and fourth two-input NOR gates, the inverter, and the grounded gate type D-gate. -F
Since it is configured by ET, the number of elements is small, suitable for high integration, and power consumption can be reduced. Furthermore, since the inverter and the gate-grounded type D-FET are provided, the first and second cross-connects are provided when the clock falls or rises.
And the state of the latch circuit constituted by the second NOR gate is determined, so that the setup time is as short as the delay time of one inverter, and high-speed operation becomes possible. Therefore, it is optimal for realizing a high-speed LSI or the like. According to the second aspect, since the D-FF of the first aspect is provided with another grounded-type D-FET, the latch composed of the first and second NOR gates is provided when the clock falls or rises. The state of the circuit is determined to be more stable and faster.
According to the third aspect, since the D-FET of the D-FF of the first or second aspect is configured as an N-channel type, it is most suitable for a semiconductor in which an N-channel type FET can be easily formed. According to the fourth invention, the D-FF of the first or second invention is replaced by the first or second D-FF.
Since the second, third, and fourth two-input NAND gates, inverters, and D-FETs whose gates are connected to the power supply potential are used, the number of elements is small, which is suitable for high integration, and power consumption can be reduced. Further, since the D-FET in which the inverter and the gate are connected to the power supply is provided, the state of the latch circuit composed of the first and second NAND gates which are cross-connected when the clock falls or rises is changed. Since it is determined, the setup time is as short as the delay time of one inverter, and high-speed operation becomes possible.
Accordingly, substantially the same effects as those of the first invention can be obtained. Fifth
According to the invention of the fourth aspect, since another P-channel type D-FET whose gate is connected to the power supply potential is provided in the D-FF of the fourth aspect, the first D-FF is provided when the clock falls or rises.
And the state of the latch circuit composed of the second NAND gate is determined more stably and faster.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a D-FF showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional D-FF.

FIG. 3 is a circuit diagram of a NOR gate in FIG. 1;

FIG. 4 is a circuit diagram of the inverter in FIG. 1;

FIG. 5 is an operation waveform diagram of FIG.

FIG. 6 is a timing chart of FIG.

FIG. 7 is a circuit diagram of a D-FF showing a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a NAND gate in FIG. 7;

FIG. 9 is a timing chart of FIG. 7;

FIG. 10 is a circuit diagram of a D-FF showing a third embodiment of the present invention.

FIG. 11 is a circuit diagram of a D-FF showing a fourth embodiment of the present invention.

[Explanation of symbols]

31, 32, 33, 34 First, second, third, fourth two-input NOR gate 41 Inverter 42, 103 N-channel type D-FET 71, 72, 73, 74 First, second, third, third Fourth two-input NAND gate 82,113 P-channel type D-FET CK Clock D Data Q In-phase output Q / Negative-phase output

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-53-92655 (JP, A) JP-A-62-258514 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 3/356

Claims (5)

(57) [Claims] A first and a second two-input NOR gate connected to each other between a clock input terminal and first and second nodes; an inverter having an input side connected to a data input terminal; A depletion-type field-effect transistor connected between the output side of the inverter and the second node, the gate of which is grounded; and first and second output terminals complementary to the first and second nodes. The third and fourth twos which are cross-connected
A delay-type flip-flop circuit comprising an input NOR gate. 2. The delay flip-flop circuit according to claim 1, wherein another depletion type field effect transistor whose gate is grounded is connected between said data input terminal and said first node. . 3. The delay flip-flop circuit according to claim 1, wherein said depletion type field effect transistor and another depletion type field effect transistor are formed by N-channel type field effect transistors. 4. The delay flip-flop according to claim 1, wherein said first, second, third and fourth two-input NOR gates are each constituted by a two-input NAND gate. circuit. 5. The delay type flip-flop circuit according to claim 4, wherein said depletion type field effect transistor and another depletion type field effect transistor are constituted by P channel type field effect transistors.