JPS622339B2 - - Google Patents

Info

Publication number
JPS622339B2
JPS622339B2 JP55188661A JP18866180A JPS622339B2 JP S622339 B2 JPS622339 B2 JP S622339B2 JP 55188661 A JP55188661 A JP 55188661A JP 18866180 A JP18866180 A JP 18866180A JP S622339 B2 JPS622339 B2 JP S622339B2
Authority
JP
Japan
Prior art keywords
microcomputer
test
board
program
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55188661A
Other languages
Japanese (ja)
Other versions
JPS57113155A (en
Inventor
Noriaki Nino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55188661A priority Critical patent/JPS57113155A/en
Publication of JPS57113155A publication Critical patent/JPS57113155A/en
Publication of JPS622339B2 publication Critical patent/JPS622339B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3648Software debugging using additional hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)

Description

【発明の詳細な説明】 本発明はマイクロコンピユータを製品に装着す
る前に予じめそのプログラムをチエツクする検査
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection device that checks the program of a microcomputer before it is installed in a product.

近来、マイクロコンピユータの応用は著しく、
種々の製品に利用されているが、そのソフトウエ
ア開発と共にその検査が重要な役割を占めてい
る。
In recent years, the application of microcomputers has been remarkable.
It is used in a variety of products, and its testing plays an important role along with its software development.

従来、マイクロコンピユータのソフトウエアの
確認は、メモリーの内容を全部調べるか、正しい
CPUを用意しておき供試品と同じ信号を与えた
場合の返答信号を比較する方法によつている。し
かしながら、これらの方法によるとメモリーの内
容の静的な状態は確認できるが、それをシーケン
ス的に動作させた場合にうまく働くかどうかは実
際の回路に組み込まないとわからない。例えばメ
モリーの内容を調べるだけでは、リセツト信号を
入れた場合にゼロ番地からスタートするかどうか
と云うことがわからない。又、CPUを比較する
方法では外部回路によりシーンケンスがうまく働
かない場合もあり、このように実際に使用する状
態と試験状態とが異なる方法は最良とは云えな
い。
Traditionally, checking the software of a microcomputer involves checking the entire memory contents, or checking the correctness of the software.
This method is based on preparing a CPU and comparing the response signals when the same signal as the sample is applied. However, although these methods allow checking the static state of memory contents, it is not possible to know whether they will work well when operated sequentially until they are incorporated into an actual circuit. For example, just by checking the contents of the memory, it is not possible to tell whether or not it will start from address zero when a reset signal is input. In addition, in the method of comparing CPUs, the sequence may not work properly depending on the external circuit, and such a method in which the actual usage state and the test state are different cannot be said to be the best.

そこで本発明はこれらを解決すべく成されもの
であつて、特にメモリーを内蔵した1チツプマイ
クロコンピユータのプログラムの良否を確実にチ
エツクできるものを提供する。
Therefore, the present invention has been made to solve these problems, and particularly provides a device that can reliably check the quality of the program of a one-chip microcomputer with a built-in memory.

本発明の検査装置は、製品基板と同じ回路構成
の試験用回路を有する試験用基板のマイクロコン
ピユータ装着部に取付けたソケツトに、被試験マ
イクロコンピユータを装着し、試験用基板上の所
定のテストポイントにチエツクピンを当接して、
被試験プログラムの全てのパターンについて順次
チエツクするよう構成された制御装置によるチエ
ツクを可能にした後、被試験マイクロコンピユー
タのプログラムを実際のシーケンスに従つて動作
させてその良否を判定するよう構成したことを特
徴とするものであつて、以下本発明の一実施例を
図面に基づいて説明する。
The inspection device of the present invention attaches the microcomputer under test to a socket attached to the microcomputer mounting part of a test board that has a test circuit with the same circuit configuration as the product board, and connects the microcomputer to a predetermined test point on the test board. Touch the check pin to
After enabling a control device configured to sequentially check all patterns of the program under test, the program is configured to run the program of the microcomputer under test according to the actual sequence and determine its acceptability. An embodiment of the present invention will be described below with reference to the drawings.

第1図は製品基板に装着されるメモリー内蔵型
1チツプマイクロコンピユータを予じめチエツク
する検査装置の構成を示し、1は被試験マイクロ
コンピユータチツプ、2は試験後のマイクロコン
ピユータチツプ1が装着される製品基板のうち予
じめ動作のチエツクが完了した正常な製品基板
で、ここでは製品基板と同じ回路構成の試験用回
路を有する試験用基板として用いられており、マ
イクロコンピユータ装着部には被試験マイクロコ
ンピユータチツプ1と同じピン数のICソケツト
3が装着されている。4は信号インターフエース
で、試験用基板としての前記製品基板2と該信号
インターフエース4とは製品基板2自身のコネク
タ5と幾つかのチエツクポイントを通じて接続さ
れており、信号インターフエース4は信号レベル
の整合および保護回路から構成されている。第2
図a,bは製品基板2を装着する治具を示し、製
品基板2が載置されるマウント6はレバー7の回
動操作によつてばね8の上方への付勢に抗して下
へ垂直移動できるよう構成されており、マウント
6の上面にはマウント6との間で製品基板2を挾
持する爪9が設けられており、マウント6の降下
によつて製品基板2の半田面の所定のテストポイ
ントに固定側のチエツクピン10が当接するよう
構成されている。また第1図において、11は製
品基板2に対して所定の擬似信号を与えると共に
その擬似信号に対して製品基板2からの応答信号
をチエツクする制御装置としてのマイクロコンピ
ユータで、例えばZ80 CPUを使用しており、試
験手順のプログラムを格納するメモリー12に基
づいて動作する。13は前記信号インターフエー
ス4とマイクロコンピユータ11との間に介装さ
れたI/O装置で、マイクロコンピユータ11と
信号インターフエース4との間のやり取りを行
う。14はコンソールパネル上のNG信号、スタ
ートおよびストツプのスイツチ、モード表示灯を
表わし、マイクロコンピユータ11によりコント
ロールされる。
Figure 1 shows the configuration of an inspection device that pre-checks a 1-chip microcomputer with a built-in memory installed on a product board, where 1 is the microcomputer chip under test, and 2 is the microcomputer chip 1 after the test is installed. This is a normal product board whose operation has been checked in advance among the product boards that are used.Here, it is used as a test board that has a test circuit with the same circuit configuration as the product board, and there is no cover on the microcomputer mounting part. An IC socket 3 with the same number of pins as the test microcomputer chip 1 is installed. 4 is a signal interface, and the product board 2 as a test board and the signal interface 4 are connected to the connector 5 of the product board 2 itself through several check points, and the signal interface 4 is connected to the product board 2 as a test board through several check points. It consists of matching and protection circuits. Second
Figures a and b show a jig for mounting the product board 2, and the mount 6 on which the product board 2 is placed is moved down by rotating the lever 7 against the upward bias of the spring 8. It is configured to be vertically movable, and claws 9 are provided on the upper surface of the mount 6 to clamp the product board 2 between the mount 6 and the solder surface of the product board 2 by lowering the mount 6. The fixed side check pin 10 is configured to come into contact with the test point. Further, in FIG. 1, numeral 11 is a microcomputer as a control device that gives a predetermined pseudo signal to the product board 2 and checks a response signal from the product board 2 in response to the pseudo signal, and uses, for example, a Z80 CPU. It operates based on a memory 12 that stores a test procedure program. Reference numeral 13 denotes an I/O device interposed between the signal interface 4 and the microcomputer 11, which performs communication between the microcomputer 11 and the signal interface 4. Reference numeral 14 represents an NG signal, start and stop switches, and a mode indicator light on the console panel, which are controlled by the microcomputer 11.

次にチエツク動作に基づいてマイクロコンピユ
ータ11、メモリー12およびI/O装置13の
動作を詳細に説明する。
Next, the operations of the microcomputer 11, memory 12 and I/O device 13 will be explained in detail based on the check operation.

チエツク動作は、先ずICソケツト3を介して
被試験マイクロコンピユータチツプ1が装着され
た製品基板2を、完成した1枚の製品基板とみな
してマイクロコンピユータ11は信号インタフエ
ース4を通じて完成後の製品基板使用状態におけ
る入力信号に相当する擬似信号を与える。次いで
マイクロコンピユータ11は、与えた擬似信号に
対し被試験マイクロコンピユータチツプ1のプロ
グラムに従つて製品基板2から出力される応答信
号をチエツクし、前記擬似信号と応答信号の両者
の関係を被試験マイクロコンピユータチツプ1の
全プログラムパターンについて順次チエツクす
る。このようにしてマウント6に載置された製品
基板2のシユミレーシヨンを実行するため、被試
験マイクロコンピユータチツプ1のメモリーのプ
ログラムを実動作でチエツクすることができ、プ
ログラムの良否を確実にチエツクできる。また被
試験マイクロコンピユータチツプ1を装着する試
験用基板として、検査後のマイクロコンピユータ
チツプが装着される製品基板を用いることができ
るため、特別な試験用基板を作る必要がない。
又、第2図のような治具は各製品基板にマイクロ
コンピユータチツプを装着した完成基板の完成検
査に利用することができる。
In the check operation, first, the product board 2 on which the microcomputer chip 1 under test is mounted via the IC socket 3 is regarded as one completed product board, and the microcomputer 11 connects it to the completed product board via the signal interface 4. Provides a pseudo signal corresponding to the input signal in use. Next, the microcomputer 11 checks the response signal output from the product board 2 according to the program of the microcomputer chip 1 under test in response to the given pseudo signal, and checks the relationship between the pseudo signal and the response signal. All program patterns of computer chip 1 are sequentially checked. Since the product board 2 placed on the mount 6 is simulated in this way, the program in the memory of the microcomputer chip 1 to be tested can be checked in actual operation, and the quality of the program can be reliably checked. Further, since the product board to which the tested microcomputer chip 1 is mounted can be used as the test board to which the microcomputer chip 1 to be tested is mounted, there is no need to create a special test board.
Further, a jig as shown in FIG. 2 can be used for completing inspection of each product board with a microcomputer chip mounted thereon.

以上説明のように本発明によると、マスク化さ
れた1チツプマイクロコンピユータのソフトウエ
アを、チツプ受入時に最終使用状態で簡単かつ確
実にチエツクでき、1チツプマイクロコンピユー
タを用いた製品の生産管理面に大なる効果をもつ
ものである。
As explained above, according to the present invention, it is possible to easily and reliably check the software of a masked one-chip microcomputer in the final use state when receiving the chip, which is useful for production management of products using one-chip microcomputers. It has a great effect.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一実施例を示し、第1図は検査
装置の構成図、第2図aは検査に際して使用する
治具の平面図、第2図bは第2図aの側面図であ
る。 1……被試験マイクロコンピユータチツプ、2
……製品基板〔試験用基板〕、3……ICソケツ
ト、11……マイクロコンピユータ〔制御装
置〕。
The drawings show one embodiment of the present invention; FIG. 1 is a configuration diagram of an inspection device, FIG. 2a is a plan view of a jig used for inspection, and FIG. 2b is a side view of FIG. 2a. . 1...Microcomputer chip under test, 2
...Product board [test board], 3...IC socket, 11...microcomputer [control device].

Claims (1)

【特許請求の範囲】[Claims] 1 製品基板に装着されるメモリー内蔵型1チツ
プマイクロコンピユータのプログラムを予じめチ
エツクする検査装置であつて、前記製品基板と同
じ回路構成の試験用回路を有し、マイクロコンピ
ユータ装着部に被試験マイクロコンピユータチツ
プを着脱可能なソケツトが取付けられた試験用基
板と、この試験用基板に対して実際のシーケンス
に従つて所定の擬似信号を与え、それに対して前
記被試験マイクロコンピユータチツプのプログラ
ムに従つて出力される試験用基板からの応答信号
を被試験プログラムの全てのパターンについて順
次チエツクするよう構成された制御装置と、前記
試験用基板の半田面の所定のテストポイントに当
接可能で前記制御装置によるチエツクを可能にす
るチエツクピンとを設けたことを特徴とする1チ
ツプマイクロコンピユータのプログラム検査装
置。
1 An inspection device that checks in advance the program of a one-chip microcomputer with a built-in memory installed on a product board, which has a test circuit with the same circuit configuration as the product board, and has a test circuit on the part where the microcomputer is installed. A test board is provided with a socket to which a microcomputer chip can be attached and removed, a predetermined pseudo signal is applied to this test board according to the actual sequence, and a predetermined pseudo signal is applied to the test board according to the program of the microcomputer chip under test. a control device configured to sequentially check response signals outputted from the test board for all patterns of the program under test; 1. A program inspection device for a one-chip microcomputer, characterized in that a check pin is provided to enable the device to perform a check.
JP55188661A 1980-12-29 1980-12-29 Program inspection device for one-chip microcomputer Granted JPS57113155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188661A JPS57113155A (en) 1980-12-29 1980-12-29 Program inspection device for one-chip microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188661A JPS57113155A (en) 1980-12-29 1980-12-29 Program inspection device for one-chip microcomputer

Publications (2)

Publication Number Publication Date
JPS57113155A JPS57113155A (en) 1982-07-14
JPS622339B2 true JPS622339B2 (en) 1987-01-19

Family

ID=16227628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188661A Granted JPS57113155A (en) 1980-12-29 1980-12-29 Program inspection device for one-chip microcomputer

Country Status (1)

Country Link
JP (1) JPS57113155A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247343A (en) * 1975-10-14 1977-04-15 Mitsubishi Electric Corp Test equipment for program control apparatus
JPS5391642A (en) * 1977-01-24 1978-08-11 Nec Corp Test system for micro computer unit
JPS54159144A (en) * 1978-06-07 1979-12-15 Komatsu Mfg Co Ltd Debugging device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247343A (en) * 1975-10-14 1977-04-15 Mitsubishi Electric Corp Test equipment for program control apparatus
JPS5391642A (en) * 1977-01-24 1978-08-11 Nec Corp Test system for micro computer unit
JPS54159144A (en) * 1978-06-07 1979-12-15 Komatsu Mfg Co Ltd Debugging device

Also Published As

Publication number Publication date
JPS57113155A (en) 1982-07-14

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