JPS622329A - Arithmetic exception instruction address calculation device - Google Patents

Abstract

PURPOSE:To calculate correctly an exception generating instruction address even when the following instruction is being executed before the preceding instruction is ended, by bringing an instruction address stack to an access by the contents of the second counter corresponding to an arithmetic unit which has generated an arithmetic exception. CONSTITUTION:At every instruction executing indication, an address of its instruction is stored in an address of an instruction address register 1, based on the contents of counters 13-15 corresponding to arithmetic units 3-5 to which an instruction executing indication is executed, and when the arithmetic is ended without an exception by the units 3-5. counters 23-25 are brought to count-up by synchronizing with the counters 13-15. However, when an arithmetic exception is generated in the units 3-5, the counters 23-25 are not brought to count-up, but held in a state that the address of the register 1 which has generated its arithmetic exception remains indicated, and from the register 1, the address of the instruction which has caused the arithmetic exception remains outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to arithmetic exception handling in an information processing device, and particularly to a device for determining the address of an instruction that causes an arithmetic exception.

In an information processing device, when an arithmetic exception such as overflow, underflow, or zero divide occurs during the execution of an arithmetic operation, it is necessary to stop the execution of the subsequent arithmetic operation, generate an interrupt, and perform processing according to the arithmetic exception.

In order to perform such processing, it is first necessary to know in which instruction an operation exception has occurred.

[Conventional technology]

Conventionally, the address of the instruction that generated the operation exception was determined by the address of the instruction that generated the operation exception, for example, as shown in FIG. Interrupt processing is started to prevent the execution of operation (2) following operation +11, and the content of the instruction address register at the time of the interrupt indicates the next address of the instruction that caused the operation exception.

[Problem that the invention seeks to solve]

However, the conventional indexing method described above assumes a system configuration in which the execution of the subsequent instruction starts after the execution of the preceding instruction is completed; in other systems, the address of the operation exception instruction is determined. That is difficult.

That is, in order to improve performance, a plurality of arithmetic units such as an adder, a multiplier, a shifter, etc. are provided, and these arithmetic units are arranged in parallel as shown in FIG. 3(b) or FIG. 3(C), for example. In an operating device, even if subsequent instruction execution is stopped due to an interrupt at a certain point, the instruction address register does not indicate the instruction following the instruction that caused the operation exception. Therefore, it is not possible to notify the software of the address of the instruction that caused the arithmetic exception, making it difficult to have the software perform necessary processing after the arithmetic exception occurs.

The present invention solves these conventional problems, and its purpose is to provide a device that can correctly determine the address of an instruction that causes an operation exception even if a subsequent instruction starts executing before the preceding instruction ends. Our goal is to provide the following.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides an information processing apparatus having a plurality of arithmetic units having different arithmetic functions. a plurality of first counters that are incremented; and a plurality of first counters that are provided corresponding to each of the arithmetic units and that are incremented by a signal from the corresponding arithmetic unit when the arithmetic operation is completed without an arithmetic exception; a first selector that generates an address based on a value indicated by the first counter corresponding to the arithmetic unit 7) to which an instruction execution instruction has been issued; a plurality of exception generation registers that are provided corresponding to each of the arithmetic units and are set when an arithmetic exception occurs in the corresponding arithmetic unit; and the second register that corresponds to the arithmetic unit in which the exception occurrence register is set. a second selector that generates an address based on the indicated value; a second selector that stores the contents of the instruction address register at that time in the address sent from the first selector;
An instruction address stack is provided that outputs the contents stored in the address sent from the selector as the address of the instruction that caused the operation exception.

[Effect]

For each instruction to execute an instruction, the address of that instruction is stored in the address of the instruction address register based on the contents of the first counter corresponding to the arithmetic unit to which the instruction execution instruction was issued. The second counter is counted up in synchronization with the corresponding first counter. However, when an arithmetic exception occurs in the arithmetic unit, the second counter is not incremented, but remains pointing to the address of the instruction address register where the address of the instruction that caused the arithmetic exception is stored. The address of the instruction that caused the operation exception remains output.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, an instruction address register 1 stores an address (instruction address) on the main memory where an instruction to be executed is stored, and an instruction register 2 stores an instruction to be executed. Further, among the plurality of arithmetic units 3 to 5, for example, the arithmetic unit 3 functions as an adder, the arithmetic unit 4 functions as a multiplier, and the arithmetic unit 5 functions as a shifter. Each calculation unit 3
-5 have counters 13-15 . Counters 23-25 are provided. Note that these counters are designed to return to zero when the count value reaches 9, for example.

Among the above-mentioned counters, the counter 13 is incremented when the instruction included in the instruction register 2 is an instruction that uses the arithmetic unit 3, and the counter 13 is incremented when the instruction is instructed to be executed.
Similarly, when the instruction uses the arithmetic unit 4, the counter 15 is counted up when the instruction is instructed to execute the instruction, and when the instruction uses the arithmetic unit 5, the counter 15 is counted up when the instruction is instructed to execute the instruction. Further, the counter 23 is incremented if no arithmetic exception occurs when the arithmetic unit 3 finishes the arithmetic operation, and the counter 24 is incremented if no arithmetic exception occurs when the arithmetic unit 4 finishes the arithmetic operation.
The counter 25 is controlled to count up if no operation exception occurs when the operation of the operation unit 5 is completed.

The selector 6 selects one of the counters 13 to 15 based on usage type information of the arithmetic units 3 to 5 included in the instruction register 2. When an instruction is given to execute an instruction, the contents of the counter 13 are changed to the contents of the counter 13 in the case of an addition instruction. If so, set the contents of the counter 14 as the write address of the instruction address stack 7, and if the shift instruction, set the contents of the counter 15 as the write address of the stack 7.
Send to.

The instruction address stack 7 stores the contents of the instruction address register 1 at the address specified by the selector 6.

Note that the selector 6 sets a constant higher than the values of the counters 13 to 15, such as "1" when selecting the counter 13, so that the addresses of the instruction address stack 7 are not the same among the counters 13 to 15.

When selecting the counter 14, add a constant such as "2" and when selecting the counter 15, add a constant such as "3".

On the other hand, the arithmetic units 3 to 3 instructed by the instruction execution instruction
When the calculation is completed without generating an exception, the circuit 5 sends a signal indicating the completion of the calculation to the counters 23 to 25 via the AND circuit 9 as a count-up signal. However, when an arithmetic exception occurs, on the other hand, such a signal cannot be sent out, and a cent signal is sent out via the AND circuit 12 to exception generation registers 33-35 provided corresponding to each arithmetic unit 3-5. Exception occurrence registers 33 to 35
The output becomes a signal that notifies an interrupt control unit (not shown) of the occurrence of an exception via the OR circuit 8, and the inverted output of the OR circuit 8 closes the AND circuit 9.12. Therefore, counting up of the counters 23 to 25 corresponding to other arithmetic units is prohibited, and setting of other exception generation registers is also prohibited.

The outputs of the respective exception occurrence registers 33 to 35 are also input to the selection determining circuit 10, and the selector 11 selects the output of the counters 23 to 25 corresponding to the arithmetic unit in which the arithmetic exception has occurred in the selection determining circuit 10. The selector 11 is controlled.If two or more of the registers 33 to 35 are sent at the same time, the selection determining circuit 10 selects the registers in a predetermined order, for example, giving priority to the one with the longer execution time of the arithmetic unit. .

The output of the selector 11 is input to the instruction address stack 7 as a read address. Similar to the selector 6, the selector 11 also adds a constant (this constant is the same as the counters 13 to 15) above the values of the counters 23 to 25, and the entry address of the instruction address stack 7 is between the counters 23 to 25. I try not to be the same.

FIG. 2(a) shows an addition instruction (11
is instructed to execute, the multiplication instruction (
In an instruction sequence in which the execution instruction (1) is instructed, the execution of the addition instruction (11) is completed before the execution of the multiplication instruction (11), and the execution instruction and completion of the addition instruction (2) at the instruction address 102 are performed. This is a time chart showing an example of the state of each part in FIG. 1 when, for example, a floating overflow operation exception occurs in addition instruction (2). FIG. FIG.

Counters 13-15. The contents of the counters 23 to 25 are initially zero, and when the real enemy instruction of the addition instruction 111 is given,
The selector 6 sends the address "lO" obtained by adding the constant rlJ to the value rOJ of the counter 13 to the instruction address stack 7, and the stack 7 receives the contents rl of the instruction address register l.
Store oOJ at address "10". Thereafter, the counter 13 is counted up and its content becomes rlJ.

Next, when an instruction to execute the multiplication instruction (1) is given, the selector 6 sends the address "20", which is the value "0" of the counter 14 and the constant "2" added to the instruction address stack 7, and
Stack 7 is the contents of instruction address register 1 r101
Store J at address "20". Then counter 1
4 is counted up and becomes "1".

When the execution of the addition instruction +11 is completed, the counter 23 is counted up and becomes "1" since no operation exception has occurred, and the exception occurrence register 33 is not set.

Next, when execution of addition instruction (2) is instructed, selector 6
sends the address "11" obtained by adding the constant rlJ to the value "1" of the counter 13 to the instruction address stack 7, and the stack 7 stores the contents r102J of the instruction address register 1 at that time in the address "11". Thereafter, the counter 13 is changed to "2".

When the execution of addition instruction (2) is completed, since an arithmetic exception has occurred in this case, the arithmetic exception register 33 is set, and an interrupt control section (not shown) is notified of the occurrence of an arithmetic exception. At this time, the counter 23 is not counted and amplified, so its content remains at "1". In addition, in the selection decision circuit 10, the address rlIJ, which is the content "1" of the counter 23 and the constant "1" added thereto, is sent to the instruction address stack 7 as a continuous address, and an operation exception occurs from the instruction address stack 7. The address r102J of the instruction (addition instruction (2)) is issued one after another.

Note that when the register 33 is set, the AND circuits 9 and 12 are closed by the output of the OR circuit 8, so even if an exception occurs in another operation, the operation exception register is not set.
The counter is not counted up either.

〔Effect of the invention〕

As explained above, the present invention sequentially stores instruction addresses in the instruction address stack corresponding to the arithmetic unit when an instruction is instructed to execute, and in response to a no-exception signal from the arithmetic unit, the instruction address is stored in the instruction address stack corresponding to the arithmetic unit. 2 counter is counted up, and in response to a signal indicating that an exception has occurred, the subsequent count amplification of the second counter is prohibited;
Since the instruction address stack is accessed using the contents of the second counter corresponding to the arithmetic unit that caused the exception, even if the subsequent instruction starts executing before the preceding instruction ends, the address of the instruction that caused the arithmetic exception cannot be accessed. It has the effect of being able to calculate correctly.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIG. 3 is an explanatory diagram of conventional problems. In the figure, 1 is an instruction address register, 2 is an instruction register, 3 to 5 are arithmetic units, 6.11 is a selector, and 7
is an instruction address stack, 8 is an OR circuit, 9 is an AND circuit, 10 is a selection decision circuit, 13° 14, 15 is a first counter, 23.24.25 is a second counter, 33.3
4.35 is an exception occurrence register. Block diagram of an embodiment of the present invention to the main memory FIG. 1 (C1) Instruction address stack 7
II 10Σ=22 output (b) Diagram for explaining the operation of the embodiment Diagram for explaining the problems of the conventional method Fig. 3

Claims (1)

[Claims] In an information processing device having a plurality of arithmetic units having different arithmetic functions, a plurality of arithmetic units provided corresponding to each of the arithmetic units and incremented when an instruction execution instruction is given to the corresponding arithmetic unit. a first counter provided corresponding to each of the arithmetic units, and a plurality of second counters that are incremented by a signal from the arithmetic unit when the arithmetic operation in the corresponding arithmetic unit is completed without an arithmetic exception. a first selector that generates an address based on a value indicated by the first counter corresponding to the arithmetic unit to which an instruction execution instruction has been issued, and a first selector provided corresponding to each of the arithmetic units; Generates an address based on a plurality of exception occurrence registers that are set when an arithmetic exception occurs in a corresponding arithmetic unit, and a value indicated by the second register corresponding to the arithmetic unit in which the exception occurrence register is set. the contents of the instruction address register at that time are stored in the address sent from the first selector;
1. An instruction address stack for outputting contents stored in an address sent from a selector of an instruction address stack as an address of an instruction that caused an operation exception.