JPH0580690B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to arithmetic exception handling in an information processing device, and particularly to a device for determining the address of an instruction that causes an arithmetic exception.

In an information processing device, when an arithmetic exception such as overflow, underflow, or zero divide occurs during the execution of an arithmetic operation, it is necessary to stop the execution of the subsequent arithmetic operation, generate an interrupt, and perform processing according to the arithmetic exception.

In order to perform such processing, it is first necessary to know in which instruction an operation exception has occurred.

[Conventional technology]

Conventionally, the address of the instruction that caused the operation exception was
For example, as shown in Figure 3a, when a calculation unit reports that an operation exception has occurred at the end of execution of a certain type of operation 1, it starts interrupt processing and does not execute operation 2 following operation 1. In this way, the contents of the instruction address register at the time of an interrupt indicate the address of the instruction that caused the operation exception.

[Problem that the invention seeks to solve]

However, the conventional indexing described above is based on a system configuration in which the execution of a subsequent instruction is started after the execution of the arithmetic operation of the preceding instruction is completed.
In other systems, it is difficult to determine the operation exception instruction address.

That is, in order to improve the performance, a plurality of arithmetic units such as adders, multipliers, shifters, etc. are provided and these arithmetic units are operated in parallel as shown in FIG. 3b or 3c, for example. Even if execution of subsequent instructions is stopped due to an interrupt at a certain point, the instruction address register does not indicate the instruction following the instruction that caused the operation exception. Therefore, it is not possible to notify the software of the address of the instruction that caused the arithmetic exception, making it difficult to have the software perform necessary processing after the arithmetic exception occurs.

The present invention solves these conventional problems, and its purpose is to provide a device that can correctly determine the address of an instruction that causes an arithmetic exception even if a subsequent instruction starts executing before the preceding instruction ends. Our goal is to provide the following.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides an information processing apparatus having a plurality of arithmetic units having different arithmetic functions.
a plurality of first counters that are incremented when instructing the corresponding arithmetic unit to execute an instruction; and a plurality of first counters provided corresponding to each of the arithmetic units;
a plurality of second counters that are incremented by a signal from a corresponding arithmetic unit when the arithmetic operation is completed without an exception; a first selector that generates an address based on the value indicated by the counter No. 1; and a first selector provided corresponding to each of the arithmetic units,
Generates an address based on a plurality of exception occurrence registers that are set when an arithmetic exception occurs in a corresponding arithmetic unit, and a value indicated by the second counter corresponding to the arithmetic unit in which the exception occurrence register is set. a second selector that stores the contents of the instruction address register at that time in the address sent from the first selector;
An instruction address stack is provided that outputs the contents stored in the address sent from the second selector as the address of the instruction that caused the operation exception.

[Effect]

For each instruction execution instruction, the address of that instruction is stored in the address of the instruction address register based on the contents of the first counter corresponding to the arithmetic unit to which the instruction execution instruction was given, and when the operation is completed without exception in the arithmetic unit, the The counter 2 is incremented. However, when an arithmetic exception occurs in an arithmetic unit, the second counter is not incremented, but remains pointing to the address of the instruction address register where the address of the instruction that caused the arithmetic exception is stored, The address of the instruction that caused the operation exception remains output.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, an instruction address register 1 stores an address (instruction address) in the main memory where an instruction word to be executed is stored, and an instruction register 2
stores the instruction word to be executed. Further, among the plurality of arithmetic units 3 to 5, for example, arithmetic unit 3 is an adder, arithmetic unit 4 is a multiplier, and arithmetic unit 5 is an adder.
acts as a shifter. Each arithmetic unit 3-5 is provided with counters 13-15 and counters 23-25, respectively. Note that these counters are designed to return to zero when the count value reaches 9, for example.

Among the counters mentioned above, the counter 13 is incremented when the instruction included in the instruction register 2 is an instruction that uses the arithmetic unit 3, and the counter 14 is counted up when the instruction is instructed to execute the instruction that uses the arithmetic unit 4. The counter 15 is counted up when an instruction is issued for execution, and the counter 15 is counted up when an instruction using the arithmetic unit 5 is issued. Further, the counter 23 is incremented if no arithmetic exception occurs when the arithmetic unit 3 finishes the arithmetic operation, the counter 24 is incremented if no arithmetic exception occurs when the arithmetic unit 4 finishes the operation, and the counter 25 is incremented by the arithmetic unit 5. If no operation exception occurs at the end of the operation, the count is incremented.

The selector 6 selects one of the counters 13 to 15 based on the usage type information of the arithmetic units 3 to 5 included in the instruction register 2. When an instruction is instructed to execute, the contents of the counter 13 are changed to the contents of the counter 13 in the case of an addition instruction, and If the instruction is a shift instruction, the contents of the counter 14 and the contents of the counter 15 are sent to the stack 7 as the write address of the instruction address stack 7, respectively.

The instruction address stack 7 stores the contents of the instruction address register 1 at the address specified by the selector 6. In addition, in the selector 6, in order to prevent the address of the instruction address stack 7 from being the same between counters 13 to 15, a constant in the values of counters 13 to 15 is set, for example, "10" when selecting counter 13, and "10" when selecting counter 14. When selecting the counter 15, add a constant such as "20" and "30" when selecting the counter 15.

On the other hand, when the arithmetic units 3 to 5 instructed by the instruction execution instruction complete the arithmetic operation without generating an arithmetic exception, they send a count-up signal to the counters 23 to 25 via the AND circuit 9 to indicate the completion of the arithmetic operation. Send as. However, on the other hand, when an arithmetic exception occurs, such a signal cannot be sent,
A set signal is sent via an AND circuit 12 to exception generation registers 33-35 provided corresponding to each arithmetic unit 3-5. Exception occurrence register 33
The outputs of 35 to 35 become a signal for notifying an interrupt control section (not shown) of the occurrence of an exception via the OR circuit 8, and the inverted output of the OR circuit 8 causes AND circuits 9 and 12.
is closed. Therefore, counting up of the counters 23 to 25 corresponding to other arithmetic units is prohibited, and setting of other exception generation registers is also prohibited.

The outputs of the exception generation registers 33 to 35 are also input to the selection decision circuit 10, and the selection decision circuit 10
The selector 11 is controlled so that the selector 11 selects the output of the counters 23 to 25 corresponding to the arithmetic unit in which the arithmetic exception has occurred. Note that when two or more of the registers 33 to 35 are set at the same time, the selection determining circuit 10 selects them in a predetermined order, for example, giving priority to the one with the longer execution time of the arithmetic unit.

The output of selector 11 is input to instruction address stack 7 as a read address. The selector 11 also has counters 23 to 25 like the selector 6.
The constant above the value of (this constant is the value of counter 13
~15) is added, and the entry address of the instruction address stack 7 is added to the counter 23~2.
I try not to make it the same between 5.

FIG. 2a shows addition instruction 1 at instruction address 100.
is instructed to execute, the multiplication instruction 1 at instruction address 101 is instructed to be executed, and the execution of addition instruction 1 is completed before the execution of multiplication instruction 1 is completed.
In an instruction sequence in which execution of addition instruction 2 is instructed and execution is completed, addition instruction 2
This is a time chart showing an example of the state of each part in FIG. 1 when, for example, a floating overflow operation exception occurs. FIG. 2b is a diagram showing an example of the contents of the instruction address stack 7.

The contents of counters 13 to 15 and counters 23 to 25 are initially zero, and when an instruction to execute addition instruction 1 is given, selector 6 selects the address ``10'', which is the value ``0'' of counter 13 and the constant ``10.''" is sent to the instruction address stack 7, and the stack 7 transfers the content "100" of the instruction address register 1 to the address "10".
Store in. Thereafter, the counter 13 is counted up and its content becomes "1".

Next, when an instruction to execute multiplication instruction 1 is given, the selector 6 sets the value of the counter 14 to "0" and the constant "20".
The address ``20'' resulting from the addition of ``20'' is sent to the instruction address stack 7, and the stack 7 stores the content ``101'' of the instruction address register 1 at address ``20''.
After that, the counter 14 is counted up,
It becomes "1".

When the execution of addition instruction 1 is completed, the counter 23 is incremented to "1" since no operation exception has occurred. Further, the exception occurrence register 33 is not set.

Next, when execution of addition instruction 2 is instructed, selector 6 adds address ``11'', which is the value ``1'' of counter 13 and constant ``10'', to instruction address stack 7.
The stack 7 stores the contents of the instruction address register 1 at that time, ``102'', at the address ``11''. Thereafter, the counter 13 is changed to "2".

When the execution of addition instruction 2 is completed, since an operation exception has occurred in this case, the operation exception register 33 is
is set, and an interrupt control unit (not shown) is notified that an arithmetic exception has occurred. At this time, since the counter 23 is not counted up, its content remains at "1". In addition, in the selection decision circuit 10, the address "11" obtained by adding the constant "10" to the content "1" of the counter 23 is sent to the instruction address stack 7 as a read address, and the instruction address stack 7 receives an operation exception. The address "102" of the generated instruction (addition instruction 2) is read.

Note that when the register 33 is set, the AND circuits 9 and 12 are closed by the output of the OR circuit 8, so even if an exception occurs in another operation, the operation exception register is not set and the counter is not counted up.

〔Effect of the invention〕

As explained above, the present invention sequentially stores instruction addresses in the instruction address stack corresponding to the arithmetic unit when instruction execution is instructed, and stores the instruction addresses corresponding to the arithmetic unit in response to a no-exception signal from the arithmetic unit. Count up the second counter,
In response to a signal indicating that an exception has occurred, subsequent count-up of the second counter is prohibited, and the instruction address stack is accessed using the contents of the second counter corresponding to the arithmetic unit that generated the exception. Therefore, even if the subsequent instruction starts executing before the preceding instruction ends, the address of the instruction that caused the operation exception can be correctly determined.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIG. 3 is an explanatory diagram of conventional problems. In the figure, 1 is an instruction address register, 2 is an instruction register, 3 to 5 are arithmetic units, and 6, 11 are
is a selector, 7 is an instruction address stack, 8 is an OR circuit, 9 is an AND circuit, 10 is a selection decision circuit,
13, 14, 15 are first counters, 23, 2
4 and 25 are second counters, and 33, 34, and 35 are exception generation registers.

Claims (1)

[Scope of Claims] 1. In an information processing device having a plurality of arithmetic units having different arithmetic functions, provided corresponding to each of the arithmetic units,
a plurality of first counters that are incremented when instructing the corresponding arithmetic unit to execute an instruction; and a plurality of first counters provided corresponding to each of the arithmetic units;
a plurality of second counters that are incremented by a signal from a corresponding arithmetic unit when the arithmetic operation is completed without an exception; a first selector that generates an address based on the value indicated by the counter No. 1; and a first selector provided corresponding to each of the arithmetic units;
Generates an address based on a plurality of exception occurrence registers that are set when an arithmetic exception occurs in a corresponding arithmetic unit, and a value indicated by the second counter corresponding to the arithmetic unit in which the exception occurrence register is set. a second selector that stores the contents of the instruction address register at that time in the address sent from the first selector;
An instruction address stack for outputting the contents stored in the address sent from the second selector as the address of the instruction that caused the operation exception.