JPH0250220A - Summarized arithmetic processing machine - Google Patents

Abstract

PURPOSE:To execute processing at high speed by executing the large quantity of summarized arithmetic processing with use of hardware. CONSTITUTION:A memory 1 to store data being the subject of summarized arithmetic, and a subject register 2 to take out the data from this memory and to hold the data as subject data are provided. Then, in order to obtain a maximum value, the subject data to be held in the subject register 2 and the data to be held in a maximum value register 4 are compared and the data of a larger value are stored in the maximum value register 4. In case to obtain a minimum value, the comparison is samely executed and the data are stored. In order to obtain a total value, the data to be held in the subject register are added to a total value register. Namely, the summarized arithmetic processing being executed by software is executed by using the hardware. Thus, the processing is executed at the high speed.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Field of Industrial Application) This invention uses software to perform aggregation calculations to obtain the maximum value, minimum value, total value (and average value), etc. for a plurality of target data. The present invention relates to a processing mechanism for aggregation calculations in a computer device, etc., which is executed at high speed without any problems.

(Prior art) Conventionally, aggregation calculations for calculating the maximum value, minimum value, total value (and average value), etc. for multiple target data are
This was often done sequentially using software.

FIG. 2 is an example of a flowchart showing the execution operation of such a conventional software-based aggregation operation. In this example, by finding the maximum value and total value for a plurality of target data, and counting the number of target data, it is also possible to obtain an average value.

To explain the operation of FIG. 2, first, a storage area for the maximum value and a storage area for the total value are prepared, and the first data of the target data is stored in each of these areas (step 10).
1 to 103). Also, set the counter for the number of target data to [1].
(Step 105).

Then, the following steps (109 to 117) are repeated until there is no more target data (step 107).

First, 1 is added to the counter (step 109), and the next target data (in the order corresponding to the number held in the counter) is retrieved (step 111).

Then, compare the size of this extracted data with the data previously held in the maximum value storage area (Step 113). If the extracted data is larger (Yes at Step 113), the extracted data is stored in the storage area for maximum value (step 115).

Furthermore, this extracted data is added to the storage area for the total value (step 115).

In this way, by repeating steps 109 to 117 described above until the above processing for all target data is completed, the maximum value and total value of all target data are obtained, and this total value is held in the counter. The average value can also be obtained by dividing by the total number of data.

(Problem to be Solved by the Invention) Conventionally, when calculating the maximum value, minimum value, total value, average value, etc. of multiple target data, software has been used to perform the aggregation calculations as described above. were done one by one.

For this reason, as the number of target data increases, the time required for the aggregation processing becomes enormous, and when a computer or the like is used, a large amount of time is occupied for this purpose.

The present invention was made in view of the conventional circumstances, and provides an aggregate arithmetic processing mechanism that uses hardware to perform aggregate arithmetic processing that requires a large amount of processing time, thereby speeding up the processing. The purpose of this is to make it possible to execute the system using a computer, reduce the exclusive time of a computer, etc., and improve the processing performance of the system.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve such an object, the aggregate calculation processing mechanism according to the present invention includes a memory for storing a plurality of data to be subjected to aggregate calculations. and a target register that retrieves the data one by one from this memory and holds it as target data, and further includes the following three groups: a maximum value register, the data stored in this maximum value register, and the target data. a first group consisting of a comparator that compares the values and stores the larger value in the maximum value register, a minimum value register, and compares the data stored in the minimum value register with the target data. , a second group consisting of a comparator that stores the smaller value in the minimum value register, a total value register, an adder that sequentially adds the target data to the total value register, and the data from the memory. and a third group consisting of a counter that increments by 1 each time one is taken out.

(Function) If the aggregate arithmetic processing mechanism has such a configuration, in order to find the maximum value, it is equipped with a maximum value register and a comparator that stores the larger value in this maximum value register. The comparator compares the data stored in the target register with the data stored in the maximum value register, which sequentially retrieves multiple pieces of data to be subjected to aggregate calculation processing from the memory, and selects the larger value as the maximum value. All you have to do is store it in a register.

When finding the minimum value, in almost the same way as for the maximum value above, we have a minimum value register and a comparator that stores the smaller value in this register, and sequentially compare it with the data held in the target register. Just store it.

In addition, to obtain the total value, it is necessary to provide a total value register and an adder that adds the data held in the target register to this register, and perform the additions sequentially.And to obtain the average value, it is sufficient to add the data held in the target register to this register. It is sufficient to have a counter that increments by 1 each time one piece of data is taken out, and divide the total value generated in the total value register by the count value held by this counter.

(Embodiment) FIG. 1 is a block diagram of an aggregation calculation mechanism according to an embodiment of the present invention.

Memory 1 that stores multiple pieces of data that are subject to aggregate calculations
and a target register 2 which takes out the data one by one from this memory I and holds it as target data.

Also, a comparator G3 compares the maximum value register 4 with the data stored in this maximum value register 4 and the target data held in the target register 2, and stores the larger value in the maximum value register 4. is provided.

Similarly, a comparator L5 compares the minimum value register 6 with the data stored in this minimum value register 6 and the target data held in the target register 2, and stores the smaller value in the minimum value register 6. There is.

Further, in response to a total value register 8, an adder 7 that sequentially adds the target data held in the target register 2 to the total value register 8, and a signal a generated each time one piece of data is taken out from the memory 1, A counter 9 that increments by 1 is provided.

Note that 10 is an output bus, and each output value of the maximum value register 4, minimum value register 6, total value register 8, counter 9, etc. is output to this bus 10.

Next, the operation of the aggregation calculation mechanism of this embodiment will be explained.

First, all the plurality of data to be subjected to the aggregation calculation are stored in the memory 1. Further, the total value register 8 and counter 9 are set to zero, the maximum value register 4 is set to the minimum value that can be represented, and the minimum value register 6 is set to the maximum value that can be represented.

Next, one piece of aggregate operation target data is read from the memory 1 and held in the target register 2. At this time, a signal a indicating that new target data is held in the target register 2 is sent from the target register 2, and the counter 9 is incremented by 1 based on this signal a.

The target data held in target register 2 is transferred to comparator G3.
, comparator L5, and adder 7 at the same time.

Then, the comparator G3 compares this target data with the data stored in the maximum value register 4, selects the one with the larger value, outputs it to the maximum value register 4, and stores it.

Further, the comparator L5 compares this target data with the data stored in the minimum value register 6, selects a friend with a smaller value, outputs it to the minimum value register 6, and stores it.

Furthermore, the adder 7 combines this target data with the total value register 8.
and the total value data held in , and send the addition result to the total value register 8 to be held there.

When each process for one piece of target data is completed in this way, the next piece of data is read out from memory 1,
Processing is performed in the same manner as each process described above.

In this way, the data to be subjected to the aggregation calculation stored in the memory 1 is sequentially read out and processed. When the above processing is completed for all target data, the values of each processing result held in the maximum value register 4, minimum value register 6, total value register 8, counter 9, etc. are output to the output bus 10. .

Then, other devices (not shown), such as a computer, read the above-mentioned items outputted via this output bus 10 to obtain aggregate calculation results regarding the maximum value, minimum value, total value, and number of cases (output value of the counter 9). You will be able to obtain it immediately. Further, regarding the average value, by obtaining the total value and dividing it by the number of cases, the aggregation calculation result can be immediately obtained.

In addition, in the aggregation processing mechanism of the above-mentioned embodiment, a configuration was shown in which calculations are performed on all of the maximum value, minimum value, and total value (average value) at the same time, but of course the configuration is not limited to this. Any one or two of the above three types
It is also possible to select and configure only one.

[Effects of the Invention] As described above, the aggregate arithmetic processing mechanism to which the present invention is applied is configured to use dedicated hardware to perform aggregate arithmetic processing that has conventionally been generally performed by software. Aggregate calculation processing can be performed at high speed. Therefore, it becomes possible to significantly reduce the enormous amount of time required for aggregate calculation processing.

In addition, devices such as computers that were traditionally responsible for the above processing are freed from the intensive calculation processing that requires a large amount of time, and can allocate that time to executing other processes. It becomes possible to improve the processing performance as

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an aggregate arithmetic processing mechanism according to an embodiment of the present invention, and FIG. 2 is a flowchart showing an example of the operation of aggregate arithmetic processing by conventional software. 1...Memory 3...Comparator G 5...Comparator L 7...Adder 9...Counter 2...Target register 4...Maximum value register 6...Minimum value register 8...Total value register 10...Output bus

Claims (1)

[Claims] (1) A memory that stores a plurality of data to be subjected to an aggregation operation, and extracts the data one by one from this memory,
A comparator comprising a target register held as target data, a maximum value register, and a comparator that compares the data stored in the maximum value register with the target data and stores the larger value in the maximum value register. a second group consisting of a minimum value register, and a comparator that compares the data stored in the minimum value register with the target data and stores the smaller value in the minimum value register; , a third group consisting of a total value register, an adder that sequentially adds the target data to the total value register, and a counter that adds 1 each time one piece of the data is taken out from the memory. An aggregate calculation processing mechanism characterized by the following.