JPH02100135A - Method of controlling signal processor - Google Patents

Abstract

PURPOSE: To enable high-speed signal processing by executing all of a cycle, wherein operand data are read out of an external memory and arithmetically processed to store the result and an arithmetic result obtain in a last instruction cycle is outputted, in one instruction cycle period through parallel operation. CONSTITUTION: In one instruction cycle, data in the external memory is accessed and the mathematical calculation, logical function, and shift operation of the data are executed to improve the signal processing speed of a measuring instrument, etc. In this one instruction cycle period, not only the transfer of data between the input memory of the equipment and a display memory, but also the addition of an offset value to the data to be transferred, measuring, multiplying, shifting, and other mathematical calculation and logical function can be executed. Thus, the data processing speed can be improved by the parallel operation of an instruction fetch unit, an address calculation unit, and an arithmetic unit constituting the digital signal processor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a DMA for high-speed digital information processing.
The present invention relates to a method for controlling a (direct memory access) type signal processing device.

BACKGROUND OF THE INVENTION Typical current measurement instruments employ programmable digital signal processing processors to execute standard signal processing algorithms and application specific routines. Figure 2 shows
A conventional measurement instrument such as a digital oscilloscope is shown, which includes a digital signal processing device (12).
is included.

In the device (10) of FIG. 2, the analog input signal is processed by an anti-aliasing filter (14) and then fed through the filter (14) to a sampler and AD conversion module (16).

This module (16) sequentially samples the values of the analog input signal at discrete, regularly spaced points in time and converts these sampled data into digital data. This digitized input signal data is transformed according to a signal processing algorithm such as fast Fourier transform (FFT) or filter processing. Note that these signal processing algorithms are a collection of processing steps executed by the digital signal processing device fff (12). Such signal processing algorithms increase computational processing power and are implemented in either hardware or software.

The calculation results of the signal processing device (12) are sent to a DA conversion and filter module (18) and converted into an analog format for use in a display device.

FIG. 3 is a block diagram of a digital signal processing device (12) including a hardware-based associative memory implemented in the measuring instrument (10) of FIG. 1. The signal processing device (12) of FIG. 3 includes a pair of digital memory circuits (memories 1 and 2) (22) and (24). This pair of memories (22) and (24) stores operand data (operated data), and sends these operand data to a μP (microprocessor) (26). μP (26) performs arithmetic calculations and logic functions on these operand data. For example, memories (22) and (24) represent the acquisition and display memories of a digital oscilloscope, respectively. μP
(26), transfer the operand data to μP(26),
The work of retrieving the calculation results in step 6) is controlled by a DMA (direct memory access) controller (28) according to instructions of a program based on the implemented signal processing algorithm.

The DMA controller (28) interrupts the operation of the μP (26) and controls the signal processing device (12) to perform predetermined arithmetic and logic functions;
) control. μP in the signal processing device (12)
(26) takes at least two machine cycles or instruction cycles to complete the task of moving data from memories (22) and (24) to μP (26) and performing arithmetic calculations or logic functions non-stop. It becomes necessary.

The fact that two or more instruction cycles are required to execute a task makes it difficult to achieve the high-speed operation required to improve versatility and enhance performance in response to market demands for the above-mentioned measurement equipment. This poses a major obstacle.

Therefore, an object of the present invention is to provide a method for controlling a signal processing device that enables high-speed digital signal processing.

Another object of the present invention is to provide a method for controlling a signal processing device that can execute a conventional signal processing algorithm in a relatively small number of instruction cycles.

Still another object of the present invention is to provide a DM capable of accessing data in an external memory circuit and executing calculations within one instruction cycle.
An object of the present invention is to provide a method for controlling a digital signal processing device that realizes the function A.

[Means and effects for solving the problem] In the present invention, 1
By implementing the DMA function in a signal processing device, which accesses external memory data within an instruction cycle and executes arithmetic calculations, logical functions, and shift operations on this data, the signal processing speed of measuring instruments, etc. can be increased. It's improving. During this one instruction cycle, the present invention not only transfers data between the capture memory and the display (or buffer) memory within the device, but also adds an offset value to the transferred data. It can also measure, multiply, shift, and perform other arithmetic and logic functions.

Such an improvement in data processing speed is achieved by parallel operation of the instruction fetch unit, address calculation unit, and arithmetic unit that constitute the digital signal processing device. The arithmetic unit selects either to combine results obtained between adjacent instruction cycles or to send results obtained between consecutive instruction cycles to an output terminal in a pipeline manner. You can.

The arithmetic unit includes the functions of a conventional digital signal processing device μP and a DMA controller, thereby forming an intelligent DMA controller. With this arithmetic unit, the .mu.P is no longer needed since it can perform the arithmetic calculations and logic functions described above that are normally required for digital signal processing devices in measurement instruments.

Embodiment FIG. 1 (FIG. 1A, FIG. 1B, and FIG. 1C) is a block diagram showing in detail the internal configuration of a digital signal processing device (40) according to the present invention. This digital signal processing device (
40) allows the execution of normal arithmetic calculations and logic functions required by instrumentation in one instruction cycle.

In FIG. 1, the signal processing device (40) includes an instruction fetch unit (42), an address calculation unit (44L
It includes arithmetic units (46), which operate in parallel to execute all instructions in about 150 nanoseconds. The instruction fetch unit (42) receives instructions stored in an external instruction memory (48), and the arithmetic unit (46) receives instructions stored in two external data memories (50).
and access the data in (52). Instruction memory (4
8) and data memories (50) and (52) are configured with separate paths so that instruction fetching and data access can be performed simultaneously.

Data communication between the instruction fetch unit (42), address calculation unit (44) and arithmetic unit (46) is via an internal register bus (54) and various status flags.

The register bus (54) represents the path along which data moves between each unit and the registers. These data include status flags.

These status flags are created by and accessible to the processor unit via a register bus (54).

These status flags provide each of the instruction fetch, address calculation, and arithmetic units with an indication of the operating state of the other two units and various permitted operating states.

A single instruction performs an arithmetic calculation, transfers one word from each of data memories (50) and (52), modifies the data address pointer, fetches an instruction, and handles branch conditions. , as well as decrementing and testing the loop counter. The operation of each of the three units mentioned above will be explained below.

The instruction fetch unit (42) executes one instruction while fetching the next instruction.

Read from the instruction memory (48) and output terminal (58)
The instructions sent to are stored in a two-stage mask slave type instruction register (60). This slave stage holds the instruction to be executed and the mask stage holds the next instruction. At the beginning of an instruction cycle, the instruction fetch unit (42) reads status flags accessible from the register bus (54) to determine which instruction to execute. The instructions stored in the instruction register (60) are sent to the control circuit (61).

The control circuit (61) generates various clock signals and other control signals necessary to operate the processor (40). SPC (Shadow Program Counter)
(62) outputs on its output terminal (64) a pointer representing the instruction memory address of the instruction to be executed.

The location of the next instruction to be fetched and held in the mask stage of the instruction register (60) is determined by the PC (program counter).
) (66L LIFO (last in first out) type stack register (68), FAR (interrupt address register) (70), MAR (overflow address register) (72), or supplied to instruction memory. PC (66)
and stack register (68) are used in normal operation. IAR (70) is used in interrupt operations, and VAR (72) is used in overflow detection (trap) operations. Stack register (6
8) maintains the appropriate address of the instruction memory depending on the overflow condition.

The digital adder (74) adds a constant value to the output value of the counter (62), and uses the addition result to
counter) (66). The PC (66) outputs on the output (76) a pointer indicating the address of the instruction memory to be fetched next. Note that this pointer assumes that there are no jump or interrupt commands.

The stack register (68) stores and re-stores the addresses of loop instructions and jump to subroutine instructions. Stack register (68) is 5PC
(62) selectively receives an instruction address pointer sent via MUX (7B) and an instruction address pointer sent via a register bus (54) from a repeat counter (described later). MUX (
88) sends the selected instruction memory address to the instruction memory (48) in response to execution of the program's task.

These instructions typically themselves contain the information necessary to perform the task.

The instruction fetch unit (42) has an l0A (iteration counter A) register file (100) and an ICB (
Iteration Counter B) A register file (102) provides indexing for program loops. ICA and ICB register files (100)
and (102) allow nesting of as many as four program loops. Each of these repeat counter register files (100) and (102) contains a reference counter and a working counter that are loaded during the same instruction cycle. To perform such nesting of program loops, the output (106) of the ICB register file (102) is
bus (54) and digital subtractor (108), which in conjunction with MUX (110) decrements the count value in the ICB register file by one during each instruction cycle. The functions of the reference counter and work counter are as follows.

Iteration counter register file (100) and (1
If one zero flag of 02) represents a branch test condition, the work counter for that register file is automatically decremented unless it is already zero. If the value of this working counter is zero, the starting value of the contents of the reference counter is automatically loaded into the working counter, preparing the bus for the next loop. Instruction fetch unit (
By configuring 42) as described above, it is possible to test, decrement and reinitialize in parallel to the operation of the arithmetic unit (46).

The address calculation unit (44) is designed to allow signal processing algorithms implemented in the instrumentation to operate on large and complex data arrays. Many such signal processing algorithms consist of multiple levels of strictly nested loops, and these levels are
Additionally, a large speed tolerance is included in each of the multiple levels of the loop. The address calculation unit (44) includes alternative calculation circuitry for calculating data address pointers for the data memories (50) and (52).

One such circuit is used to sequentially read data from the memory, and the other circuit is used to repeatedly read data from the memory non-sequentially but periodically.

The first circuit of the alternative calculation circuit in the address calculation unit (44) has four address register files (120), (122), (12) arranged in pairs.
4) and (126). , ARAl (Address Register File AI) (120) and ARBI
(Address register file Bl) indicates the storage location of the data memory (50), ARA2 (Address register file A2) (124) and ARB2
(Address register file B2) (126) is
The storage location of the data memory (52) is shown.

One of the 16 registers in each of ARAI (120) and ARA2 (124) is connected to data memory (5
0) is used as a reference pointer to indicate the beginning of the data (e.g. waveform) frame;
The corresponding register in each of RB2 (126) is
It is used as a working pointer for the data (waveform) frame.

The output terminals (12B) and (130) of ARAI (120) and ARA2 (124) are connected to the input terminal of MUX (132), and A'RBI (122) and AR
The output of B2 (126) is connected to the input of MUX (138). Index register (142
) output terminal (140) is connected to MUX (132) and (13
8). Both these MUs
The output terminals (144) and (146) of X are ALUs, respectively.
(Arithmetic logic unit)) (14f3) is connected to the input terminal. MUX (132) and (13B) select reference and working pointers to send to either data memory (50) or (52).

The index register (142)
It implements a continuous index address function with offset capability (eg, the ability to address all third operand data).

The ALU (i4B) can add the reference pointer and the working pointer and output the sum on the output terminal (150), and this output signal can be sent to the register bus (54) or to the second option described below. Supplied to a type 1 calculation circuit. ALU (14
By using 8), there is more flexibility when implementing algorithms including jump instructions and index functions. For example, the reference pointer can be easily indexed by appropriately selecting the reference pointer input of the MUX and the index register output.

The ALU (14B) can then add the fixed reference pointer to the changing index register output to provide the desired indexing.

The sum signal provided on the register bus (54) is then sent to the MUX (152). The output terminal (154) of this MUX is the register file (120), (12
2), (+, 24) and (126), and an appropriate one of these can be updated. During most operations the working pointer is updated. In short, register files (120), (122
), (124) and (126) first generate the addresses, then the ALU (148) processes these addresses and updates the register file that generated these addresses.

The output of the ARBI register file (122) contains the working pointer and is sent via MUX (158) to the address input of the data memory (50). A.R.
Output ends (130) and (13) of A2 register file (124) and ARB2 register file (126)
6) contain a reference pointer and a working pointer, respectively, and are connected to the data memory (52) via MUX (162).
is sent to the address input terminal of.

The second alternative calculation circuit in the address calculation unit (44) is useful when the data pointers are not read sequentially from memory, but repeat a predetermined pattern. This repeating pattern is generated by a modulo and bit reversal counter (164). The counting pattern of this counter (164) is A, LUC14B)0)
It is set by the sum of the reference pointer and the working pointer on the output end (150). This bit reversal feature facilitates the creation of alternating increasing and decreasing address patterns (eg, O17, 1, 6, 2, 5, etc.) suitable for algorithms such as FFT (Fast Fourier Transform). The output terminal (166) of the counter (164) is connected to the MUX (
1, 68) and (170), and these M
Other inputs of UX (168) and (170) receive the sum of the reference pointer and the working pointer. MUX (168
) output terminal (172) outputs the sum of reference pointers as PTR1
(Pattern register 1) (174). This P.T.
The output (176) of Rl is connected to the address input of the data memory (50) via a MUX (158). The output terminal (178) of MUX (170) outputs the sum of working pointers to PTR2 (pattern register 2) (180).
This output terminal (1B2) is connected to MUX (1,62
) to the address input terminal of the data memory (52).

The special processing modes of the second alternative calculation circuit include modulo queue and bit inversion capabilities, which allow data address processing in applications such as averaging, correlation calculations, and FFTs. is simplified.

The arithmetic unit (46) includes a 3-boat register file (200), a parallel multiplier (202), and an ALU.
(204) and a scale barrel shifter (206). During each instruction cycle, the register file (200) can read three operand data and perform two external memory exchanges. The provision of two directly accessible external memories improves application signal processing capabilities such as filter processing, data transfer, and FFT.

Two bidirectional terminals B (
208) and C (210) and data memory (50)
A register bus (5
4), data is sent and received via

At the beginning of an instruction cycle, the arithmetic unit (46) retrieves two or three operands from the register file (200).
Read data, data points read from memory (52) during the previous instruction cycle, and/or preloaded constants. register file (
Data read from the multiplier (202), the ALU (204), and the barrel shifter (206) during the same instruction cycle according to the execution of program instructions. The results of this calculation are then returned and stored in the register file (200).

In particular, the data on the third bidirectional terminal A (212) of the register file (200) is
Sent to one of the input ends. An output end (216) of this MUX (214) is connected to one input end of the multiplier (202) and one input end of the MUX (218). Output end (208) of register file (200)
) is fed directly to the other input of the multiplier (202) and to one input of the MUX (220). Output end (222) of multiplier (202)
is connected to the other input terminal of MUX (220). Output end (224) of MUX (218) and (220)
) and (226) are respectively connected to different input terminals of the ALU (204). Output end (22B) of this ALU
is connected to the input of the barrel shifter (206) and the priority encoder (230). With the above configuration, the ALU (204
) can now selectively combine multiple operand data read from the register file (200) and their products.

Barrel Thick (206) is used to modify the input data, for example, to remove extra logical 1 states at the beginning of small negative data represented in two's complement form, or to normalize the input data. Shift the bit position. Operation of priority encoder (230) causes barrel shifter (206)
determines the number of shifts that the barrel shifter (206) needs to perform, allowing the barrel shifter (206) to efficiently perform the specified shifts during operation.

The output terminal (232) of the barrel shifter (206) is M
connected to the other input end of UX (214),
Connected to bidirectional terminal A (212) for storage in register file (200). Then, depending on the program being executed, the barrel shifter (
The output of the multiplier (202) or the AL
It is sent to U (204). Priority encoder (230
) is connected to the input terminal of the Q register (236) and one input terminal of the MUX (238). The output terminal (240) of this MUX (23B) is
Bidirectional terminal C (210) of register file (200)
) and the other input terminal of MUX (21B). By arranging the input/output terminals of these MUX (23B) and providing the Q register (236) and MUX (214), block floating point operations can be executed on the data processed by the arithmetic unit (46). I can do it.

Since many digital signal processing algorithms implemented in instrumentation are based on multiple accumulation operations, some of the features of the arithmetic unit 1-(46) include parallel multipliers (202) and Also included is an ALU (204). The register file (202) also contains an accumulator for multiple accumulate instructions. The output of the multiplier (202) may be shifted to the left for fractional arithmetic (calculations are made assuming that the decimal point is at the left end of the word), or may be overflowed by executing multiple accumulate instructions in succession. You can shift to the right to avoid this.

Barrel shifter (206) is useful for scaling data and supporting the processor's block floating point operation mode.

The arithmetic unit (46) sets or resets appropriate flags after executing the instruction. Block floating-point arithmetic mode automatically sets the type of scale needed by the algorithm designer to extend dynamic range, but scales only when the scale is required by the size of the data.

The arithmetic unit (46) also includes a non-recovery division algorithm built into the hardware.

The arithmetic unit (46) is the register file (200)
While calculating the data read from the memory (5
The new data point stored in 0) is read and sent to the register file (200) and the result obtained during the previous instruction cycle is read from the register file (200) and sent to memory (52). sent to. Therefore, these entire operations are performed in memory (
This means that line data or processed data has been transferred between 50) and (52).

The operation of the arithmetic unit (46) during one instruction cycle can be summarized by the following three equations.

GR[r,''(-GR[r,] *GR[r,, 1) This formula performs some arithmetic calculation or logic function on the data read from memory (52) during the previous instruction cycle. It shows one of them.

GR[rs+ko+DM, [a d d r
, ] This formula indicates that the data stored at address position 1 of the memory (50) is read and placed in the register file.

address and the loop control mechanism of the instruction fetch unit (42) facilitate data transfer functions. The register file (200) not only facilitates data transfer to and from the data memories (50) and (52), but also allows multiple accumulate shift operations to be performed.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein.
It will be apparent to those skilled in the art that various modifications and changes can be made as necessary without departing from the spirit of the invention.

DMz [a d d r 2] ←GR [
rmz This expression indicates that the contents of the register file (200) are stored in memory (52).

Memories (50) and (52) calculated by the address generator of the address calculation unit (44) [Effects of the Invention] According to the present invention, operand data is read from an external memory and subjected to various necessary arithmetic processing. The process of storing this result and outputting the operation result obtained during the previous instruction cycle can be executed in parallel, all within one instruction cycle, making extremely high-speed signal processing possible. I have to.

[Brief explanation of the drawing]

1A to 1C are block diagrams of a signal processing device according to an embodiment of the present invention, FIG. 2 is a simplified block diagram of a conventional measuring instrument having a digital signal processing device, and FIG. 3 is a block diagram of a conventional measuring instrument having a digital signal processing device. 3 is a block diagram showing the configuration of the signal processing device shown in FIG. 2. FIG. (42) is an instruction fetch unit, (44) is an address calculation unit, (46) is an arithmetic unit, and (50) and (52) are data memories. Agent Hidemori Matsukuma

Claims (1)

[Scope of Claims] A method for controlling a signal processing device that includes an instruction fetch unit, an address calculation unit, and an arithmetic unit that can communicate data with each other, and that executes processing according to a predetermined algorithm, comprising: (a) According to the instruction obtained by the instruction fetch unit, operand data is read from a plurality of data memories, (b) the operand data is transferred to the arithmetic unit, and (c) an operation is performed on the operand data. (d) stores this operation result and outputs the operation result obtained during the previous instruction cycle, and the steps (a) to (d) above are executed by the instruction fetch unit and address calculation unit. and a control method for a signal processing device, characterized in that the control method is executed during one instruction cycle period by parallel operation of arithmetic units.