NL8902040A - HIGH SPEED DIRECT MEMORY ACCESS CONTROL FOR TEST AND MEASUREMENT INSTRUMENTS. - Google Patents

Description

Short designation: High-speed direct memory access control for test and measurement instruments.

The invention relates to direct memory access control circuits for microprocessor-based information systems and in particular to the application of a direct memory access control circuit of a type suitable for high-speed processing of the digital information.

Known test and measurement instruments typically use programmable digital signal processors to perform standard signal processing algorithms and specific routines. Figure 1 shows a known test and measurement instrument 10, such as a digital oscilloscope, into which a digital signal processing subsystem 12 can be mounted.

In Figure 1, an instrument 10 includes an anti-overlap input filter 14 that processes an analog input signal and supplies it to the input of a sample and analog / digital conversion module 16. The module 16 samples the amplitude of the analog signal in discrete, regularly separated time intervals and converts the amplitude values into a digital signal format. The digitized input signal is converted according to a signal processing algorithm, such as a fast Fourier transform (FFT) off-filtering, which is an ordered collection of processing steps performed by processing subsystem 12. Such algorithms are computationally intensive and are realized in hard or soft ware. The result calculated by the processing subsystem 12 is supplied to a digital / analog conversion and filter module 18 which converts the calculation result into an analog format suitable for use by a display unit.

Figure 2 shows a block diagram of a known hardware-type digital signal processing system 12 and associated memory in the instrument 10 of Figure 1. In Figure 2, the processing subsystem 12 includes a pair of digital memory circuits 22, 24 which store operands and supply them to a microprocessor 26 which provides predetermined performs arithmetic calculations and logical functions on the operands.

For example, the memories 22 and 24 are the respective acquisition and display memories of a digital oscillos coop. The transfer of operands to and the transfer of the calculated result from the microprocessor 26 are controlled by a direct access control circuit 28 in accordance with program instructions determined by the signal processing algorithm being implemented.

The digital memory access control circuit 28 interrupts the operation of the microprocessor 26 and takes control of the processing subsystem 12 to perform the predetermined calculations and logic functions and then returns control to the microprocessor 26. The microprocessor 26 in the processing subsystem 12 requires at least two machine or instruction cycles to perform the tasks of moving data from memories 22 and 24 to microprocessor 26 and performing arithmetic calculations or logic functions while it is in progress ("on the fly").

The need for two or more instructional cycles poses an inherent barrier to the very rapid action required to increase versatility and improve performance capabilities required in the market for such instruments.

The object of the invention is therefore to provide a test and measuring instrument which is suitable for very fast digital signal processing.

Another object of the invention is to provide an instrument suitable for performing typical signal processing algorithms with relatively few instruction cycles.

Another object of the invention is to provide in a test and measurement instrument a method of using a digital signal processor to provide a direct memory access capability for accessing data from external memory chains and performing arithmetic functions on the data within a single instruction cycle.

The invention increases the processing speed of input signal information supplied to a test and measuring instrument by providing a direct memory access capability in its digital signal processor for accessing data from external memory chains and for performing arithmetic calculations, logic functions and scrolling operations on the data within a single instruction cycle. During the single instruction cycle, the invention allows not only data transfer between a data acquisition memory and a display or a buffer memory or the like instrument, but also addition of a data shift value, scaling, multiplication, shifts execution of other arithmetic operations and logic functions on the transferred data.

The increase in data processing speed is provided by the parallel operation of an instruction fetch unit, an address calculation unit and an arithmetic unit constituting the digital signal processor. The arithmetic unit is selectively configurable to combine results obtained during adjacent instruction cycles and to rank results obtained during successive instruction cycles for pipeline delivery to an output terminal.

The arithmetic unit incorporates the microprocessor function in the direct memory access control chain into a known digital processing subsystem, thereby forming "intelligent" direct memory access control chains. The arithmetic unit eliminates the need for the microprocessor because the arithmetic unit is arranged to perform the aforementioned arithmetic calculations and logic functions typically required for digital signal processors in the test and measurement instruments.

The invention is elucidated with reference to the drawings. In the drawings shows:

Figure 1 is a block diagram of a known test and measurement instrument employing a known digital signal processing subsystem;

Figure 2 is a block diagram of a known digital signal processing subsystem of the type included in the test and measurement instrument of Figure 1? and

Figure 3 is a detailed block diagram of the internal architecture of a digital signal processor implemented in accordance with the invention.

Figure 3 shows the internal architecture of a digital signal processor 40, which is suitable for single instruction cycle realization of typical arithmetic calculations and logic functions required for test and measurement instruments.

In Figure 3, a processor 40 includes an instruction fetch unit 42, an address calculation unit 44 and an arithmetic unit 46 which operate in parallel and execute all instructions in approximately 150 nanoseconds. The instruction fetching unit 42 receives instructions stored in an external instruction memory 48 and the arithmetic unit 46 accesses data from two external data memories 50 and 52. The data memory 50 stores operands for delivery to the arithmetic unit 46 and the data memory 52 stores results delivered by the arithmetic unit 46. Instruction memory 48 and data memories 50 and 52 are implemented in separate chains to allow simultaneous retrieval of instructions and access of data.

Data communication between the instruction fetch unit 42, the address calculation unit 44 and the arithmetic unit 46 is provided via an internal register bus 54 and various status flags. Register bus 54 represents the internal data paths over which data is moved between the units and registers. This data includes status flags generated by the processor units and accessed by them through register bus 54. The status flags indicate to the instruction fetch unit, the address calculation unit and the arithmetic unit what the other two units are doing and allow a variety of conditional operations. A single instruction can perform an arithmetic operation, transfer a word from each of data memories 50 and 52, change data address pointers, retrieve an instruction, process a current condition, and decrease and test a loop counter. The operation of each of the three units mentioned is explained below.

The instruction fetch unit 52 executes an instruction while it fetches the next instruction. The instructions read on the outputs 58 of the instruction memory 48 are stored in an instruction register 60, which is arranged with a two-stage master-slave arrangement.

The slave stage contains the instruction being executed and the master stage contains the following instruction. At the beginning of an instruction cycle, the instruction fetch unit 42 reads status flags accessible from the register bus 54 to determine which instruction is being executed. The instruction stored in instruction register 60 is supplied to a control circuit 61 which supplies various clock signals and other control signals required for the operation of processor 40. A shadow program counter (SPC) 62 supplies on its output 64 a pointer representative of the instruction memory address of the instruction being executed,

The location of the next instruction to be retrieved and to be stored in the master stage of the instruction register 60 is selected from a program counter (PC) 66; one last in, first out (LIFO) stack register 68; an interruption address register (IAR) 70; an overflow address register (VAR) 72; or an address delivered directly in the instruction. Program counter 66 and stack register 68 are used in normal operation. The interrupt address register 70 is used for interrupts and the overflow address register 72 is used for overflow traps ("overflow traps").

A digital adder 74 counts a unit value at the value proposed by the outputs 64 of the counter 62 and sets the program counter 66 with the result in advance. The program counter 66 provides on its outputs 76 a pointer indicative of the instruction memory address of the next instruction to be retrieved, assuming the presence of no jump or interrupt commands.

The stack register 68 stores instruction addresses for loops and jumps to subroutines (again). The stack register 68 selectively receives instruction address pointers supplied through a multiplexer 78 from the shadow program counter 62, from the program counter 66, and through the register bus 54 from the iteration counters explained below.

A multiplexer 88 supplies the instruction memory 48 with the instruction memory address selected in accordance with the program task being performed. The instructions themselves typically included the information required to perform the task.

The instruction fetcher 42 uses an iteration counter register file (ICA) 100 and an iteration counter register file (ICB) 102, which provide indexing for program loops. The iteration counters 100 and 102 allow nests of up to four program loops. Each iteration counter 100,102 includes a reference counter and a working counter, which are loaded during the same instruction cycle. To provide such program loop nests, the outputs 106 of the iteration counter 102 are connected to the register bus 54 and to a digital subtractor 108, which cooperates with a multiplexer 110 to decrease the content of deiteration counter 102 by one during each instruction cycle. The functions of the reference and work counters are accomplished as follows:

When a zero flag of one of the iteration counters 100 and 102 represents a jump test condition, the working counter is automatically lowered unless it is already zero. When the value of the working counter is zero, the start value present in the reference counter is automatically loaded into the working counter, preparing the counter for the next pass by a loop. The previously explained design of the instruction fetch unit 42 allows testing, lowering and initialization to be performed in parallel with the operation of the arithmetic unit 46.

The address calculation unit 44 is designed to accommodate signal processing algorithms in the test and measurement instruments to operate on large complex data matrixes. Many such algorithms consist of different levels of densely nested loops that are themselves contained in different levels of slower critical loops.

The address calculation unit 44 includes alternative calculation chains that calculate the data address pointers for the data memories 50 and 52. Such a circuit is suitable for reading data sequentially from a memory, and the other chain is suitable for non-sequential but periodic reading of data from a memory.

The first of the alternative calculation chains in dead address calculator 44 uses four address register files 120, 122, 124 and 126 which are arranged in two groups of two address register files. The address register file (ARA ^) 120 and the address register file (ARB ^) 122 point to the locations in a data memory 50, and the address register file (ARA2) 124 and the address register file (ARB2) 126 point to locations in a data memory 52. One of 16 registers in each of the register files 120 and 124 is used as a reference pointer to the beginning of a data (e.g. waveform) frame in the data memory 50, and the corresponding register in each of the register files 122 and 126 is used as a waveform method.

The outputs 128 and 130 of the respective address register files 120 and 124 are connected to inputs of a multiplexer 132, and the outputs 134 and 136 of the respective address register files 122 and 126 are connected to inputs of a multiplexer 138. The outputs 140 of an index register 142 are connected to an input of each of multiplexers 132 and 138, the outputs of which 144 and 146, respectively, are connected to the inputs of an arithmetic logic unit (ALU) 148. The multiplexers 132 and 138 select a reference pointer and a method for delivery to the data memory 50 or the data memory 52. The index register 142 serves to provide a subsequent index addressing function with an index shift capability (e.g., addressing each third operand).

3 The arithmetic logic unit 148 is capable of adding the reference and methods and supplying the sum of its outputs 150 for delivery to register bus 54 or the second of the alternative calculation circuits which will be explained below. The use of the arithmetic logic unit 148 to form the sum of the reference pointer and the method provides greater flexibility in realizing algorithms with jump instructions and index functions. For example, a reference pointer can be easily indexed by properly selecting multiplexer inputs for the index register outputs and the reference pointer. The arithmetic logic unit 148 can then count the fixed reference pointer at the changing index register output to obtain the desired indexing.

The sum supplied to the register bus 54 is then supplied to a multiplexer 152 whose outputs 154 are connected to the preset inputs of the register files 120, 122, 124 and 126 for updating its most suitable file. The process is updated most of the time. In summary, registers 120, 122, 124 and 126 first supply the addresses and the arithmetic logic unit 148 then processes them and updates the registers from which they advance.

The outputs of the registers 122 containing processors are supplied through the multiplexer 158 to the address inputs 156 of the data memory 50. The outputs 130 of the register file 124 and the outputs 136 of the register file 126, which contain reference methods, are supplied via the multiplexer 162 to the address inputs 160 of the data memory 52.

The second of the alternative calculation chains in the address calculator 44 is useful when data pointers are not read sequentially from memory, but follow a repeated predetermined pattern. The repeated pattern is generated by a modulo and bit reversal counter 164, the counting pattern of which is set by the sum of the outputs of the reference pointer and the index register on the outputs 150 of the arithmetic logic unit 148. The debit reversal function facilitates the formation of alternately increasing and decreasing address patterns (e.g., 0, 7; 1.6; 2.5; etc.) that are useful in certain algorithms, such as FFT. The outputs 166 of the counter 164 are supplied to inputs of a pair of multiplexers 168 and 170 which receive the sums of the reference and methods on other inputs. The outputs 172 of the multiplexer 168 supply the sums of the reference pointers to a pattern register (PTR) 174, the outputs 176 of which are supplied via the multiplexer 158 to the address inputs of the data memory 50. The outputs 178 of the multiplexer 170 supply the sums of the methods to a pattern register (PTI) 180, the outputs 182 of which are supplied via the multiplexer 162 to the address inputs of the data memory 52.

The special processing modes available in the second alternative chain include modulo rowing and bit reversal, which facilitates data addressing for averaging, correlation and FFT applications.

The arithmetic unit 46 includes a three-port register file 200, a parallel multiplier 202, an arithmetic logic unit (ALU) 204 and a scaling group shifter (barrel shifter) 206. During each instruction cycle, the register file 200 is suitable for reading up to three operands and performing two external memory exchanges. The presence of two-way accessible external data memories increases throughput for applications such as filtering, FFT data transfers.

Data communication takes place via the register bus 54 between two bidirectional connections (B) 208 and (C) 210 of the register file 200 and the input and output connections of the respective data memories 50 and 52.

At the beginning of an instruction cycle, the arithmetic unit 46 reads from the register file 200 two or three operands, a data point previously read from memory 52 during a previous instruction cycle and / or a pre-loaded constant. The data read from the register file 200 is manipulated by the multiplier 202, the logic logic unit 204 and the group shifter 206 during the same instruction cycle in accordance with the program instruction in progress. The calculated result is then stored back in the register file 200.

Specifically, the data on a third bidirectional terminal (A) 202 of the register file 200 is supplied to one of two inputs of a multiplexer 214, the outputs 216 of which are supplied directly to an input of multiplier 202 and to one of two inputs of a multiplexer 218 turn into. The data on the outputs 208 of the register file 200 are supplied directly to the other input of the multiplier 202 and to one of two inputs of a multiplexer 220. The outputs 222 of the multiplier 202 are connected to the other input of the multiplexer 220. The outputs 224 and 226 of the respective multiplexers 218 and 220 are connected to different inputs of the arithmetic logic unit 204 of which outputs 228 are supplied to the inputs of the group shifter 206 and a priority co door 230. The arrangement explained above allows a selective combination of the operands to be read from the register file 200 and their products to be pre-processed by the arithmetic logic unit 204 in accordance with the program instruction in progress.

Group shifter (barrel shifter) 206 shifts depositions of the bits in the input data to, for example, eliminate the additional leading one-state logic in a small negative data represented in two's complement format or normalize the input data. The operation of the priority encoder 230 determines the number of shifts that the group shifter 206 must perform so that it can effectively perform the specified shifts while it is in progress.

The outputs 232 of the group shifter 206 are connected to the other input of the multiplexer 214 and to the bidirectional connector (A) 212 of the register file 200 for storage and subsequent delivery to the multiplier 202 or the arithmetic logic unit 204, when required by the program in progress. The outputs 234 of the priority encoder 230 are connected to the inputs of a Q register 236 and to one of two inputs of a multiplexer 238, outputs 240 of which are connected to a bidirectional connection (C) 210 of the register file 200 and to the other input of the multiplexer 218. This arrangement of the input and output terminals of the multiplexer 238 and the presence of the Q register236 and the multiplexer 214 allows the execution of floating block arithmetic or data processed by the arithmetic unit 46.

The design of the arithmetic unit 46 includes a parallel multiplier 202 and an arithmetic logic unit 204 because many digital signal processing algorithms in test and measurement systems are based on the multiply and accumulate operation. The register file 202 also includes the accumulators for the multiply and accumulate instruction. The output of the multiplier 202 can be shifted to the left for fractional arithmetic or to the right for overflow avoidance by subsequent execution of multiply accumulation instructions. The group shifter 206 is useful for scaling data and supporting the floating point block calculation mode of the processor. The arithmetic unit 46 sets or resets appropriate flags after an instruction has been executed. Floating point block mode automatically provides the type scaling required by an algorithm designer for dynamic range enlargement, but performs the scaling only when made necessary by the size of the data. The arithmetic unit 46 also includes a hard-ware realized non-redo partial algorithm.

During the time that the arithmetic unit 46 is operating on the data read from the register file 200, a new data point stored in the memory 50 is read into the register file 200 and the result generated during the immediately preceding instruction cycle is stored from the> register file 200 to the memory 52 read. The operation therefore becomes a transfer of raw or processed data between memories 50 and 52 during a single instruction cycle.

The operation of the arithmetic unit 46 during a single instruction cycle can be summarized by the following three expressions: GR [ra] ^ - GR [ra3 * GRtr ^], which indicates one of several arithmetic calculations or logic functions consecutively during the immediately preceding instruction cycle read from memory 52; GR1 rM1 -1 DM1 £ addr13 'which indicates a reading in the register file 200 of a data stored in an address location of the memory 50; and DM2 [addr2] «- GRErm2 ^ t indicating storing the contents of a register file 200 in a location of the memory 52.

The addresses for the memories 50 and 52 and the loop controllers of the instruction fetch unit 42 calculated by the address generators of the address calculation unit 44 facilitate the data transfer function. The register file 200 not only facilitates interaction with the data memories 50 and 52, but also allows the execution of a multiply accumulate shift operation.

Claims (5)

1. A method of accessing and processing operands for pipelining generating an output result upon termination of each of successive instruction cycles in a data signal processor, comprising an instruction fetch unit, an address calculator, and an arithmetic unit comprising operating in parallel and with data communication, the instruction fetching unit providing instructions to the computing unit for supplying pre-stored operands to the computing unit in accordance with a predetermined algorithm, comprising: accessing a plurality of data memories stored operands, the approximation taking place during a single instruction cycle in response to an instruction obtained by the instruction fetch unit; and delivering the operands during the single instruction cycle to an arithmetic unit adapted to perform arithmetic operations and / or logic functions to generate and store a result and to supply an output bus with a result generated during a previous instruction cycle. Method according to claim 1, characterized in that the data memories are arranged externally of the instruction fetching unit, dead address calculation unit and the arithmetic unit. Method according to claim 1, characterized in that the arithmetic operations and the logic functions that the arithmetic unit can perform in the single instruction cycle comprise multiplication, accumulation and shifting. Method according to claim 1, characterized in that the arithmetic unit comprises a multi-port storage register, a multi-bit parallel multiplier, an arithmetic logic unit and a group shifter (barrel shifter), the input and output terminals of which are connected together for longitudinal appropriate internal data paths lead from open edges provided by the data memories and for storing the result in accordance with the instruction obtained by the instruction fetch unit. A method according to claim 4, characterized by: storing a result generated during an instruction cycle in a multi-port storage register; and supplying the result to the multiplier for processing with an operand received during the next instruction cycle for calculating an output result in accordance with an iterative processing algorithm.