JPH01310444A - Parallel arithmetic processor - Google Patents

Abstract

PURPOSE:To attains the high speed of processing by copying with a task such that branching conditions occurring during execution of the parallel arithmetic operation of plural computing elements are different between plural computing elements to each other. CONSTITUTION:A command stored in a program memory 2 is successively read by an address signal from a counter 1 for preparing an address. The read command is supplied and processed to respective corresponding plural computing elements P1, P2...Pn. These computing elements P1, P2...Pn judge whether or not the branching conditions specified to the condition branching instructions outputted from a program memory are satisfied. It is determined which computing element is stopped or operated by the branching conditions.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a parallel processing device.

[Conventional technology]

In conventional parallel arithmetic processing devices, it is not possible to react when branch conditions occur between multiple arithmetic units while executing parallel arithmetic operations of multiple Ω operators. Ta. Therefore, the present invention provides a novel parallel arithmetic processing device that can respond to different branch conditions among a plurality of arithmetic units during the execution of parallel arithmetic operations of the plurality of arithmetic units. 1! ! This is something to be concerned about.

[Embodiment 1] Next, an embodiment of a parallel arithmetic processing device according to the present invention will be described with reference to FIGS. 1 to 7. In the parallel processing device according to the present invention shown in FIGS. 1 to 7, the program counter 1 and the address output output from the program counter 1 are , a program memory 2 that sequentially outputs scheduled addresses and instructions each time they are obtained, and a plurality of n units (hereinafter, for simplicity, , n=4) computing units P ~ P
4. However, 1. The computing units P to P4 are configured as follows so that the following processing is performed. For the sake of simplicity, the addresses <A>, CB for a series of processing from the program memory 2 to [A], CB], . 〉・・・・・・
...<K>, instructions A, B...K are output, and the conditional branch address <3r-Q
＞, < B r −1> =・・−・−・＜ B
r -4> (!:, conditional branch instruction Br-1>...
...Br-4 shall be output. Further, as shown in FIG.
B], [C] and [D] are sequentially processed, and the processing unit P2
sequentially processes [△], [B], [F] and [HF, and arithmetic units P3 and F4 both process [A], [I] and [
K] processing is performed sequentially. ■ First, address <A> is output from the program counter. At this time, stop flag memories HM, I-IM2, HM3
and the stop flag HF' stored in HM4,
HF, HF3 and l-IF4 are all "0" in binary representation. In addition, the end flag memory EM,
The end flags EF, EF2, EF3, and EF4 stored in EM, EM3, and EM are also "0" in binary representation. Therefore, the clock pulse CL from the clock pulse generation circuit 3 is transmitted to the gate circuits H01, 11G, HO3 and 1.
Since the signal is supplied to the computing units P 1 , P 2 , P 2 and F4 through -IO2, all of the computing units P -F4 sequentially process [AI]. At this time, the program counter is incremented by "1". ■ If the program counter 1 operates as described above and outputs the conditional branch command Br-0, all the arithmetic units P-F4 will judge whether or not they satisfy the branch condition; If the branch condition is satisfied, the stop flag F is output as "1", and if not, the stop flag F is output as "0". Therefore, the arithmetic units P1 and F2 are set to stop flags F1 and F2.
2 is output as rOJ, and the arithmetic units P3 and P output the stop flag "3" and F4 as "1". These stop flags F
, F2, F and F4 are respectively stop flag memories HM.
, HM , HM and 8M4 OR circuit 0R1
, OR2, OR and OR4. On the other hand, the outputs of the stop flag memories HM, HM2, 1-(M3 and IM4) are
1G3 and HO2. For this reason, the computing units P1 and F2 are in a state where they continue to perform computing operations, but the computing units P3 and F4 are in a state where their computing operations are stopped. - The branch destination address <1> specified by the conditional branch instruction Br-0 is the branch destination address storage register R and R.
It is latched to 4. (2) Next, since the contents of the program counter are incremented by "1", the address <B> is output, and the processing of [B] is sequentially executed only in the arithmetic units P1 and F2. ■ If the conditional branch instruction <3r-i> is output from the program counter 1 after the arithmetic units P and F2 have sequentially executed the processing of [B] in this way, the arithmetic units P and F2
2 determines whether it satisfies the conditional branch instruction [Br-1]. In this case, since the arithmetic unit P1 does not satisfy the branch condition, it does not output the stop flag F1 as "1", but since the arithmetic unit P2 satisfies the branch condition, it outputs the stop flag F2 as "1". Therefore, the clock pulse CL is no longer supplied to the arithmetic unit P2, and the arithmetic unit P2 is stopped. Also, at this time, as in the case described above, the branch destination address <l''> is latched in the branch destination address storage register R2.At the same time, the contents of the program counter 1 are incremented by "1". be done. Therefore, only the computing unit P1 sequentially executes the process [C]. ■ Next, from program counter 1, conditional branch instruction <
3r-2> is output, the arithmetic unit P1 determines whether or not it satisfies the branch condition specified in the conditional branch instruction Br-2. In this case, since the arithmetic unit P1 does not satisfy the branch condition, it does not output the stop flag F1 as "1", and therefore the arithmetic unit P1
does not become stopped. Further, the contents of the program counter 1 are incremented by "1", and the arithmetic unit P1 executes the process [D]. After operating as above, from program memory 2,
Since the instruction specified in the instruction is output, it is detected by the end detection 3D1, and it is stored in the end flag memory E.
It is stored in M1. Therefore, the stop flag memory HM1 is connected to the gate circuit EG.
, is reset through . At this time, based on the output of the exclusive OR circuit EX2,
The branch destination address register R2 corresponding to the arithmetic unit P2 is selected through the gate circuits RG2 and RG', and the branch destination address <F> is written into the program counter, and at the same time, the coincidence circuit CI2 selects the branch destination address register R2.
A match is made between the branch destination address F> from the gate circuit RG' and the branch destination address F> from the branch address storage register R2, and the stop flag memory HM2 is reset by the output thereof. In this case, exclusive OR circuits EX1 to EX4 and gate circuits RG to RG4 and RG' constitute a priority circuit. Further, the coincidence circuit CI-C14 is composed of exclusive OR circuits REX, the number of which corresponds to the number of bits of the branch destination address, and an AND circuit AU. Since the stop flag memory HM2 is reset, the processing of [F] is started in the arithmetic unit P2. ■ Next, a conditional branch instruction is sent from the program counter.
3r-3> is output, so the arithmetic unit P2 determines whether the branch condition is satisfied. In this case, since the arithmetic unit P2 satisfies the branch condition, the stop flag memory HM2 is set, and the branch destination address specified in the branch instruction <3r-3> is latched in the branch destination address storage register R2. be done. (2) Next, the above-mentioned priority circuit selects the branch destination address register R2 corresponding to the arithmetic unit P, and writes the branch destination address <H> to the program counter. At this time, the stop flag memory HM2 sets the stop flag to "1".
”, and only the arithmetic unit P2 becomes operational. (2) Subsequently, the P14 calculator P2 sequentially executes the process [1→], and when it is completed, the end flag memory EM,2 stores the end flag as "1" and enters the lζ state. Therefore, the program counter shows the branch destination address <
I> is written, while the matching circuits CI3 and C
The stop flag memories HM and HM4 are reset by the output from I4, and the processing of [11] is sequentially executed in the arithmetic units P3 and P4. ■ In this way, [1
] are sequentially executed, a conditional branch instruction <3r-4> is output from the program counter 1, and the processors P and P4 determine whether or not they satisfy the branch condition. In this case, since the arithmetic units P and P4 satisfy the branch condition, the stop flags in the stop flag memories P3 and P4 become "1", and the branch destination address storage registers P3 and P4 store the branch destination address <K. > is latched. Further, the above-mentioned priority circuit selects the branch destination address storage register R3, and the branch destination address <K> is
On the other hand, the outputs from the above-mentioned coincidence circuits CI3 and C14 reset the stop flag memo 'J HM 3 and 11M4, so that in the nasal performers P3 and P4, the processing of [K] are executed sequentially. [Stock] Next, when an end command is detected, the end flag memories EM3 and 1M4 are set, and both end flags are stored as "1", and the stop flag memories HM1 to 1-IM4 are reset. Then, the end flag memories EM1 to EM4 and branch destination address storage registers R1 to R4 are reset, the jump destination address is written to the program counter 1, and the program returns to its original state. As is clear from the above, according to the parallel arithmetic processing device according to the present invention, while the plurality of arithmetic units P1 to P4 are executing parallel arithmetic operations, different conditions are applied between the plurality of arithmetic units P1 to P4. Even if a branch occurs, it can be easily executed. Embodiment 2 FIG. 3 is a circuit configuration diagram showing a second embodiment of a sequencer using the conditional branch control method for parallel arithmetic units of the present invention. In this embodiment, a group of flags indicating an arithmetic unit that is in a stopped state at that time when a branch condition is satisfied and a branch destination address are combined and stored in the branch destination storage section. When the end of the previously executed routine is detected, the flag group and the branch destination address are read from the branch destination storage section, and the arithmetic unit 13 is in a stopped state at the time when the flag group and the branch destination address are written. is activated and processing starts from the branch destination address. Note that, unlike the first embodiment, the branch destination storage unit has a one-to-one relationship with the PE.
There is no need to correspond to (, in this example, F I F O (
The stack 18 has a structure (Fast In La5t Out: data written from #li is read first). Similar to the first embodiment, a case where the processor shown in FIG. 2A performs the conditional branching process shown in FIG. 2B will be described below. 11. ALT-FLAG indicates the status of the stop flag, stack 18, and program counter 19. Here, 118 LT-FLAG is HALT FLAG
This flag is written in the REGISTER and causes the arithmetic unit 13 to be stopped through the operator stop circuit 12. The stop flag is written in the stop flag storage unit 15, and is set to stop when the branch condition is satisfied. This is a flag indicating the arithmetic unit that has changed. Also, as in the first embodiment, IIALT-FLAG and stop flag are PE01PE1, PE2, P
Make a set of four flags corresponding to E3, and set each flag to IIA.
LT-CODE is called a stop code. First, (1) the start address <A> of routine A is written into the program counter 19; At this time, II A L T
-COD E is “oooo”, stack pointer 1
7 indicates address 0, the contents of the stack are stop code "0000", and the branch destination address is don't care. Therefore, routine A is executed for all of P'E O to PEa. At this time, the program counter 19 is incremented by 7 from A>. ■ When the program counter 19 reaches <3rQ>, P
Each of the arithmetic units EO to 3 tests the condition written in the conditional branch instruction and outputs the status. If the status is O, the branch is not branched, and if the status is 1, the branch is branched. Depending on the status of the PE that is not in the stopped state, the branch instruction detection unit 2°1 executes one of the following three processes. 1 The status of all PEs is O. The program counter 19 is incremented. 2 Status of all PEs is 1 Jump to the branch destination using the contents of the program counter 19 as the branch destination address specified in the conditional branch instruction. 3 O and 1 exist in the status ■ Increment the stack pointer 17 by 1 i ~, and store the stop flag in the stack 18 with only the PE that is not in the stopped state and whose status is 1, set the stop flag to 1, and set the rest to O Write in section 15. At the same time, the branch destination address is written into the branch destination address storage section 16. In addition, the PE whose status is 1 is newly ORed with HALT-FLAG without indicating the PE that was in the stopped state, and 118L
Write to T FLAG IIEGISTIER11. (2) Thereafter, the program counter 19 is incremented by 1, and only the PE that outputs the status O executes the process. Only the PE that outputs the status O executes processing. That is, in the example of FIG. 2B, since PEO and PE1 output status O, PE2 outputs status 1, and PE3 outputs status 1, the branch instruction detection unit 21 sets ]1^Lj-CODE to '0.
At the same time, the address of the stack pointer 17 is set to 1, and the stop code '0011' and the branch destination address <1> specified in the conditional branch instruction BrO are stored in the stop flag storage unit 15 and the branch destination address storage unit 16, respectively. In and out. (2) Next, the program counter 19 is incremented by 1, and processing of routine B is started. At this time, PEO and PEI are in operation. When routine B ends and the program counter 19 becomes <Br1>, PEO and PE1 test the condition written in the conditional branch instruction, and as a result, PEO outputs status 0 and PE1 outputs status 1, so the branch is executed. The instruction detection unit 21 sets the 118 LT-CODE to "0111" as before, and at the same time sets the address of the stack pointer 17 to 2, and reads the stop code "'0100" and the branch destination address specified in the conditional branch instruction Br1. > are written in the stop flag storage unit 15 and branch destination address storage unit 16, respectively. ■ Next, the program counter 19 is incremented by 1, and execution of the processing of routine C is started. At this time, only PEO is in the operating state. ■ When the program counter 19 becomes <3r2>, P
As a result of testing the condition written in the conditional branch instruction at EO, the status 0 is output, so the branch instruction detection unit 21 increments the program counter 19 by 1, and the processing of routine D starts. will be started. ■ At the end of Routine Do, an instruction indicating the end of the conditional branch routine is specified, so the end instruction detection unit 14 detects that instruction and executes one of the following two processes depending on the stack state. . 1 This means that the stacked PE with no data has completed the conditional branch processing, and the HALT FLAG I? EGISTER1
1, jumps to the address specified in the end command, and starts executing a new process. 2 Read the stop flag from the stacked data stack 18, invert it, set it as a new HALT-FLAG, and set it to +1
Enter ALT FLAG REGISTER11. At the same time, the branch destination address is read from the stack 18, and is entered into the program counter 19, and processing is started from the branch destination address. Stack pointer 17 is decremented by code. In other words, in this case, the address of stack pointer 17 is 2, so the stop code "0100" is inverted.
1oit" becomes the new 118 LT-FLAG and HA
At the same time, the branch destination address <F> is updated to program counter 1.
9, and processing of routine F is started. At this time, only PE1 is in the 0 operating state. When the program counter 19 becomes <Br3>, PE1
tests the condition written in the conditional branch instruction, and as a result,
Since the status 1 is output, the branch instruction detection unit 21 sets the contents of the program counter 19 to the branch destination address specified in the conditional branch instruction 1>, and processing of the routine 1 is started. Since the instruction indicating the end of the conditional branch routine is specified in 241 of ``Routine 1'', the end instruction detection unit 14 detects that instruction, and when the stack pointer 17 is checked, the address is 1, so the same as last time. Then, the stop code "0011" and the reversed "1100" are the new 11.
8LT-FLAG, the branch destination address <(> is entered into the program counter 19, and processing of routine I is started. At this time, PE2 and PE3 are in the operating state. The program counter 19 is <3r4 ＞, PE2
The condition written in the conditional branch instruction is tested in PE3, and as a result, status 1 is output in both PE2 and PES, so the branch instruction detection unit 21 converts the contents of the program counter 19 into a branch specified in the conditional branch instruction. Destination address <K>
Then, routine K is executed. Since an instruction indicating the end of the conditional branch routine is specified at the end of the routine, the end instruction detection section 14 detects this instruction and checks the address of the stack pointer 17. ■ As a result, there is no data on the stack this time, so IIALT FLAG ItEGIST "R11
, jumps to the address specified in the end instruction, and starts executing a new process.

[Brief explanation of the drawing]

1 to 9 are diagrams for explaining a first embodiment of a parallel arithmetic processing device according to the present invention. FIGS. 10 and 11 are diagrams for explaining a second embodiment of the parallel arithmetic processing device according to the present invention. Applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Scope of Claims] A command address generation counter, and a command that sequentially outputs scheduled commands each time the command address generation count output is obtained, based on the command address generation count output output from the command address generation counter. a generating circuit; and a plurality of n arithmetic units P_1, P_2 that each perform an arithmetic operation based on the frame each time the command is output based on the command output from the command generating circuit.
......P_n, in which the arithmetic unit P_i (i=1, 2......n) executes a conditional branch instruction output from the program memory based on the output from the program counter. It is determined whether or not the branch condition specified in
1. A parallel arithmetic processing device characterized by having means for placing the unit into an operating state or a stopped state.