JP2719676B2 - Parallel processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

 The present invention relates to a parallel processing device.

[Prior art]

The conventional parallel operation processing device has a drawback that if a plurality of operation units have different branching conditions during execution of the parallel operation operation of the plurality of operation units, it cannot respond to this. Was. Therefore, the present invention provides a novel parallel operation processing that can cope with a case where a plurality of operation units have different branch conditions during the execution of the parallel operation operation of the plurality of operation units. The device is not proposed.

Embodiment 1 Next, an embodiment of a parallel processing device according to the present invention will be described with reference to FIGS. The parallel processing device according to the present invention shown in FIGS. 1 to 7 has a program counter 1 (FIG. 7) and a program counter 1 as in the case of the conventional parallel processing device.
And a program memory 2 (FIG. 7) for sequentially outputting scheduled addresses and instructions, and an instruction output from the program memory 2 each time it is obtained. It has a plurality of n arithmetic units P _{1 to} P ₄ (FIG. 4) (each of which is hereinafter referred to as n = 4 for simplicity) for executing arithmetic operations. Here, the computing unit P ₁ to P _4, as described below processing is performed, is configured as described below. That is, for simplicity, [A], [B]... [K] from the program memory 2 as shown in FIG.
<A>, <B> for a series of processing of
<K> and instructions A, B... K are output, and conditional branch addresses <Br-0>, <Br-1>.
<Br-4> and conditional branch instructions Br-0, Br-1,... Br
Shall -4 and is output, also as shown in FIG. 9, the computing unit P ₁ is [A], sequentially performs processing [B], [C] and [D], the calculator P ₂ Describes that the processes of [A], [B], [F] and [H] are sequentially performed, and that the arithmetic units P ₃ and P ₄ sequentially perform the processes of [A], [I] and [K]. It is as follows. First, the program counter 1 (FIG. 7)
As shown in the figure, an address <A> for the process [A] is output. At this time, the stop flag memory HM _1, HM _2, HM ₃ and HM
₄ The stop flags F ₁ and F stored in FIG.
_2, F ₃ and F _4, as shown in FIG. 8, a "0" in both the binary display. In addition, termination flag memory EM _1, EM _2, EM
₃ and EM ₄ (FIG. 3) end flags EF ₁ , E
As shown in FIG. 8, F ₂ , EF _3, and EF ₄ are both binary display “0”. Therefore, the clock pulse CL from the clock pulse generation circuit 3 (FIG. 7) is applied to the gate circuits HG ₁ , HG ₂ , HG ₃ and H
Through G ₄ (FIG. 4), arithmetic units P ₁ , P ₂ , P ₃ and
Are supplied to P _4, therefore, all of the arithmetic unit P ₁ to P ₄ performs a process of [A]. At this time, the content of the program counter 1 is incremented by “1”. Next, the program counter 1 determines that the conditional branch instruction Br-
If 0 is output, the arithmetic unit P ₁ (i = 1, 2, 3, 4)
Itself determines whether or not to satisfy a branch condition, If it is determined that satisfies the branch condition, and outputs a stop flag F ₁ to "1" in the binary display, whereas if the judgment is satisfied, the stop flag the F ₁ to output "0" of the binary display. Therefore, the arithmetic unit
The P ₁ and P ₂ are respectively stopped flag F ₁ and F ₂ is output in "0" in the binary display, stop calculator P ₃ and P ₄ are each flag
F ₃ and F ₄ to output "1" of the binary display. In this way, the stop flags F ₁ , F ₂ , F _3, and F ₄ output from the arithmetic units P ₁ , P ₂ , P _3, and P ₄ are OR circuits OR ₁ , OR ₂ , OR _3, and OR _{4, respectively.} through (FIG. 4), as shown in FIG. 8, the stop flag memory HM _1, HM _2, HM ₃ and HM
₄ (FIG. 4). On the other hand, the stop flags F ₁ , F ₂ , F ₃ and F ₄ stored in the stop flag memories HM ₁ , HM ₂ , HM ₃ and HM _{4 correspond} to the gate circuit.
HG _1, are supplied to the HG _2, HG ₃ and HG _4. Thus, the clock pulse CL from a clock pulse generating circuit 3, the arithmetic unit P ₁ and the gate circuits HG ₁ and HG ₃ to P ₂
Are supplied to the computing units P ₃ and P ₄ , respectively.Therefore, the computing units P ₁ and P ₂ are in a state of continuing the computing operation, and the computing units P ₃ and P ₄ , The arithmetic operation stops. At this time, the arithmetic units P ₃ and P _4, the conditional branch instruction
Branch address Br-0 is specified <I> is the branch target address storing register R ₃ and R ₄ (FIG. 2), as shown in FIG. 8, it is latched. Next, the program counter 1 sets the content to “1”.
Then, the address <B> is output as shown in FIG. Therefore, only the calculator P ₁ and P ₂ executes a process [B]. Then, after the end and executes the processing of the arithmetic unit P ₁ and P ₂ [B], the program counter 1, the conditional branch instruction Br-1
, The arithmetic units P ₁ and P _{2 use} their own conditional branch instructions.
It is determined whether Br-1 is satisfied. In this case, the arithmetic unit
P _1, because is not determined that satisfies the branch condition, but does not output the stop flag F ₁ to "1", the arithmetic unit P _2, since it is determined that satisfies the branch condition, a stop flag F ₂ is "1" Output. Therefore, the arithmetic unit P _2, a clock pulse generating circuit 3
Clock pulse CL is not supplied from
Calculator P ₂ is stopped. At this time, the arithmetic unit P _2, the branch destination address <F> is, the branch target address storing register R _2, as shown in FIG. 8, is latched. Next, the program counter 1 increments the content by “1” and outputs the address <C>. Therefore, only the operation unit P ₁ executes the process of [C]. Next, from the program counter 1, the conditional branch instruction Br
If −2 is output, the arithmetic unit P ₁ itself is a conditional branch instruction.
It is determined whether the branch condition specified in Br-2 is satisfied. In this case, the arithmetic unit P _1, since it is determined not to satisfy the branch condition, does not output the stop flag F ₁ to "1". Therefore, the arithmetic unit P ₁ is not in a stopped state. At this time, the program counter 1 increments its content by "1" and outputs the address <D>. Therefore, the arithmetic unit P ₁ executes processing of [D]. After operating as described above, an end instruction specified in the instruction D is output from the program memory 2. And the end (end) instruction is the end detector D ₁
Is detected by (FIG. 3), the detection output is as shown in FIG. 8, the end flag memory EM _1, stored displayed binary "1". Therefore, the stop flag memory HM _1, through the gate circuits EG _1, is reset to the contents of "1" in the binary display. At this time, based on the output of the exclusive OR circuit EX ₂ (FIG. 2), the operation unit P is output through the gate circuit RG ₂ (FIG. 2).
_{2. The} branch destination address storage register R ₂ (FIG. 2) corresponding to ₂ is selected and the branch destination address storage register R ₂ is selected.
The branch destination address <F> from R ₂ is written into the program counter 1 (FIG. 7), and at the same time, the coincidence circuit CI ₂ (FIG. 5) changes the branch destination from the gate circuit RG ′. The address <F> is matched with the branch destination address <F> from the branch destination address storage register R ₂ , and the output is sent to the stop flag memory HM ₂ (FIG. 4) through the gate circuit EG ₁ . Reset to the contents of "0" in binary display. here,
An exclusive OR circuit EX ₁ ~EX _4, and a gate circuit RG ₁ ~RG ₄ and RG 'constitute a priority circuit. Also, the matching circuit CI
_{1 to} CI ₄ are composed of exclusive OR circuits REX of a number corresponding to the number of bits of the branch destination address, and AND circuits AND. Stop flag memory HM _2, as described above, if it is reset to the content of "0" in the binary display, the calculator P _2, starts the process of [F]. Then, from the program counter 1, a conditional branch instruction
If br-3 is output, the arithmetic unit P ₂ determines whether satisfies the branch condition. In this case, the arithmetic unit P _2, since it is determined that satisfies the branch condition, as shown in FIG. 8, is set to the contents of "1" in the stop flag memory HM ₂ are binary display, also, the branch destination address in the storage register R _2, the branch destination address specified in the conditional branch instruction Br-3 <H> is latched. Then, by the above-described preference circuit, the branch destination address storage register R ₂ corresponding to the arithmetic unit P ₂ is selected, its branch address branch destination address from the storage register R ₂ <H>, the program counter 1 Is written to. At this time, is ready for the stop flag memory HM ₂ storing stop flag F ₂ is "1", only the operation unit P ₂ is operational. Subsequently, the computing unit P ₂ executes the process of [H], if the processing is finished for the [H], a state where the end flag memory EM ₂ stores an end flag "1". For this reason, the branch destination address <I> is written into the program counter 1, while the matching circuits CI ₃ and CI ₄ described above are written.
From the stop flag memories HM ₃ and HM ₄
It resets the contents of the "0" value display, calculator P ₃ and P ₄
Performs the process [I]. In this manner, the arithmetic unit P ₃ and P ₄ are After completion executes the processes of [I], a conditional branch instruction from the program counter 1
Br-4 is output, the arithmetic unit P ₃ and P ₄ are themselves determines whether satisfies the branch condition. In this case, the operator P ₃ and
Since P ₄ is determined to satisfy the branch condition, a stop flag F ₃ and F ₄ of the stop flag memory HM ₃ and HM _4, are "1"
Becomes, the branch target address storing register R ₃ and R _4, the branch destination address <K> is latched. Further, by the above-described preference circuit, the branch target address storing register R ₃ is selected, the branch target address from branch target address storing register R ₃ <K> is written into the program counter 1, whereas, above the output from the matching circuit CI ₃ and CI ₄ was, the stop flag memory HM ₃ and HM ₄
Is reset to the content of "1" in the binary display,
Calculator P ₃ and P ₄ executes the processing of the [K]. Then, if terminated (end) instruction is detected by the end detecting device D ₃ and D _4, it is set to the contents of "1" in the completion flag memory EM ₃ and EM ₄ are both binary display, together end flag ready stored at "1" in the binary display, also, resets the stop flag memory HM ₁ ~HM ₄ is the contents of "1" in the binary display, end flag memory EM ₁ ~EM _4, and the branch destination address storing register R ₁ to R ₄ is reset and returns to the original state. As apparent from the above, according to the parallel processing apparatus according to the present invention, during execution of a parallel arithmetic operation by a plurality of computing units P ₁ to P _4, between a plurality of computing units P ₁ to P _4, Even if mutually different conditional branches occur, it can be easily executed.

Second Embodiment Next, a second embodiment of the parallel processing device of the present invention will be described with reference to FIGS. 10 and 11. In the second embodiment of the parallel arithmetic processing device according to the present invention, a stop flag group indicating the operation unit 13 that has stopped at the time when the branch condition is satisfied, and a branch destination address are combined. Write to the branch destination address storage unit 16. When the end of the previously executed process (routine) is detected, the flag group and the branch destination address are read out from the branch destination address storage unit 16 and the flag group and the branch destination address are written at the point of time. Computing unit 13 stopped
Is activated, and processing is started according to the branch destination address. In the case of the second embodiment of the parallel operation processing device according to the present invention, the branch destination address storage registers R _{1 to} R ₄ have the branch destination address storage unit 16 and have a FILO (Fast In Last Out:
The stack 18 has a structure in which data written later is read first). Hereinafter, as in the case of the first embodiment, the case where the conditional branch processing shown in FIG. 9 is performed will be described. FIG. 11 shows the states of the stop flag register 11, the stack 18, and the program counter 19. The stop flag written in the stop flag register 11 is a flag for putting the arithmetic unit 13 into the stop state through the arithmetic unit stop gate circuit 12, and the stop flag written in the stop flag storage unit 15 of the stack 18. The flag is a flag indicating an arithmetic unit that has been stopped due to satisfaction of the branch condition. Note that computing units P ₁ , P ₂ , P ₃ ,
The sequences of the respective corresponding stop flag to P _4, referred to as a stop code. First, as shown in FIG. 11, an address <A> for the process (A) of [A] is output from the program counter 19. At this time, as shown in FIG. 11, the stop flag register
The stop code stored in 11 has the content of “0000”, and the stack pointer 17 of the stack 18 has the address “0”.
The stop code stored in the stop flag storage unit 15 of the stack 18 has the content “0000”, and the branch destination address stored in the branch destination address storage unit 16 is “don't care”. Therefore, the computing units P _{1 to} P ₄ constituting the computing unit 13 are:
In both cases, the process (routine) of [A] is executed. At this time, the program counter 19 increments by “1”. The program counter 19 sets the condition branch address <Br−
If outputs O>, calculator P ₁ to P ₄ tests the condition noted in the conditional branch instruction, and outputs the status. If the status is "0", it is determined to be unbranched, and if the status is "1", it is determined to be a branch,
The branch instruction detection unit 21 causes any of the following three processes to be executed according to the status of the arithmetic unit that is not in the halt state. (1) When the statuses of all the arithmetic units are "0" The program counter 19 is incremented by one. (2) When the status of all the arithmetic units is "1" The content of the program counter 19 is set to the branch destination address specified in the conditional branch instruction, and the program jumps to the branch destination. (3) The status of a certain arithmetic unit among all the arithmetic units is “0”,
When the status of other operation units is "1" The stack pointer 17 is incremented by "1",
For a computing unit that is not in a stopped state and has a status of “1”, the stop flag is set to “1”, and for the remaining computing units having a status of “0”, the stop flag is set to “0”
These stop flags are stored in the stop flag storage unit in the stack 18.
Write to 15. At the same time, the branch destination address is written into the branch destination address storage unit 16. In addition, in order to newly set the arithmetic unit having the status "1" to a stopped state, the logical sum of the status and a stop flag indicating the arithmetic unit which has been stopped so far is taken, and the logical sum output is stopped. Write to the flag memory 11. After that, the program counter 19 is incremented by “1”, and
Only the arithmetic unit that outputs the status “0” executes the processing. That is, in the example shown in FIG. 9, the computing unit P ₁ and P ₂ outputs the status in the "0", and since calculator P ₃ and P ₄ outputs the status in the "1", the branch instruction Detector 21
Sets the stop code to “0011”, sets the address of the stack pointer 17 to “1”, and sets the stop code to “001”.
1 "and the branch destination address <I> specified in the conditional branch instruction Br-0 are written into the stop flag storage unit 15 and the branch destination address storage unit 16, respectively. Next, the program counter 19 is set to" 1 ". And the process (routine) of [B] is started. At this time, the arithmetic unit P ₁ and P ₂ are actuated state. [B] a process (routine) is terminated, if the output of the program counter 19 is a conditional branch address <Br-1>, calculator P ₁ and P _2, to test the conditions noted in the conditional branch instruction, As a result, the arithmetic unit P ₁ outputs the status in the "0", arithmetic unit P ₂ outputs a status "1". Therefore, the branch instruction detecting unit 21 sets the stop code to “0111” and simultaneously sets the stack pointer 17
And the stop code “0100” and the branch destination address <F> specified in the conditional branch instruction Br-1 are
Stop flag storage unit 15 and branch destination address storage unit 16 respectively
To be written. Next, the program counter 19 is incremented by "1", and the execution of the process (routine) of [C] is started. At this time, only the operation unit P ₁ is operational. When the execution of the process [C] is completed, the program counter
If 19 outputs the conditional branch address <Br-2>, to test the described conditions in the conditional branch instruction in the arithmetic unit P _1,
As a result, the arithmetic unit P _1, since outputs the status "0", the branch instruction detection unit 21, the program counter 19 is incremented by "1", to start the process of [D] (routine). At the end of the processing (routine) of [D], an instruction indicating the end of the conditional branch routine is specified, so the end instruction detecting unit 14 detects the instruction and stacks the instruction.
One of the following two processes is executed according to the state of 18. (1) When there is no stacked data Assuming that all the arithmetic units have completed the conditional branch processing, reset the stop flag register 11, jump to the address specified in the end instruction, and perform new processing. Start execution. (2) When Stacked Data Exists The stop flag is read from the stop flag storage unit 15 of the stack 18, inverted, made a new stop flag, and written into the stop flag register 11. At the same time, the branch destination address is read from the branch destination address storage unit 16 of the stack 18 and is written to the program counter 19, thereby starting the processing from the branch destination address. Further, the stack pointer 17 is decremented by "1". That is, since the address of the stack pointer 17 is “2”, the stop code “0100” is inverted to “101”.
1 "as a new stop flag, the stop flag register 11
At the same time, the branch destination address <F> is written into the program counter 19, and [F]
(Routine) is started. Only calculator P ₂ this time is the operating state. The program counter 19 sets the conditional branch address <Br−
If output 3>, to test the described conditions in the conditional branch instruction in the arithmetic unit P _2, resulting arithmetic unit P ₂ outputs the status "1". For this reason, the branch instruction detecting unit 21 sets the contents of the program counter 19 to the branch destination address <H> specified in the conditional branch instruction, and performs the processing of [H] (routine).
To start. At the end of the process (routine) of [H], an instruction indicating the end of the conditional branch routine is specified, so the end instruction detecting unit 14 detects the instruction. Since the address is “1”, the stop code “0011” is inverted to “110” as in the previous case.
0 "becomes the new stop flag, the branch destination address <I> is written into the program counter 19, the processing (routine) is started. At this time calculator P ₃ and P ₄ are operational state of [I] The program counter 19 determines that the conditional branch address <Br−
If outputs 4>, the arithmetic unit P ₃ and P _4, and test conditions noted in the conditional branch instruction, so that the arithmetic unit P ₃ and P ₄ outputs a status "1". For this reason, the branch instruction detecting unit 21 sets the contents of the program counter 19 to the branch destination address <K> specified in the conditional branch instruction, and sets [K]
(Routine) is executed. At the end of the process (routine) of [K], an instruction indicating the end of the conditional branch routine is specified, so the end instruction detecting unit 14 detects the instruction and checks the address of the stack pointer 17. As a result, since there is no data in the stack 18 this time, the stop flag register 11 is reset, jumps to the address specified in the end instruction, and starts execution of the process anew.

[Brief description of the drawings]

1 to 9 are views for explaining a first embodiment of a parallel operation processing device according to the present invention. FIGS. 10 and 11 are diagrams for explaining a second embodiment of the parallel operation processing device according to the present invention. 1 Program counter 2 Program memory 3 Clock pulse generation circuit 11 Stop flag register 12 Computing device stop gate circuit 13 Computing device 14 Completion detector 15 Stop flag storage unit 16 ...... branch destination address storage unit 17 ...... stack pointer 18 ...... stack 19 ...... program counter 20 ...... branch target address output section 21 ...... branch instruction detection unit the aND ...... aND circuit CI ₁ ~CI ₄ ...... matches Circuit D _{1 to} D ₄ … End detector EG _{1 to} EG ₄ … Gate circuit EM _{1 to} EM ₄ … End flag memory EX _{1 to} EX ₄ … Exclusive OR circuit HM _{1 to} HM ₄ … Stop Flag memory HG _{1 to} HG ₄ … Gate circuit OR _{1 to} OR ₄ … OR circuit P _{1 to} P ₄ … Calculator RG _{1 to} RG ₄ … Gate circuit R _{1 to} R ₄ … for branch destination address storage Register REX …… Exclusive OR circuit

Continuing on the front page (72) Inventor Shigeken Hamaguchi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Hiroki Yamauchi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Stock Inside the company (72) Inventor Yutaka Suzuki 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Hideo Kuroda 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-63-106859 (JP, A) JP-A-61-246868 (JP, A)

Claims (1)

(57) [Claims] 1. A program counter for outputting an address, and each time the address is obtained from the program counter, one of a processing instruction and a conditional branch instruction specifying a branch address is provided. A program memory to be output, and a process based on an instruction for a process output from the program memory, respectively, and based on a conditional branch instruction output from the program memory, a branch condition specified in the instruction itself is written. Each of the arithmetic units is controlled from the operating state to the stopped state, and only a part of the plurality of arithmetic units is changed from the operating state to the stopped state. When the controlled state is reached, the branch destination address storage means for storing the branch destination address specified in the conditional branch instruction. The branch destination address stored in the branch destination address storage means is output from the program memory based on the address from the program counter by an arithmetic unit which is not controlled to be in a stopped state among the plurality of arithmetic units. Means for writing, after executing a process based on an instruction for a series of processes, the program counter as the address to be output to the program memory, a parallel arithmetic processing device.