JPH02287624A - Data processor - Google Patents

Abstract

PURPOSE:To execute the multi-direction branch at the time of processing a CASE sentence at a high speed by selecting a head address of the processing corresponding to the condition of the CASE sentence and setting it to a location counter, at the time of executing a CASE instruction. CONSTITUTION:Head addresses X0 - Xn of the respective processings which become a multi-direction branch by a CASE sentence are stored in registers 15-0 - 15-n. Also, a multi-direction branch condition N (0<=N<=n) of the CASE sentence is generated, and stored in a register 16. A selector 17 selects the register 15-N (0<=N<=n) corresponding to a value of this N. When a CASE instruction is executed in such a state, an input control part 18 selects a head address XN stored in the register 15-N selected by the selector 17, and sets it to a location counter 11. In such a way, the control is shifted to the processing for setting the address XN as a head address, and the multi-direction branch by the CASE sentence is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a data processing device that processes high-level language instructions that frequently use CASE statements.

(Prior Art) Conventionally, in a data processing device that processes a CASE statement in a high-level language as shown in FIG. 2, the CASE statement is executed as shown in the flowchart of FIG. That is, conventionally, first, each process aO that becomes a multi-directional branch (corresponding to the value of condition N 0.1...n) in a CASE statement.

al...an's start address (jump destination address) xO
, xl...xn are stored at intervals of d in a continuous area starting from address A of the main memory (step Sl). Also, N, which is a condition for a CASE statement (multidirectional branch condition), is generated (step S2). Then execute the CASE instruction as follows. First, the value of N generated in step S2 is used to calculate X-A+ (Nod) to generate address X (step S3).
. Next, the content X of the address X generated in step S3
N (start address of process aN selected by CASE statement)
is read out and set in the location counter (step S3), and control is transferred to the selected process aN.

(Problems to be Solved and Attempted by the Invention) As mentioned above, conventionally, the group of start addresses (jump destination addresses) of processes to be selected by the CASE statement are placed in the main memory, so the conditions for the CASE statement are The value of N is used to generate the main memory address where the start address of the corresponding process is located, the generated address is used to read the target start address from the main memory, and then the location counter is Since the flag was set, there was a problem in that it took a lot of time to complete the branch (processing of the CASE instruction).

Therefore, the problem to be solved by the present invention is to enable high-speed execution of the CASE instruction in the processing of the CASE statement.

[Structure of the Invention] (Means for Solving the Problems) This invention includes a plurality of eleventh noisters for holding the start addresses of each process that can be selected by a CASE statement, and a CASE statement.
A second register for holding a condition of the SE statement, and a first selection means for selecting one of the plurality of first registers according to the condition held in the second register,
The second selection means for selecting the address to be set in the location counter is set to the first selection means when executing the CASE instruction.
The present invention is characterized in that it is configured to select the output of the selection means.

(Operation) According to the above configuration, when executing a CASE statement, 1, CA
For each process that can be selected according to the value of condition N in the SE statement
(on the main memory) to the corresponding first address.
If N, which is the condition of the CASE statement, is generated and stored in the second register, the first register corresponding to the condition N stored in the second register among the plurality of first registers the register is selected by the first selection means;
When the CAS E instruction is executed in this state, the content of the first register selected by the first selection means, that is, the start address of the process directly corresponding to the condition N indicated by the second register is immediately selected by the second selection means. Since this is set in the location run counter, multi-directional branching can be performed at high speed when processing a CASE statement.

(Embodiment) FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention. The data processing device shown in FIG. 1 is a sequential processing type device that sequentially reads out a group of instructions stored in a main memory (not shown) and executes the instructions.

In FIG. 1, 11 is a register (
12 is a count-up unit that counts up the address indicated by the location counter 11 to generate the address of the instruction next to the currently executed instruction. 13 is an input signal input as an initial setting value to the location counter 11;
14 is a register for storing the branch destination address X when the conditional branch is established. 15-0.15-1...15-
Each process aQ that can be selected by the CASE statement (corresponding to possible values 0, 1...n of the condition N of the CASE statement).

al...A register for storing the start address (jump destination address, multidirectional branch destination address) xO, xi...xn of an, 16 is the condition of the CASE statement (condition of multidirectional branch) N (0≦ This is a register for storing (Nun). 17 is a selector that selects one of the registers 15-θ to 15-0 according to the condition N indicated by register 16; 18 is an input control unit that selects the address to be set in the location counter 11 next.

This input control unit 18 is configured to select the output of the selector L7 when executing the CASE instruction.

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, when input signal 13 is given, input control section 18 selects assimilated bone 13 and sets it in location counter 11 as an initial setting value.

As a result, the command on the main memory specified by the setting contents (initial setting value) of the location counter 11 is read out and executed. Next, in the normal state, the input control section 18 selects the location of the next instruction generated by the count up section 12 counting up the value indicated by the location counter 11, and sets it in the location counter 11. By repeating the above operations, the locations set in the location counter ll are sequentially counted up, and the instruction group is executed one instruction at a time. When a conditional branch is established in the process of this instruction processing, the input control unit 18 inputs a register 1 for use when the conditional branch is established.
4 is selected, and the branch destination address X stored in the same register 14 is set in the location counter 11. As a result, a branch is executed.

Now, when executing a CASE statement that is directly related to the present invention, first, each process that causes a multi-way branch in the CASE statement (corresponding to the possible values 0.1...n of the condition N of the CASE statement) Start address xO, xl of aO, al...in
...xn in register 15-0゜15-1...l 5
-n (corresponding to step Sl in FIG. 3) is performed. Further, an operation is performed to generate a condition (multidirectional branch condition) N (0≦N≦n) for a CASE statement and store it in the register 16 (corresponding to step S2 in FIG. 3). When condition N is stored in register 16, selector 17
is the register 15-N corresponding to the value of N (0≦N≦
Select n). Therefore, if the value of N stored in the register 16 is 0, the register 15-0 is stored, if it is 1, the register 15-1 is stored, and if the value is n, the register 15-n is stored.
is selected.

When the CASE instruction is executed in the above state, the input control unit 18 outputs the output of the selector 17, that is, the start address (multidirectional branch destination address) XN stored in the register l5-N selected by the selector 17. choose,
The location counter 11 is set. As a result, a process aN whose start address is XN set in the location counter 11 (if XN-xo, a process ao,
If N mxn, control is transferred to processing an) and CAS
The multi-way branch in the E statement is completed. The execution operation of the above CASE instruction corresponds to step S5 in FIG. 3, and compared to the conventional case, step S3 in FIG. Processing corresponding to S4 is no longer necessary, and the execution speed of the CASE instruction is increased accordingly.

[Effects of the Invention] As detailed above, according to the present invention, when a CASE instruction is executed, the start address of the process corresponding to the condition of the CASE statement can be immediately selected and set in the location counter. , multi-directional branching can be performed at high speed when processing a CASE statement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the structure of a CASE statement, and FIG. 3 is a flowchart for explaining conventional CASE statement processing. . 11... Location counter, 15-0 to 15-n
...Register (second register), 1B...Register (second register), 17...Selector (first selection means), 18...Input control section (second selection means). Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] In a sequential processing type data processing device that sequentially reads a group of instructions stored in a main memory and executes the instructions, a plurality of a first register, a second register for holding the conditions of the CASE statement, and a first selection means for selecting one of the plurality of first registers according to the conditions held in the second register. a location counter for holding an address of an instruction to be executed, and a second selection means for selecting an address to be set in the location counter, and the second selection means is configured to: A data processing device characterized in that the data processing device is configured to select the contents of the first register selected by the first selection means.