JPH02103630A - Data processor - Google Patents

Abstract

PURPOSE:To speed up a data processing designating plural registers with one instruction to a register group composed of plural kinds of plural general purpose registers, address registers, etc., each of which is composed of plural registers and processing instructions for storing data in a main memory device. CONSTITUTION:This data processor is constituted of an instruction control section 1, main memory device (memory) 2, alignment circuits 5 and 9, registers 6-8, 11, 12, 15...30, 39, and 40, operation register 10, selector 13, ALU (arithmetic logic unit) 14, store mask decoder 35, and adders 31...34, 36, and 38. Then plural registers of the register group composed of general purpose registers, address registers, etc., each of which is composed of plural registers are designated by one instruction and instructions for storing data in the memory 2 are performed. Therefore, processing speeds of arithmetic operations of various data sizes can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a system in which multiple registers such as general-purpose registers and address registers each specify a plurality of registers with one instruction for a register group consisting of a plurality of registers. It relates to a data processing device that processes instructions to be stored in a storage device, and in particular, a first register group and a second register group consisting of a plurality of registers that are serially numbered and occupy the same data width when stored in the memory. The present invention relates to a data processing device having a group of registers, and capable of storing data in the memory with a data width corresponding to a plurality of individual registers.

[Conventional technology]

In this type of data processing device, the pace register (Baa
A register called a general-purpose register (GensR) and a register that stores address information for specifying instruction words and data used in instructions on the main memory.
An index (I) that is mainly used with calculation data and pace register
A plurality of registers are prepared to store (ndex) information, and can be used freely by the program.

The pace registers and general-purpose registers are each assigned consecutive and independent numbers, and by specifying these numbers they can be easily used from a program, but because there is a limit to their number, they cannot be used in subroutine programs, etc. If a working register is required, the register used by the main program must be temporarily saved and restored when returning to the main program.

The instruction used at this time is the load multiple (Loa).
d Multiples instruction (hereinafter referred to as 5M instruction)
@) command (hereinafter referred to as S'IM command). And these I, M instructions and 87M instructions are 5M instructions,
The instruction format is as shown in Figure 4, which is a diagram showing the instruction word format of the 5Tyi instruction, and the operation code section OP indicates that it is a 5M instruction or an 87M instruction, and in the case of an LM instruction, the data to be loaded into the register is AD indicates the address on the main memory where it is stored, and in the case of an 87M instruction, indicates the address on the main memory where the contents of the register should be stored.
It has an H field, a pace register to load or store, Nb and Ng fields indicating the number of general-purpose registers, a pace register to need or store, and Bi and Gl fields indicating the first number of general-purpose registers. The pace registers loaded or stored by the 5M instruction and the s'rM instruction are Nb with consecutive numbers starting from the number indicated by B1, and similarly, the general-purpose registers are Ng with consecutive numbers starting from the number indicated by ci.
It is individual.

When a subroutine program is called from the main program, the contents of the pace register and general-purpose register used by the main program are saved to the main memory by the 87M instruction, and the subroutine program can then freely use these pace registers and general-purpose registers. become able to. When the subroutine program finishes processing and returns to the calling main program, the pace register and general-purpose registers that were saved to the main memory by the 87M instruction are restored to the state they were in before the subroutine program was called by the LM instruction/CL. Program processing continues.

[Problems to be Solved by the Invention] A feature of the 5M and 87M instructions is that when saving and restoring multiple registers, it is not necessary to write one register and one load instruction each, like normal load and store instructions. However, since the registers to be actually loaded or stored are not described one by one in the instruction word, the control circuit of the data processing device can easily read the first register number. Each register number must be generated from Bl, Gi and the number of registers Nb, Ng to control reading and writing of the registers.

Generally, in high-speed general-purpose data processing equipment, in order to speed up arithmetic processing of various data sizes, the data width for reading and writing to and from the main memory is made as wide as possible to increase efficiency. Normally, this data width is often twice or more than that of the pace register and general-purpose register, but the LM instruction,
In the 87M instruction, the data bus between the main storage device and the data processing device cannot be used effectively due to the complexity of controlling the load/store register numbers mentioned above.

Furthermore, in conventional data processing devices of this type, there are instructions for operations between general-purpose registers, such as adding general-purpose registers a and general-purpose register b and storing it in general-purpose register a, and it is necessary to speed up this instruction. 2 general-purpose registers for
However, there is a problem in that this function is not effectively used for the 87M instruction for the reasons mentioned above.

[Next means to solve the problem]

The data processing device of the present invention has a first register group and a second register group that are composed of a plurality of registers that are serially numbered and occupy the same data width when stored in a memory, A data processing device capable of storing data in a memory with a data width corresponding to a plurality of individual registers, and comprising an arbitrary number of registers from an arbitrary number of registers in the first register group and the second register group. When executing an instruction to store an arbitrary number of registers from an arbitrary number of registers into the above memory, the number of registers in the first register group to be stored into the memory specified by the instruction is set, and the number of registers stored into the memory specified by the instruction is set. A counter means that is decremented by a multiple of the data width of the register each time it is stored in the memory, and registers to be read from the first register group and the second register group to be stored in the memory. and a group of register numbers equal to the multiple of the above for holding register numbers, and when the value of the counter means is larger than the multiple, the first store after the start of the instruction is specified by the instruction. The first
Set successive register numbers starting from the first register number of the register group in order in each register of the register group with the above register number.

For the second and subsequent stores after the start of the instruction, a value obtained by adding the above multiple to the previous value is set in each register of the register number register group, and when the value of the counter means is smaller than the multiple and 0 or more, In this case, for the first store after the start of the instruction, consecutive register numbers from the first register number of the first register group specified by the instruction are counted from the first register of the first register group to the value of the counter means. The remaining register number registers are set to consecutive register numbers starting from the first register number of the second register group specified by the instruction, and for the second and subsequent stores after the start of the instruction. sets the above register number register group, and sets consecutive register numbers from the first register number of the second register group specified by the instruction to the remaining register number registers,
When the value of the counter means is negative, each register of the register number register group is controlled to be set to a value obtained by adding the above multiple to the previous value.

[For production]

In the present invention, a single instruction specifies multiple registers for a group of registers each of multiple types such as general-purpose registers and address registers, and processes an instruction to store them in the main memory fl (memory). .

(Example〕 Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is an instruction control unit, 2 is a main storage device (memory), and 5, 9 are alignment circuits J~8, 11, 12° 15.16
...30, 39, 40 are registers, 10 is an arithmetic register, and this arithmetic register 1a is made up of a plurality of registers that are assigned a series of numbers and stored in the memo exchange, and occupy the same data width just in case. It contains a first register group and a second register group. And register 16.1
7 is a multiple of the data width of the store to memory to the data width of the register that holds the register number that specifies the register to be read from the first register group and the second register group for storing to main storage device 1 (memory). The number of register numbers forms a register group.

13 is a selector, 14 is an ALU (Arithm@ti
c LogicUnit), 31, 32. 33, 34,
36, 37, and 38 are adders, and this adder 38 and register 23 are set to the number of registers in the first register group to be stored to the memory specified by the instruction, and the number of registers of the data width to be stored to that memory is set. It constitutes a counter means that is decremented by a multiple of the data width every time it is stored in the memory.

Then, in executing an instruction to store an arbitrary number of registers from an arbitrary numbered register of the first register group and an arbitrary number of registers from an arbitrary numbered register of the second register group into the memory, the counter means When the value of is greater than or equal to the above multiple, for the first store after the start of the instruction, consecutive register numbers from the first register number of the first register group specified by the instruction are assigned to each register number register group. For the second and subsequent stores after the start of the instruction, a value obtained by adding the above multiple to the previous value is set in each register of the register number register group, and the value of the counter means is set to the above value. If it is less than a multiple and greater than or equal to 0, for the first store after the start of the instruction, consecutive register numbers from the first register number of the first register group specified by the instruction are Set the number of registers corresponding to the value of the counter means, and set consecutive register numbers from the first register number of the second register group specified by the instruction to the remaining register number registers.
For subsequent stores, a value obtained by adding the above multiple to the previous value is set in the registers corresponding to the value of the counter means from the beginning of the register number register group, and the remaining register number registers are specified by the instruction. A consecutive register number is set from the first register number of the second register group, and when the value of the counter means is negative, the above multiple is added to the previous value in each register of the register number register group, and the next register number is set. It is configured to be controlled to set.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the instruction control section 1 decodes the instruction word and supplies information and control signals necessary for executing the instruction to each section of the data processing device. The main memory device 2 stores instructions and various data to be executed by the data processing device, but in the embodiment shown in FIG. 1, the instruction supply path to the instruction control unit 1 is omitted. From this main memory device 2, 8 bytes of data with addresses 8n to 8n+7 can be read at a time, but since the various operands stored in the main memory device 2 are placed at arbitrary addresses, the alignment circuit 5 is used to type various data types. Each time, the data is read out while being arranged in a predetermined position in the register 6 for easy processing. Then, as information for aligning the read data, the least significant three bits of the first address of the operand are supplied from the instruction control unit 1 via registers 39 and 40. It is possible to know at which position in the 8 bytes of data read from 2 the beginning of the operand is located.

The data stored in the main memory fii2 is also at address 8n.
Since it is based on 8 bytes of ~8n+7, in order to write data from any byte position, store data is set in registers 7 and 8, and then the alignment circuit 9 shifts the start position of the data to a predetermined byte position. and then stored. As information for arranging the store data, the least significant bit of the start address is supplied from the instruction control unit 1 via the registers 27 to 30, as in the case of reading. Here, the function of register 8 is to serve as a buffer for sequentially aligning and writing data larger than 8 bytes to main memory e2, and the stored data in register 7 that is out of alignment is stored in the next machine cycle. The manner in which it is supplied from register 8 and stored is the fifth
As shown in the figure. FIG. 5 is an explanatory diagram of the operation of the register 7.8 and alignment circuit 9 in FIG.
indicates the format of the data to be stored, (b
) shows the operation of register γ, 8 and alignment circuit 9. Further, (a) indicates the address of the main storage device e2, and ←) indicates the byte position from the beginning of the data to be stored.

A similar mechanism is also required for data read from the main memory device 2, but the details are omitted because it is not relevant to the STM instruction explained in this embodiment. Also, since the data to be stored in the main memory is not always all 8 bytes, the store mask decoder 3 uses store mask information that specifies which bytes to actually store among the 8 bytes.
5 and sends it from the register 26 to the main memory 2 together with the store data. For example, in FIG. 5, when bytes 0 to 5 of the store data are first stored, the first two bytes of the eight bytes of data to the main storage device 2 or bytes 14 to 15 of the last store data are stored. This is because the original contents of the 6 bytes after the 8 bytes must not be rewritten even after data is stored. Details of the store mask decoder 35 will be described later.

Next, the arithmetic register 10 includes eight nine-pace registers and eight general-purpose registers each having a data width of 4 bytes. Each base register and general-purpose register is assigned a unique consecutive number within the base register and general-purpose register, respectively, and these register numbers are used to distinguish each other. The 4-byte data held in the register 15 can be written into the arithmetic register 10 for the base register of the register number held in the register 19 or one of the 16 general-purpose registers. On the other hand, regarding reading, the base register or general-purpose register of the register number held in register 16 and register 1T can be read simultaneously, and operations between general-purpose registers and general-purpose registers can be processed at high speed. Further, data read from the arithmetic register 10 can also be stored in the main memory 2 through the register 7 and the alignment circuit 9.

The ALU 14 performs a logical operation or arithmetic operation on the data read from the operation register 10 and the data read from the other operation register 10 or the data read from the main storage device 2 selected by the selector 13.
5 to the calculation register 10.

Next, the register 16 holds the register number of the register read from the calculation register 10, and the register 17 holds the register number read from the other calculation register 10, and also controls the register number written to the calculation register 10. Registers 18 and 19 and register numbers are rotated.

The registers 16 and 17 include adders H, 32,
33 and 34 are connected, the contents of the registers 20 and 21 holding the register number supplied from the instruction control unit 1 can be added by 1 or +1, and the next place can be set, and the contents of the register can be set by +2. You can also set the added value. Here, the meaning of adding 1 to the register number is to obtain the register number of the next base register or general-purpose register. As a reminder, what you should be careful about here is that the base register and general-purpose register each have 8
Since there are only three registers, the registers following the base register/general-purpose register having the largest register number become the base register/general-purpose register having the smallest register number, and the adders 31, 32, 33, and 34 operate in the same manner.

The register 22 is a dedicated register for controlling STM instructions, and is set by supplying the value of the Nb field of the instruction word, that is, the number of base registers to be stored, from the instruction control unit 1, and mainly controls the contents of the operation register 10. Each time the value is stored in the storage device 2, the adder 37 decrements the value by -2.

The function of this register 22 is calculated by controlling the register numbers set in the register number registers 16 and 1 of the register 10, and as shown in the table below, the 87M instruction is executed according to the value of the register 22. The contents of the register 1617 are controlled in accordance with the first store operation or the second and subsequent store excitations of the specified arithmetic register. Yes, when an STM instruction is executed, the value of the Ng field in the corner field of the instruction word is supplied from the instruction control unit 1, and the value obtained by adding these values in the adder 36, that is, the pace register and general-purpose register to be stored. The number is set and is decremented by -2 by the adder 38 each time the contents of the arithmetic register 10 are stored in the main memory device 2. The value of the register 23, which is decremented by -2 for each store operation, is supplied to the store mask decoder 35 via registers 24 and 25.

The store mask decoder 35 receives the information of the least significant 3 bits of the start address of the store from the instruction control unit 1 via the n registers 27, 28, and 29 to the main storage device 2, and the 1/digits information from the register 23. /24 and 25, that is, the number of remaining registers to be stored and information on whether the store operation is the first store operation of the 87M instruction, generates store 1 disk information and stores it in the register. 26 to the main memory fM2 in synchronization with the store data from the alignment circuit 9. FIG. 2(,) shows a store mask generation pattern.

In Figure 2, which is a diagram (b) showing the operation pattern (a) and usage example of the store mask decoder 35 in Figure 1, the mask pattern A shown in (a) is the number of registers remaining in the first store. Mask pattern B is used when the number of remaining registers is 1 in the first store, and mask pattern C is used when the number of remaining registers is 2 or more in the second and subsequent stores. For mask pattern D, when the number of remaining registers is 1 in the second and subsequent stores,
For mask pattern E, when the number of remaining registers is 0 in the second and subsequent stores, the number of remaining registers is 1 in the previous store in mask pattern FF12fllj.
The bytes corresponding to the bits set to rlJ in each mask pattern are actually written into the main memory.

FIG. 2(b) shows how the store mask pattern is used depending on the number of registers actually stored and the start address of stores.

Note that the number of store operations actually performed on the main memory device 2, S, is the sum of the base registers and general-purpose registers to be stored, R=Nb+Ng, and the lowest 3 pits A to 5 of the first address of the store destination = (4R+A+7)/ 8 (rounded down to the nearest whole number)
...(1), and the store operation is performed this number of times under control from the instruction control unit 1.

The above is a functional explanation of each part of the data processing device shown in FIG.
This will be explained with reference to FIG. 3, which is a time chart showing an example of execution of the 7M instruction. In the figure, the register numbers of the base register and general-purpose register and the contents read from each register are Bj (j-0...7).

It is expressed as Gj (j-0...7).

And in this example, the pace register to be stored is B
, and the general-purpose register is G.

In the sum of 4 starting from ff+9, the lowest 3 bits of the store address are 6, and the number of store operations is 6 according to the above equation (1).

The following is a step-by-step explanation.

First, machine cycle t. The instruction control unit 1 that decodes the 87M instruction extracts the instruction word (see FIG. 4) and outputs information such as Nb, Ng, B 1 v B j , etc. Then, these information are stored in machine cycle t1
In the register 23, Nb+Ng=9, in the register 22 Nb=5, in the register 21 BimB, and in the register 20 CI=G. onwards,
The contents of registers 21 and 20 continue to be held as they are until the 87M instruction is completed. On the other hand, the information for Nb +Ng and Nb 1 taken into registers 23 and 22 is the same (
It is decremented by -2 until the 87M instruction is completed, and is used to control the generation of a store mask and the read number of the arithmetic register.

Then, the read register number from the arithmetic register 10 held in registers 17 and 16 is set for the first time in machine cycle t2 in order to read data from the arithmetic register 10, and until machine cycle t8 (
B5+B6L (B7+Bo) and base register bare are instructed in order, but machine cycle 1. When it is found that the number of remaining base registers is 1 due to the value of register 22 = 1, the next machine cycle t4
Then, the remaining pace register B1 and the next general-purpose register are controlled to point to the first G8, and thereafter (G,.

's ) * (c6, none) and instruct the register numbers to be read in order.

After machine cycle tlI, the pace registers and general-purpose registers read two by two from the operation register 10 are registers N and ? 2, 7.8 and the main memory f2 via the alignment circuit 9.
The data is stored to , and ends after six store operations.

On the other hand, in synchronization with the store data, the store mask is generated by the sorting circuit 9 based on the number of remaining registers passed through registers 23 to 24 and 25 and the information on the lowest three pits of the store address.
It is generated according to the byte order of the store data aligned in , and is sent to the main storage device t2.

〔Effect of the invention〕

As explained above, the present invention relates to a general-purpose register.

By processing an instruction to specify multiple registers in one instruction for a register group consisting of multiple types of address registers, etc., and store them in the main storage device (memory), store data/data to memory can be stored. If @ is multiple times the data width of each register, it is possible to store multiple registers simultaneously into memory in one store operation, and it is also possible to store consecutively at the joint between registers of different types. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the store mask decoder in FIG. 1, FIG. 3 is a time chart showing an example of the operation in the embodiment of FIG. 1, and FIG. Figure 4 is an LM instruction, 87M, used to explain the present invention.
FIG. 5 is an explanatory diagram showing the instruction word format of an instruction. FIG. 5 is an explanatory diagram of the operation of the register and alignment circuit in FIG. 1. 1...Instruction control unit, 2...Main storage device (memory), 5.9...Alignment circuit, 1o...Arithmetic register, 13...Selector, 14...・ALU
, 6-8, 11, 12. 15-30...

Claims (1)

[Claims] A first register consisting of a series of numbered registers that occupy the same data width when stored in memory.
A data processing device having a register group and a second register group, and capable of storing data in the memory with a data width corresponding to a plurality of individual registers; A first register to be stored in the memory specified by the instruction in executing an instruction to store an arbitrary number of registers from the registers and an arbitrary number of registers from the arbitrary numbered registers of the second register group into the memory. a counter means in which the number of registers of the group is set and is decremented by a multiple of the data width of the store to the memory each time the data width of the register is stored; and the first register group and the second register. a register number register group of the multiple number for holding a register number specifying a register to be read from the group for storing into the memory, and when the value of the counter means is greater than or equal to the multiple number, an instruction For the first store after the start, consecutive register numbers from the first register number of the first register group specified by the instruction are set in each register of the register number register group, and for the second and subsequent stores after the start of the instruction, For storing, each register of the register number register group is set to a value obtained by adding the multiple to the previous value, and when the value of the counter means is smaller than the multiple and is 0 or more, after the start of the instruction For the first store, consecutive register numbers from the first register number of the first register group specified by the instruction are set in the number of registers equal to the value of the counter means from the first register of the register number register group. , the remaining register number registers are set with consecutive register numbers starting from the first register number of the second register group specified by the instruction, and for the second and subsequent stores after the start of the instruction, the register numbers of the register number register group are set in the remaining register number registers. The registers corresponding to the number of values of the counter means from the beginning are set with the value obtained by adding the above multiple to the previous value, and the remaining register number registers are set with the value starting from the register number at the beginning of the second register group specified by the instruction. It is characterized in that when consecutive register numbers are set and the value of the counter means is negative, each register of the register number register group is controlled to set a value obtained by adding the previous value by the multiple. data processing equipment.