JPH02103630A - Data processor - Google Patents

Data processor

Info

Publication number
JPH02103630A
JPH02103630A JP63256845A JP25684588A JPH02103630A JP H02103630 A JPH02103630 A JP H02103630A JP 63256845 A JP63256845 A JP 63256845A JP 25684588 A JP25684588 A JP 25684588A JP H02103630 A JPH02103630 A JP H02103630A
Authority
JP
Japan
Prior art keywords
registers
plural
composed
instruction
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63256845A
Other versions
JPH0748179B2 (en
Inventor
Tomohiko Endo
Akihisa Makita
Original Assignee
Koufu Nippon Denki Kk
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koufu Nippon Denki Kk, Nec Corp filed Critical Koufu Nippon Denki Kk
Priority to JP63256845A priority Critical patent/JPH0748179B2/en
Publication of JPH02103630A publication Critical patent/JPH02103630A/en
Publication of JPH0748179B2 publication Critical patent/JPH0748179B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043LOAD or STORE instructions; Clear instruction

Abstract

PURPOSE: To speed up a data processing designating plural registers with one instruction to a register group composed of plural kinds of plural general purpose registers, address registers, etc., each of which is composed of plural registers and processing instructions for storing data in a main memory device.
CONSTITUTION: This data processor is constituted of an instruction control section 1, main memory device (memory) 2, alignment circuits 5 and 9, registers 6-8, 11, 12, 15...30, 39, and 40, operation register 10, selector 13, ALU (arithmetic logic unit) 14, store mask decoder 35, and adders 31...34, 36, and 38. Then plural registers of the register group composed of general purpose registers, address registers, etc., each of which is composed of plural registers are designated by one instruction and instructions for storing data in the memory 2 are performed. Therefore, processing speeds of arithmetic operations of various data sizes can be improved.
COPYRIGHT: (C)1990,JPO&Japio
JP63256845A 1988-10-12 1988-10-12 Data processing equipment Expired - Lifetime JPH0748179B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63256845A JPH0748179B2 (en) 1988-10-12 1988-10-12 Data processing equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63256845A JPH0748179B2 (en) 1988-10-12 1988-10-12 Data processing equipment
FR8913353A FR2637708B1 (en) 1988-10-12 1989-10-12 Apparatus for processing data

Publications (2)

Publication Number Publication Date
JPH02103630A true JPH02103630A (en) 1990-04-16
JPH0748179B2 JPH0748179B2 (en) 1995-05-24

Family

ID=17298212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63256845A Expired - Lifetime JPH0748179B2 (en) 1988-10-12 1988-10-12 Data processing equipment

Country Status (2)

Country Link
JP (1) JPH0748179B2 (en)
FR (1) FR2637708B1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7035997B1 (en) 1998-12-16 2006-04-25 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US7237093B1 (en) 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7707391B2 (en) 1998-12-16 2010-04-27 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US7765546B2 (en) 1998-12-16 2010-07-27 Mips Technologies, Inc. Interstream control and communications for multi-streaming digital processors

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0583932B2 (en) * 1988-12-29 1993-11-30 Intaanashonaru Bijinesu Mashiinzu Corp
JP2889845B2 (en) * 1995-09-22 1999-05-10 松下電器産業株式会社 The information processing apparatus
JPH1091443A (en) 1996-05-22 1998-04-10 Seiko Epson Corp Information processing circuit, microcomputer and electronic equipment
GB2326253A (en) * 1997-06-10 1998-12-16 Advanced Risc Mach Ltd Coprocessor data access control

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916388A (en) * 1974-05-30 1975-10-28 Ibm Shifting apparatus for automatic data alignment

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7035997B1 (en) 1998-12-16 2006-04-25 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US7237093B1 (en) 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7467385B2 (en) 1998-12-16 2008-12-16 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7650605B2 (en) 1998-12-16 2010-01-19 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7707391B2 (en) 1998-12-16 2010-04-27 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US7765546B2 (en) 1998-12-16 2010-07-27 Mips Technologies, Inc. Interstream control and communications for multi-streaming digital processors
US7900207B2 (en) 1998-12-16 2011-03-01 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7926062B2 (en) 1998-12-16 2011-04-12 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US8468540B2 (en) 1998-12-16 2013-06-18 Bridge Crossing, Llc Interrupt and exception handling for multi-streaming digital processors

Also Published As

Publication number Publication date
FR2637708B1 (en) 1992-10-23
JPH0748179B2 (en) 1995-05-24
FR2637708A1 (en) 1990-04-13

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