KR100413651B1 - An information processing apparatus and its information processing method for realizing data transfer of multiple registers with short word length commands - Google Patents

Abstract

The information processing apparatus of the present invention includes a register group composed of a plurality of registers, a separate field indicating whether or not each machine word instruction in a program is sequentially read, and a register of a portion of the register group is individually designated. Data transfer is performed between a first operand comprising a batch field indicating whether or not to be designated collectively, a second operand specifying an effective address of a memory, and a plurality of registers designated by the first operand and a memory designated by the second operand. Decoding means for detecting an instructing machine language instruction, determining means for determining whether each bit is valid for individual fields and batch fields in the first operand of the detected machine language instruction, a register of a register corresponding to the bit determined to be valid in the individual field 1st number generation The second generating means, which sequentially generates register numbers of portions of the registers other than the above, when the validity is determined in the batch field, the register of the register number generated by the first generating means and the second generating means, and the second operand. And transfer means for performing data transfer between consecutive memory areas from the designated effective address. According to this configuration, in a machine language instruction capable of specifying a plurality of registers, a plurality of registers can be specified with a small number of bits, and an increase in the code size of the program can be suppressed even if the number of registers mounted in the information processing apparatus increases.

Description

Information processing apparatus and its information processing method for realizing data transfer of multiple registers with short word length instruction

The present invention relates to an information processing apparatus using an instruction for transferring data between a plurality of registers and a continuous area of a memory, and an information processing method thereof.

In recent years, the processing capacity of information processing apparatuses such as microcomputers has been greatly improved and used in all fields.

In general, microcomputers use transfer instructions for saving and restoring the contents of general-purpose registers to a memory when calling a subroutine or switching a task.

Some conventional microcomputers transfer a plurality of register data to and from the memory by one of the transfer commands (for example, the "MOVEM command" disclosed in "MC68040 User Manual", published by Motorola, Japan). .

In this instruction, when a plurality of registers are designated, one register is allocated to one bit in an operand, and a register designation field having the same number of bits as the number of registers implemented is required.

1 is a diagram showing bit allocation of an operand for designating a plurality of registers in an instruction for transferring a plurality of registers of a conventional processor. The processor specifies 16 registers (16 data registers and 8 address registers) in 16 bits.

However, according to the conventional technology, the larger the number of registers mounted in the processor, the longer the register designation field and the larger the code size.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an information processing apparatus and information processing method capable of designating a plurality of registers in a short register designation field and suppressing an increase in code size even when the number of registers is large. It is for.

An information processing apparatus according to the present invention for achieving the above object comprises: a register group consisting of a plurality of registers;

A first field comprising a separate field indicating whether to sequentially read a machine language instruction in the program and individually designating a register of a portion of the register group and a batch field indicating whether to designate a register of another portion of the register group collectively; Decoding means for detecting a machine language instruction having an operand and a second operand specifying an effective address of the memory, the machine language instruction instructing data transfer between a plurality of registers designated by the first operand and a memory designated by the second operand;

Determination means for determining whether each bit is valid or invalid for the individual field and the batch field in the first operand of the detected machine language instruction;

First generating means for generating a register number of a register corresponding to the bit determined to be valid in the individual field;

Second generating means for sequentially generating register numbers of the other partial registers when it is determined that the batch field is valid;

And transfer means for performing data transfer between the register of the register number generated by the first generating means and the second generating means, and the memory area contiguous from the effective address designated by the second operand.

According to this configuration, in a machine language instruction capable of designating a plurality of registers, a plurality of registers can be specified with a small number of bits, and an increase in the code size of a program can be suppressed even if the number of registers mounted in the information processing apparatus is large. There is.

The register group may include m + n registers, the individual field may be composed of m bits corresponding to m registers individually, and the batch field may be configured of one bit for collectively designating n registers. According to this configuration, in addition to the effect of the first invention of the present application, there is an effect that a plurality of registers can be designated in a field of 1 bit.

In addition, the determination means,

Latch means for latching the contents of the individual field and the batch field of the machine language instruction detected by the decryption means, the contents of the individual field being latched above the contents of the batch field;

Bit detection means for detecting a first valid bit from the MSB side of the latch means and outputting a position signal indicating the bit position to the first and second generating means;

A bit reset means for resetting the bits detected by the bit detection means among the bits latched by the latch means when the data transfer for one register is made by the transfer means,

The bit detection means attempts the detection again after the reset. The first and second generating means may be configured to generate one register number in accordance with the position signal in one register data transfer cycle.

The first generating means may be configured to generate the number of the register corresponding to the bit position among the m registers when the position signal indicates the bit position in the individual field.

In addition, the second generating means,

Batch field determination means for determining whether the position signal indicates the bit position of the batch field among the latch means, and when it is determined that the position signal indicates the bit position of the batch field, one in one transfer cycle for the n registers. It may be a configuration including a continuous generating means for sequentially generating a register number.

According to this configuration, first, register data specified in the individual designated field is transferred, and then register data designated in the batch designated field is transferred.

The second operand is designated with a stack pointer, and the transfer means is configured to perform data transfer between a register of register numbers generated by the first and second generating means and a stack area designated by the stack pointer. You may also do it.

According to this configuration, since data transfer is performed between the plurality of registers and the stack area, the data can be saved and the data can be efficiently returned in the subroutine or interrupt processing routine.

The register group includes m + n registers, the individual field is composed of m bits corresponding to each of the m registers, the batch field is composed of at least 2 bits, and the second generating means includes bits of the batch field. According to the pattern, a register number corresponding to a register group consisting of a plurality of predetermined registers among n registers may be sequentially generated.

According to this configuration, it is possible to specify collectively in units of register groups.

The machine language instruction further instructs an operation between a plurality of register data designated by the first operand and data of a memory area contiguous from the execution address designated by the second operand, and the information processing apparatus instructs the machine language instruction. And a calculating means for executing the calculated operation, wherein the transmitting means may be configured to transmit the calculation result by the calculating means to the plurality of registers or the memory area.

According to this configuration, for example, flexible program design is possible, such as updating data collectively for the table data in the memory.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

1 is a diagram illustrating bit allocation of an operand for specifying a plurality of registers in an instruction for transferring a plurality of registers of a conventional processor.

2 is a diagram showing a command method for transferring a plurality of registers according to the first embodiment of the present invention.

3 is a block diagram showing a configuration of main parts of a microcomputer according to the first embodiment of the present invention.

4 is a block diagram showing an internal configuration of a register designation field decoder 105 according to the first embodiment of the present invention.

5 is a detailed circuit diagram of a latch 201 according to the first embodiment of the present invention.

6A is an explanatory diagram showing the input / output logic of the priority encoder 202 according to the first embodiment of the present invention.

6B is an explanatory diagram showing input and output logic of the decoder 203 according to the first embodiment of the present invention.

6C is an explanatory diagram showing input and output logic of the register number conversion circuit 204 according to the first embodiment of the present invention.

6D is an explanatory diagram showing input and output logic of the register number detection circuit 214 according to the first embodiment of the present invention.

7A is a detailed circuit diagram of a batch designation bit detection circuit 205 according to the first embodiment of the present invention.

7B is an explanatory diagram showing the input / output logic of the batch designation bit detection circuit 205 according to the first embodiment of the present invention.

7C is a circuit diagram of a batch processing continuation signal generating circuit 210 according to the first embodiment of the present invention.

7D is an explanatory diagram showing the input / output logic of the integrator 209 according to the first embodiment of the present invention.

8A and 8B are explanatory diagrams showing control order of MOVM instructions by the instruction decoder 101 according to the first embodiment of the present invention in register transfer levels.

9 is a schematic diagram showing an order in which a plurality of register data is stored in a memory by a MOVM instruction according to the first embodiment of the present invention.

10 is a schematic diagram showing an order in which a plurality of data from a memory is stored in a register by a MOVM instruction according to the first embodiment of the present invention.

11 is a execution time chart of a MOVM instruction according to the first embodiment of the present invention.

12 shows an example of a context save program according to the first embodiment of the present invention.

13 is an explanatory diagram comparing a conventional MOVM command with a MOVM command of an embodiment of the present invention.

14 is a view showing a command method for transferring a plurality of registers according to a second embodiment of the present invention.

Fig. 15 is a block diagram showing an internal configuration of a register designation field decoder according to the second embodiment.

16 is an explanatory diagram showing an input / output logic table of the register number conversion circuit 303 according to the second embodiment.

17A and 17B are explanatory diagrams showing control order by the instruction decoder in the register transfer level when the call instruction of the subroutine and the return instruction from the subroutine are applied to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: instruction register 101: instruction decoder

102: register file 103: operator group

104: memory 105: register designation field decoder

201, 208, 213, 300: Latch 202: Priority Encoder

203: decoder 204, 303: register number conversion circuit

205: batch designation bit detection circuit

206, 301: Batch Register Number Output Sequencer

207, 212, 601, 603: AND gate

209, 302: incremental

210: batch processing continuation signal generation circuit 211: register processing completion detection circuit

214: register number detection circuit 215, 216: selector

602: RS flip-flop SP: stack pointer

2 is a diagram showing an instruction method for transferring a plurality of registers according to the first embodiment of the present invention. In FIG. 2, "MOVM regs, <ea>" is a machine language command for instructing block transfer to the continuous area of the memory, and is expressed in mnemonic format. "MOVM <ea>, regs" is a machine language instruction for instructing block transfer from a contiguous area of memory to a plurality of registers.

"MOVM" is an OP code, and different codes are assigned to "MOVM regs, <ea>" and "MOVM <ea>, regs" for determining the transmission direction.

"<Ea>" is an operand that specifies an effective address of the memory, and is transferred to a continuous memory area from the head of the designated address. In this embodiment, it is assumed that the effective address is specified by indirect addressing by the stack pointer.

"Regs" is an operand for specifying a register to be transferred, and indicates a register designation field obtained by designating multiple registers. This register designation field has an 8-bit structure as shown in FIG. 2, and has individual designation fields and collective designation fields. The individual designation field is composed of 6 bits of bits 7 to 2, and each bit is set to '1' for R10, R11, R12, R13, R14, and R15 in order from the MSB (most significant bit) side. This means transferring between registers corresponding to bits. The batch designation field consists of bit 1 (denoted "other" in the figure), and designates other registers R0 to R9 collectively. When this bit is set to "1", it means to transfer between all registers of R0 to R9. In this configuration, 16 general purpose registers (R0 to R15) are mounted.

The registers designated by the individual designated fields and the collective designated fields are preferably divided so as to correspond to the destructive registers and the non-destructive registers determined by the compiler. Here, the destroy register is a register that is used without destroying the register data in the subroutine, that is, save and return to the stack. Non-destructive registers are registers in which the register data is stored in the subroutine, that is, saved and returned to the stack.

3 is a block diagram showing the configuration of main parts of the microcomputer according to the present embodiment.

The main part of this microcomputer includes an instruction register 100, an instruction decoder 101, a register file 102, an operator group 103, a memory 104, and a register designation field decoder 105.

The instruction register 100 sequentially holds instructions fetched from the memory 104.

The command decoder 101 decodes the command held in the command register 100 and outputs various control signals for controlling the execution of the command. In particular, when the instruction decoder 101 decodes the MOVM instruction shown in FIG. 2, the register of the register number sequentially output by the register designation field decoder 105 and the memory 104 designated by the <ea> operand. Control data transfer between contiguous regions of the image.

The register file 102 is composed of 32-bit general registers R0 to R15 and a 32-bit stack pointer SP that indicates the head of the stack area in the memory 104.

The operator group 103 includes a plurality of calculators, and calculates an effective address designated by the data operation designated by the instruction or the operand of the instruction under the control of the instruction decoder 101. One of the calculators (hereinafter, referred to as dedicated calculators) in the calculator group 103 is provided exclusively for calculating the operand address. The dedicated operator is based on the control of the instruction decoder 101 at the time of execution of the MOVM instruction shown in FIG. 2, and the offset value (4) is set in the contents of the stack pointer designated by the <ea> operand every time 32-bit data is transmitted. Memory addresses of the continuous area are sequentially calculated.

The memory 104 stores a program or data including the MOVM instruction shown in FIG. 2, and has a stack area in part of the storage area.

The register designation field decoder 105 decodes the regs operand described above when the instruction decoder 101 decodes the MOVM instruction, and outputs the register number of the designated register to the register file 102.

4 is a block diagram showing the internal structure of the register designation field decoder 105. As shown in FIG. The register designation field decoder 105 includes a latch 201, a priority encoder 202, a decoder 203, a register number conversion circuit 204, a batch designation bit detection circuit 205, and a batch designation register. The number output sequencer 206, the register processing completion detection circuit 211, the AND gate 212, the latch 213, the register number detection circuit 214, and the selector 215, 216 are comprised. The batch designation register number output sequencer 206 is composed of an AND gate 207, a latch 208, an incrementer 209, and a batch processing continuation signal generating circuit 210.

The latch 201 latches a register designation field in the MOVM instruction at the time when the MOVM instruction is detected by the instruction decoder 101. Each latched bit " 1 " is in turn reset by the decoder 203 every time data is transmitted. 5 shows a specific circuit example of the latch 201, and consists of eight one-bit latch circuits. Each latch circuit has a reset terminal individually, and is reset by the decoder 203 when " 1 " is detected by the priority encoder 202.

The priority encoder 202 detects one bit in the register designation field in the latch 201 for each data transfer cycle, and outputs a signal (hereinafter referred to as a bit position) indicating the detected bit position. do. An explanatory diagram (truth value table) showing the input / output logic of the priority encoder 202 is shown in FIG. 6A. In Fig. 6A, both input and output are shown in binary. As shown in the "input" column, the priority encoder 202 detects the bit that is "1" for the first time as viewed from the MSB side of the latch 201 for each data transfer cycle, and the detection result is displayed in the "output" field. As described above, the bit position indicated by three bits is output. Thereafter, the detected bit "1" is reset by the decoder 203, so that "1" in the individual designated fields (bits 7 to 2) shown in FIG. 2 is sequentially detected every transmission cycle, and collectively. "1" in the designated field (bit 1) is detected. In addition, the priority encoder 202 detects the last bit "1" after detecting the first bit "1" of the latch 201 and sets the bit detection continuation signal to be valid "1" until it finishes. Output

The decoder 203 inputs the bit position detected by the priority encoder 202 and resets "1" of the latch 201 corresponding to the bit position to "0". Explanatory drawing (truth value table) which shows the input / output logic of the decoder 203 in FIG. 6B is shown. In FIG. 6B, both input and output are represented in binary. For example, when the "input" is the bit position "111" from the priority encoder 202, only bit 7 of the "output" becomes "0", so that bit 7 of the latch 201 is reset. This makes it possible for the priority encoder 202 to detect &quot; 1 &quot; further down the latch 201 in the next data transfer cycle.

The register number conversion circuit 204 inputs the bit position from the priority encoder 202 and outputs the register number of the register corresponding to it. Explanatory drawing (truth value table) which shows the input / output logic of the register number conversion circuit 204 in FIG. 6C is shown. In Fig. 6C, both input and output are represented in binary. In the present embodiment, register numbers 0000 to 1111 are assigned to registers R0 to R15 of the register file 102 in binary. For example, when the "input" is "111", the "output" becomes the register number "1010" of R10. In addition, as shown in the "input" and "output" columns of FIG. 6C, the register number conversion circuit 204 outputs the register number only for the bit positions representing each bit of the individual designated field.

The batch designation bit detection circuit 205 detects a bit position indicating the batch designation field among the bit positions from the priority encoder 202, and outputs a batch designation bit detection signal indicating that it is detected. A specific circuit example of the collectively designated bit detection circuit 205 in FIG. 7A is shown in FIG. 7B and its input / output logic. As shown in FIG. 7A, the batch designation bit detection circuit 205 includes an AND gate 601, an RS flip-flop 602, and an AND gate 603. The AND gate 601 detects that the bit position is "001", that is, a batch designation field. As shown in FIG. 7B, the RS flip-flop 602 is set at the time when it is detected that the batch designation field is detected by the AND gate 601, and is reset by the AND gate 603. FIG. The AND gate 603 resets the RS flip-flop 602 when the count value output of the incrementer 209 becomes " 1001 ". Therefore, the batch designation bit detection signal becomes valid "1" at the time when "1" of the batch designation field is detected by the priority encoder 202, and then the count value of the incrementer 209 becomes "1001". It becomes invalid "0" in the next cycle.

The batch designation register number output sequencer 206 outputs one register number of the registers R0 to R9 for each data transfer cycle when the batch designation bit detection signal from the batch designation bit detection circuit 205 is valid.

The AND gate 207 enables the supply of the latch clock to the latch 208 when the batch designation bit detection signal is valid.

The latch 208 is a 4-bit long latch and latches the output of the incrementer 209 every data transfer cycle when the batch designation bit detection signal is valid. Since the batch designation bit detection signal becomes invalid "0" when the count value of the incrementer 209 becomes "1001", the latch 208 is "1001" while the batch designation bit detection signal is invalid "0". Is keeping.

The incrementer 209 sequentially outputs register numbers "0000" to "1001" by adding 1 to the output of the latch 208. 7D shows input / output logic of the integrator 209. As shown in the 7D diagram, when the "input" is "1001", the "output" is "0000", and when the "input" is "0000" to "1001", the "output" is a value to which 1 is added. As a result, the register numbers R0 to R9 are combined with the data transfer cycles and output in order.

The batch processing continuation signal generating circuit 210 outputs a batch processing continuation signal indicating that the data transfer of the batch designation register is being continued. The circuit example is shown in FIG. 7C. The batch processing continuation signal generating circuit 210 is an OR gate 604, and outputs the batch processing continuation signal as valid ("1") when the count value from the incrementer 209 is other than "0000".

The register processing completion detection circuit 211 takes a logical sum of the bit detection continuation signal from the priority encoder 202 and the batch processing continuation signal and outputs it as a register processing continuation signal. This register processing continue signal becomes valid "1" while all the register numbers specified in the register designation field are output.

The AND gate 212 prohibits clock supply to the command register while the register processing continuation signal is valid.

The latch 213 latches a register designation field in the MOVM instruction at the time when the MOVM instruction is detected by the instruction decoder 101.

The register number detection circuit 214 detects the number of registers specified in the register designation field in the latch 213 and the memory size (transfer data size) required for the data of the register number. 6D shows an input / output logic of the register number detection circuit 214. FIG. In FIG. 6D, "input" is a value of the register designation field in the latch 213. FIG. For bit 2 to bit 2 of the "input" column, for example, the expression "one" or "1" indicates only the number of "1", omitting six of 100000, 010000, 001000, 000100, 000010, 000001. have. "Output 1" shows the number of registers and "Output 2" shows the transfer data size. In this embodiment, since each register is four bytes long, the transfer data size is four times the number of registers indicated at output 1.

The selectors 215 and 216 output register numbers output from the register number conversion circuit 204, the incrementer 209, and the instruction decoder 101 to a register file.

8A and 8B are explanatory diagrams showing the control procedure of the MOVM instruction by the instruction decoder 101 at the register transfer level.

In FIG. 8A, MOVMs [R10-R15, etc.], (SP) show a case where data is stored in memory from all registers. FIG. 9 is a schematic diagram showing the order in which data is stored in the memory by this command.

Part (a1) shows the control contents for transferring register data designated as individual fields to the memory. For example, for (R10? (SP-4)), the instruction decoder 101 reads data from the register of register number 10 and subtracts 4 from the contents of the stack pointer SP to a memory whose address is the address. Data is transferred by recording. The register number at this time is generated by the register number conversion circuit 204 and supplied to the register file. The memory address at this time is obtained by subtracting 4 from the contents of the SP by the dedicated operator. In this example, all registers of the individual fields are specified, but registers not specified are not transferred because the register number is not generated by the register number conversion circuit 204.

The portion (a2) shows the control contents for transferring the register data designated in the batch field to the memory. The control contents of the command decoder 101 are as described above. However, the register number is different from the above in that it is generated by the incrementer 209.

In addition, the instruction decoder 101 sequentially subtracts a multiple of four (4, 8, 12, ...) for each data transfer from the contents of the stack pointer SP by a dedicated operator through the data transfer of (a1) and (a2). Create a memory address.

Part of (a3) means updating the stack pointer. The instruction decoder 101 subtracts the transfer data size (or transfer register number * 4) generated by the register number detection circuit 214 from the contents of the stack pointer SP with a dedicated operator, and subtracts the subtracted value from the stack pointer. It is stored in (SP).

In FIG. 8B, MOVM (SP), [R10-R15, etc.] shows a case where data is returned from memory to all registers. FIG. 10 shows a schematic diagram showing the order in which data is returned from the memory to the registers R0 to R15 by this instruction. In the control of the instruction decoder 101 for this instruction, only the point of updating the stack pointer is performed first and the data transfer direction (register from memory) is different. Other than that is as described above, detailed description thereof will be omitted.

11 shows execution time charts of the MOVM [R10-R15, etc.], (SP) instructions of FIG. 8A. In the figure, a to j are symbols shown in respective parts of FIG. 4 and are the following signals. The numerical value for "Ox" represents a hexadecimal number.

a: contents of command register

b: Register designation field in latch 201

c: bit position output from the priority encoder 202

d: register number output from register number conversion circuit 204

e: bit detection continuation signal output from priority encoder 202

f: batch designation bit detection signal output from batch designation bit detection circuit 205

g: Register number outputted from the incrementer 209

h: batch processing continuation signal outputted from the batch processing continuation signal generating circuit 210

i: Register processing continuation signal output from the register processing completion detection circuit 211

j: Register number output from selector 216

As in the eleventh figure, in the MOVM instruction, data of a plurality of registers specified in the register designation field is transferred in sequence every transfer cycle. 11 shows a case where all registers are designated, but the transfer cycle does not occur when " 0 " is set in the individual designation field for R10 to R15. When the batch designation field is "0", the transfer cycle of R0 to R9 does not occur.

The operation of the information processing device configured as described above will be described taking the case of transferring a plurality of data from a memory to a register as an example.

Typically, some of the general purpose registers in subroutines are used as destructive registers, and others are used as nondestructive registers. For example, when R0 to R9 are defined as destruction registers by the compiler, the destruction registers do not need to save to the stack and return from the stack in the subroutine. Therefore, the stack save and return of the required number of non-destructive registers are performed only when more than 10 registers are used in the subroutine.

For example, in the case of using two registers R10 and R11 in addition to the destroy register in the routine, the next (1) instruction is placed at the beginning of the subroutine and the next (2) instruction is placed at the end of the subroutine. do.

Thus, the microcomputer saves only the non-destructive registers R10 and R11 on the stack after the subroutine execution start value, and returns only R10 and R11 from the stack immediately before the subroutine execution ends. The instruction execution operation in (1) ends in the first two cycles shown in FIG.

Next, an example of saving and returning context associated with task switching will be described.

12 shows an example of the context save program.

In Fig. 12, (11.1) is a command to save the value of the stack pointer SP into the stack pointer save area of the predetermined context save area. Here,

The save area of the tack pointer is set to OxFFFFFEBC for convenience. (11.2) is an instruction to set a fixed address predetermined as a context save area to the stack pointer SP. In this example, OxOOOO OOOO is used as a fixed address for convenience. (11.3) is a MOVM instruction that saves the contents of all registers into the context save area. (11.4) is an instruction to load the stack pointer SP from the area where the task stack pointer value newly executed by the task switching is saved. In this case, the area that is the stack pointer save area for a newly executed task is referred to as OxFFFFFEBC for convenience.

By the execution of this program, the contents of all registers R0 to R15 are transferred to the context save area. The transfer operation by the MOVM instruction in (11.3) is the same as the time chart shown in FIG. 11, and is executed in 16 cycles.

As described above, according to the present embodiment, it is possible to designate a large number of registers with a small number of bits by grouping registers into destructive registers and non-destructive registers, and assigning them to a batch designation field that designates a destroyed register as 1 bit. Even if the code size does not increase. FIG. 13 shows a comparison of the conventional MOVM command and the MOVM command of this embodiment. In Fig. 13, (1), (2), and (11.3) show the command bit pattern of the MOVM instruction of this embodiment and the instruction mnemonic which have already been described. (1 '), (2'), and (11.3 ') indicate the command bit pattern of the conventional MOVM instruction and its instruction mnemonic. In the instructions (1) and (2), the third byte "OxCO" specifies two registers R10 and R11, whereas in the instructions (1 ') and (2'), the third and fourth instructions are used. "0x0030" of the byte designates the registers R10 and R11. In the instruction of (11.3), the "OxFE" of the third byte designates all registers R0 to R15. In the instruction of (11.3 '), the "OxFFFF" of the third and fourth bytes is all Registers R0 to R15 are specified. As described above, in the present embodiment, the code size of 1 byte is reduced by one MOVM instruction. It is common to have many programs subdivided into many subroutines, and MOVM instructions are frequently used because they are used for register save and return in subroutines. Therefore, the code size of the whole program can be shortened.

In this embodiment, the grouping of registers is a destructive register or a non-destructive register defined by the compiler, but the grouping may be performed under other conditions.

In the present embodiment, a load / store for a plurality of registers is used. However, the operation instruction may use a plurality of registers.

14 is a diagram showing a command method for transferring a plurality of registers according to a second embodiment of the present invention. For the MOVM instruction of FIG. 2 shown in the first embodiment, only the batch designation bit is 2 bits is different. Hereinafter, description of the same parts will be omitted and only different parts will be described. In Fig. 14, bit 1 and bit 0 of the register designation field indicate that none of R0 to R9 is designated when "00", and that R0 to R4 when "01" is specified. When R5 to R9 is specified, R0 to R2, R5 and R6 are designated as "11". Here, R0 to R4 are group 1, and R5 to R9 are group 2, and R0 to R2, R5 and R6 are group 3. In the MOVM instruction of this embodiment, the batch designation field may designate any one of groups 1, 2, and 3 of the registers R0 to R9.

The configuration of the main part of the microcomputer according to the present embodiment is almost the same as the schematic block diagram shown in FIG. However, a part of the internal configuration of the register designation field decoder 105 is different because it decodes the register designation field of the two bits.

15 is a block diagram showing the internal structure of the register designation field decoder 105. As shown in FIG. The latch 300 is added, and the batch designation register number output sequencer 301 is provided in place of the batch designation register number output sequencer 206.

The latch 300 latches two bits of the batch designation field of the MOVM instructions at the time when the MOWM instruction is detected by the instruction decoder 101 and outputs the value to the batch designation register number output sequencer 301.

The batch designation register number output sequencer 301 uses the register numbers of R0 to R4 when the value of the batch designation field input from the latch 300 designates group 1, and R5 to R9 when the group 2 is designated. If group 3 is specified, register numbers R0 to R2, R5 and R6 are generated sequentially.

16 is a block diagram showing the internal structure of the batch designation register number output sequencer 301. As shown in FIG. In FIG. 16, the same reference numerals are given to the same components as those in FIG. 4, and detailed description thereof will be omitted.

The incrementer 302 has a different count from 0 to 4 with respect to the incrementer 209 of FIG. 4, and as shown in the input / output logic table of FIG. "000".

The register number conversion circuit 303 is output from the batch designation register number output sequencer 301 according to the group number indicated by the value of the batch designation field output from the latch 300, as shown in the input / output logic table in FIG. Count values are converted to register numbers in the group and output in order.

As described above, in the present embodiment, registers that can be designated collectively are divided into groups, so that a flexible program design can be made by designating an appropriate group according to the use.

In the first and second embodiments, the MOW instruction has been described as an example. However, the MOW instruction is not limited to the transfer instruction, but may be applied to an operation instruction that performs an operation between a plurality of registers and a continuous area of a memory. For example, when applied to an add instruction such as ADDM (SP), [R10-R15, etc.], the instruction decoder 101 adds register data and memory data to the operator group 103 and then transfers them to the memory. Control. This enables flexible program design, for example, updating data collectively for the table data in the memory.

In addition, the case where the present invention is applied to an instruction other than the above will be described with reference to FIGS. 17A and 17B. 17A and 17B are explanatory views showing the control procedure by the instruction decoder 101 in the case where the call instruction of the subroutine and the return instruction from the subroutine are applied to the present invention.

In FIG. 17A, the CALL (disp, PC), [R10-R15, etc.] instructions are instructions for calling a subroutine and for saving data from a plurality of registers onto a stack above the memory. The operands disp and PC represent the start address of the subroutine (obtained by adding the displacement to the value of the program counter PC (the instruction address of this instruction itself)). Another operand [R10-R15, etc.] represents the register data to be saved on the stack when making a subroutine call, and consists of the individual fields and batch fields already described.

In Fig. 17A, the register transfer in the portion (a0) indicates the stack save of the value of the program counter PC (the address of the return destination from the subroutine).

Part (a1) shows the stack save of the register specified by the individual field. In FIG. 17A, all registers are designated. However, if not specified, this register data is not saved.

Part (a2) shows the stack save of the register specified in the batch field. 17A shows a case where a batch field is designated, but if not specified, data of R0-R9 is not saved.

Part (a3) indicates updating the stack pointer (for stack securing).

The part (a4) indicates the update of the program counter, that is, the branch to the subroutine.

In Fig. 17B, RET, [R10-R15, etc.] are instructions for instructing data return from the stack to multiple registers and return from the subroutine. The operands [R10-R15, etc.] consist of the individual fields and the batch fields already described, and indicate register data to be returned from the stack at the end of the subroutine. Since it is used in conjunction with the above CALL instruction, the same register as the CALL instruction must be specified.

In Fig. 17B, part (b0) indicates an update (for stack opening) of the stack pointer.

Part (b1) indicates the update of the program counter PC, i.e., the return from the subroutine.

Part (b2) shows the stack return to the register designated by the individual field. 17B shows a case where all registers are designated, but if not specified, this register data is not saved.

Part (b3) indicates the stack return of the register designated by the batch field. Although FIG. 17B shows a case where a batch field is designated, the data of R0-R9 is not returned if it is not specified.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art may make various modifications, changes, substitutions, and additions through the spirit and scope of the present invention as set forth in the appended claims.

Claims (24)

In an information processing apparatus for executing a program, A register group composed of a plurality of registers; Decoding means for sequentially decoding a machine language instruction in a program to detect a predetermined machine language instruction, wherein the predetermined machine language instruction includes a first operand and a second operand, and includes a plurality of registers and a second operand designated as the first operand. Instructs data transfer between designated memories, and indicates whether the first operand individually specifies a register of a portion of the register individually, and whether to collectively specify a register of another portion of the register group. Decrypting means comprising a batch field, the second operand designating an effective address of the memory; Judging means for judging whether each bit is valid or invalid for the individual field and the batch field in the first operand of the detected machine language instruction; First generating means for generating a register number of a register corresponding to the bit determined to be valid in the respective field; Second generating means for sequentially generating register numbers of the other partial registers when it is determined to be valid in the batch field; And information transfer means for performing data transfer between a register of a register number generated by said first generation means and said second generation means and an effective address region designated by a second operand. Processing unit. The method of claim 1, The register group includes m + n registers, the individual field is composed of m bits corresponding to m registers individually, and the batch field is composed of 1 bit which collectively designates n registers. Device. The method of claim 2, The determination means, A latching means for latching the contents of the individual field and the contents of the batch field of the machine language instruction detected by the decryption means, the latch means for latching the contents of the individual field above the contents of the batch field; Bit detection means for detecting the first valid bit from the most significant bit (MSB) side of the latch means and outputting a position signal indicating the bit position to the first and second generating means; And a bit reset means for resetting bits detected by said bit detection means among bits latched by said latch means when data transfer for one register is made by said transfer means, The bit detecting means attempts the detection again after the reset, and the first and second generating means generate one register number based on the position signal in a data transfer cycle of one register. Processing unit. The method of claim 3, wherein And said first generating means generates a number of a register corresponding to a corresponding bit position among said m registers when said position signal indicates a bit position in an individual field. The method of claim 4, wherein The second generating means, Batch field determining means for determining whether the position signal indicates a bit position of a batch field among the latch means; And a continuous generating means for sequentially generating one register number in one transfer cycle for the n registers, when it is determined that the bit field of the batch field is indicated. The method of claim 5, wherein The second operand is assigned a stack pointer, And said transfer means performs data transfer between a register of a register number generated by said first and second generating means and a stack region designated by said stack pointer. The method of claim 1, The register group has m + n registers, The individual field consists of m bits corresponding to each of m registers. The batch field consists of at least 2 bits, And said second generating means sequentially generates a register number corresponding to a register group consisting of a plurality of predetermined registers of n registers according to a bit pattern of a batch field. The method of claim 7, wherein The determination means, A first latching means for latching the individual field and the batch field of the machine language instruction detected by said decrypting means, said first latch means for latching the individual field above the batch field; Second latch means for latching a batch field of a machine language command detected by said decrypting means; Bit detection means for first detecting a valid bit from the MSB side of the latch means and outputting a position signal indicating the bit position to the first and second generating means; And a bit reset means for resetting bits detected by said bit detection means among bits latched by said first latch means when data transfer for one register is made by said transfer means, The bit detecting means tries the detection again after the reset, the first generating means generates one register number based on the position signal in a data transfer cycle of one register, and the second generating means And one register number in one data transfer cycle for one register in accordance with the position signal and the contents of the second latching means. The method of claim 8, And said first generating means generates a number of a register corresponding to the corresponding bit position among said m registers when said position signal indicates the bit position of an individual field. The method of claim 9, The second generating means, Batch field determination means for determining whether the position signal indicates any one of the bit positions in the batch field; When it is determined that the bit field of the batch field is indicated, the register group is specified in accordance with the bit pattern of the second latching means, and one register number is sequentially generated in one transfer cycle for a plurality of registers in the register group. And a continuous generating means. The method of claim 10, The second operand is assigned a stack pointer, And said transfer means performs data transfer between a register of a register number generated by said first and second generating means and a stack region designated by said stack pointer. The method of claim 1, The machine language instruction further instructs an operation between a plurality of register data designated by a first operand and data in a contiguous memory area from an execution address designated by a second operand, The information processing device, And an operation means for executing an operation indicated by the machine language command, wherein the transmission means transmits an operation result of the operation means to the plurality of registers or the memory area. In an information processing apparatus for executing a program, A register group having m registers used as non-destructive registers that require data to be stored in the subroutine, and n registers used as destructive registers in the subroutine which do not need to be stored; Decoding means for sequentially decoding a machine language instruction in a program to detect a predetermined machine language instruction, wherein the predetermined machine language instruction includes a first operand and a second operand, and includes a plurality of registers and a second operand designated as the first operand. Instructs data transfer between designated memories, and consists of a separate field indicating whether the first operand individually specifies the m registers and a batch field indicating whether the n registers are collectively designated; Decoding means for the second operand to specify an effective address of the memory by the stack pointer; Determination means for determining whether each bit is valid or invalid for the individual field and the batch field in the first operand of the detected machine language instruction: First generating means for generating a register number of a register corresponding to the bit determined to be valid in the respective field; Second generating means for sequentially generating register numbers of the other partial registers when it is determined to be valid in the batch field; And information transfer means for performing data transfer between a register having a register number generated by said first generation means and said second generation means and a memory area contiguous from an effective address designated by a second operand. Device. The method of claim 13, And the machine language instruction includes a first transfer instruction for instructing transfer of data from a register to a memory and a second transfer instruction for instructing transfer of data from a memory to a register. The method of claim 14, The determination means, Latch means for latching an individual field and a batch field of the machine language instruction detected by the decryption means, the latch means for latching the individual field above the batch field; Bit detection means for detecting a first valid bit from the MSB side of the latch means and outputting a position signal indicating the bit position to the first and second generating means; And a bit reset means for resetting bits detected by said bit detection means among bits latched by said latch means when data transfer for one register is made by said transfer means, The bit detecting means tries the detection again after the reset, and the first and second generating means generate one register number based on the position signal in a data transfer cycle of one register. Processing unit. The method of claim 15, And said first generating means generates a number of a register corresponding to the corresponding bit position among said m registers when said position signal indicates the bit position of an individual field. The method of claim 16, The second generating means, Batch field determining means for determining whether the position signal indicates a bit position of a batch field among the latch means; And a continuous generating means for sequentially generating one register number in one transfer cycle for the n registers when it is determined that the bit field of the batch field is indicated. In an information processing apparatus for executing a program, A register group consisting of a plurality of registers; Decoding means for sequentially decoding machine language instructions in a program to detect predetermined machine language instructions, wherein the predetermined machine language instructions include at least a subroutine call instruction and a return instruction from the subroutine, each machine instruction specifying a plurality of registers. A separate field of register groups, including an operand, instructing data transfer between the multiple registers designated by this operand and the stack on top of the memory, and indicating whether the operand individually specifies each of a portion of a register group; Decrypting means comprising a batch field indicating whether a part of registers are collectively designated; Judging means for judging whether each bit is valid or invalid for the individual field and the batch field among the operands of the detected machine language instruction; First generating means for generating a register number of a register corresponding to the bit determined to be valid in the respective field; Second generating means for sequentially generating register numbers of the other partial registers when it is determined to be valid in the batch field; And transfer means for performing data transfer between a register on a memory and a register of a register number generated by said first and second generating means. The method of claim 18, The register group includes m + n registers, the individual field is composed of m bits corresponding to m registers individually, and the batch field is composed of 1 bit which collectively designates n registers. Device. The method of claim 19, The determination means, Latch means for latching the contents of the individual field of the machine language instruction and the contents of the batch field detected by the decryption means, so that the contents of the individual field are latched above the contents of the batch field; Bit detection means for detecting the first valid bit from the MSB side of the latch means and outputting a position signal indicating the bit position to the first and second generating means; And a bit reset means for resetting bits detected by the bit detection means among the bits latched by the latch means when data transfer for one register is made by the transfer means, The bit detecting means tries the detection again after the reset, and the first and second generating means generate one register number based on the position signal in a data transfer cycle of one register. Processing unit. The method of claim 20, And said first generating means generates a number of a register corresponding to a corresponding bit position among said m registers when said position signal indicates a bit position in an individual field. The method of claim 21, The second generating means, Batch field determining means for determining whether the position signal indicates a bit position of a batch field in the latch means; And a continuous generating means for sequentially generating one register number in one transfer cycle for the n registers, when it is determined that the bit field of the batch field is indicated. In an information processing apparatus including a register group, an information processing method for executing a predetermined machine language instruction having a first operand and a second operand, The first operand is composed of a separate field indicating whether or not each register of a part of the register group is individually designated and a batch field indicating whether or not a register of another part of the register group is collectively designated. A first operand designating step in which registers of? Are individually designated by the respective fields, and registers of other portions of the register group are collectively designated by the batch field; A second operand designating step in which an effective address of a memory is designated by the second operand; And an operation step of executing data transfer between a plurality of registers specified in said first operand specifying step and a memory specified in said second operand specifying step. The method of claim 23, The register group includes m registers used as non-destructive registers that require data to be preserved in subroutines, and n registers used as destructive registers in which data does not need to be preserved among subroutines. And said individual field is composed of m bits corresponding to said m registers, and said batch field is composed of 1 bit for collectively designating said n registers.