KR100379151B1 - Apparatus and method for executing a block data transfer instruction inside processor - Google Patents

Abstract

An apparatus and method for executing a block data transfer instruction inside a processor. The device can find the register to be processed and the corresponding address from the decryption information of the register list. By processing only the data in the specified registers, you can reduce the program code as well as the memory access cycle and improve the performance of the processor.

Description

Device and method for executing block data transfer instructions inside the processor {APPARATUS AND METHOD FOR EXECUTING A BLOCK DATA TRANSFER INSTRUCTION INSIDE PROCESSOR}

The present invention relates to an apparatus and method for executing instructions of a processor. More specifically, the present invention relates to an apparatus for executing a block data transfer command in a processor.

Processors are indispensable for many electronic devices. For example, every computer must have at least one central processing unit and various controllers require one or more specially functional processors. As powerful electronic equipment develops, the role that processors play becomes increasingly important.

One obvious solution to achieving higher performance is to reduce the clock cycle, ie increase the operating frequency. Another way to improve performance is to execute multiple instructions simultaneously in each cycle.

In the instruction list provided by the processor is one special purpose instruction that processes data in the entire register block. For example, one instruction can read and write data from an entire register block. As an example, if you execute an instruction using 16 register blocks, the processor must perform the same operation, such as transferring data, for each register in the list. This mode of operation is economical because all 16 registers contain data to be transferred, making full use of the processor's execution time. However, if the number of registers actually to be processed is less than 16 or as small as 1, then the rules for processing all 16 registers are very uneconomical and can reduce processing efficiency. On the other hand, using the prior art, at least 16 program codes are required to perform the transfer operation, which means that a longer size program code is required. Too much program code is consumed to carry out the transfer command.

Accordingly, it is an object of the present invention to provide a method and apparatus for executing a block data transfer command inside a processor. The device may find registers to be processed and corresponding addresses from the decryption information of the register list. By processing only the data in a specific register, the processor's execution cycle as well as the program code can be reduced. Thus, the performance of the program can be significantly improved.

1 is a block diagram illustrating an apparatus for executing a block data transfer command inside a processor according to a preferred embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operating state inside the register ID number generator shown in FIG. 1.

In order to achieve the above and other advantages according to the object of the present invention, the present invention provides an apparatus for executing a block data transfer instruction inside a processor, as will be described in detail and broadly below. The device may receive decryption information having at least N bits. The apparatus includes an adder, a counter, a register identification number generator, a memory unit and a register list. The adder receives the N bit decryption information and then adds all the bit values of the N bit decryption information to obtain an initial count value. The counter receives an initial count value. The initial count value is decremented by one each time it finds an N bit decryption information location whose bit value is '1'. The counter then outputs a counting control signal. In accordance with the count control signal, the register unique number generator generates a plurality of register unique numbers IDs equal to the initial count value. This register unique number corresponds to the location of the N bit decryption information with a value of '1'. The register list includes a plurality of registers. The register list receives a register unique (ID) number. According to the register unique number, data is freely transferred between the memory unit and the register corresponding to the register unique number.

The block data transmission apparatus further includes an address counter. The address counter generates an address signal according to the decryption information. The address signal is sent to the memory unit. Data is transferred between a register corresponding to a specific register ID number and a memory unit corresponding to a specific address signal.

The register ID number generator of the block data transfer apparatus further includes N logical units for generating the same number of register ID numbers as the initial count value. The counter subtracts one from the initial count until the initial count reaches zero. The N logic devices generate corresponding register ID numbers according to the position of the N bit decryption information whose bit value is '1'.

The present invention also provides a method of performing block data transfer inside the processor after receiving N bit decryption information. The method includes adding all N bits of the N bit decryption information to form an initial count value, and generating a plurality of register ID numbers equal to the initial count value. The register ID number corresponds to the position of N bit decryption information whose bit value is '1'. According to the register ID number, a plurality of registers and a memory unit corresponding to the register ID number are connected to freely exchange data in which the memory unit and the register are stored.

In the block data transfer method, the register ID number generating step further includes subtracting one from the initial count value each time the N bit decryption information position where the bit value is '1' is found. The counting operation decrements the initial value one by one until a zero value is obtained. After each decrement operation, the position of the N bit decryption information generates a register ID number depending on whether the bit value is '1' or not.

The block data transmission method further includes generating an address signal according to the decryption information. Thus, data is exchanged between a register corresponding to a specific register ID number and a memory location corresponding to an address signal.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to further explain the invention described in the claims.

The accompanying drawings are included to assist in a further understanding of the invention and are incorporated as part of this specification. The drawings, together with the description, illustrate embodiments of the invention and serve to explain the principles of the invention.

Example

Reference numerals are embodied in a preferred embodiment of the present invention and are shown in the accompanying drawings. Wherever possible, the same reference numbers are used to refer to the same or similar parts in the drawings and the description.

The present invention provides an apparatus for executing a block data transfer command and a method of operating the apparatus corresponding thereto. The device uses the decryption information in the register list to find the register number and addresses to be processed corresponding to the number. Ultimately, only the data in the specified register is processed while skipping the unspecified register.

1 is a block diagram illustrating an apparatus for executing a block data transfer command inside a processor according to a preferred embodiment of the present invention. In this embodiment, for example, a register list (RL) is selected that can handle block data transfer for 16 registers. As shown in Fig. 1, the decryption information in the RL together includes 16 bits. Although only 16 bits are included in FIG. 1 to process 16 registers, the actual number of bits that can be handled by the present invention and the corresponding number of registers are not limited. That is, the present invention can be extended to include data transfers for 32 or 64 registers.

First, the RL decryption information is sent to the adder 110. Inside the adder 110, all the bits in the RL decryption information are all added up. That is, the position number in the RL decryption information whose bit value is '1' is added to form the total value. The value is input to the counter 120 to serve as an initial count value. In fact, each bit number position whose bit value is '1' represents a register to be processed. For example, '1' of the first bit position starting from the right side of the RL decryption information indicates that the first register should be processed. In fact, the value entered into counter 120 is used to find the register number in the instruction required for processing. That is, the number of data transfers between the memory and the registers (the total time required to complete the data transfer depends on the hit rate of the memory) can be measured from the initial count value.

After each memory access and register store operation, counter 120 decrements one from the initial count value. The command is complete when the counter 120 decreases to zero. Thus, the counter 120 only needs 16 processes (the actual number is related to the number of registers required for the process depending on the decryption information).

Before counter 120 is zero, each operation generates a register ID number through register ID number generator 130. At the same time, the address counter 140 transmits the address data to the memory 150. Thereafter, the memory 150 transmits or receives data corresponding to the address. The data is transferred to the register corresponding to the register in the register list specified by the register ID. Alternatively, data is read from the register corresponding to the address in register address list 160 as specified by the register ID. All of this depends on whether data is read from or transferred to memory 150. Accordingly, the data exchange between the registers in the register address list 160 and the memory 150 starts according to the register ID generated by the register ID generator 130.

The above operation can be described with reference to FIG. 1. For example, counter 120 is a device capable of performing a reduction operation. In each operation, counter 120 outputs a coefficient control signal through cable 122 to control register ID generator 130. In accordance with the coefficient control signal, the register ID generator 130 may generate a register ID. Accordingly, according to the calculated address provided by the address counter 140 and the ID generated by the register ID generator, data in the register may be transferred to the memory between the registers in the register address list 160 corresponding to the generated register ID. Data in memory 150 corresponding to the calculated address may be transferred to a register corresponding to a register ID.

FIG. 2 is a flowchart showing an operating state inside the register ID number generator shown in FIG. Upon receiving the count control signal provided by the counter 120 over the cable 122, the register ID generator first determines whether the count value decreases to zero at step 210. If the count value is zero, the process is complete. However, if the count value is not zero, one or more registers remain in operation. In step 212, the first bit of RL decryption information is checked to see if the bit value is '1'. If the bit value in the position is '1', this means that the first register needs to be accessed from the register list. In step 213, a unique number of registers is set to facilitate access. In the example, ID = 0. The first bit of the register list is then set to '0' to avoid repetition. In other words, by setting the first bit of the register list to zero, the next count value does not operate again in the first register of the register list. Finally, the count value decreases by one.

Control returns to the initial state via path 220 to repeat step 210. Here, the coefficient value is queried again to determine whether zero has been reached. If a zero value appears, this means that the command is complete. On the other hand, if the count value is not yet zero, step 212 is executed to determine if the first bit of the register list has a value of '1'. Since the first bit position value has already been set to zero in the previous step 213, the next step 214 is executed. In step 214, the second bit of RL decryption information is examined to determine if the value is '1'. If the value of '1' is actually present in the second bit position, the register ID is set to the value of '1', i.e., ID = 1. Similarly, in step 215, the second bit position of the register list is set to zero to avoid repetition, and then decrement the count value by one. If the second bit position value of the RL decryption information initially contains '0', the third bit position value of the RL decryption information is examined to determine if operation of the third register is necessary. The process is repeated until the counter value of the counter 120 becomes zero. In fact, the number of iteration steps should be equal to the count value of the counter 120. Therefore, in the system of the above structure, the initial count value input to the counter 120 indicates the number of registers required for data transfer.

It will be apparent to those skilled in the art that various modifications may be made to the structure of the invention without departing from the spirit or scope of the invention. In view of the foregoing, it is intended that the present invention cover various modifications that fall within the scope of the following claims and their equivalents.

As described above, the present invention provides an apparatus for executing a block data transfer command inside a processor. The device can find the register to be processed and the corresponding address from the decryption information of the register list. By processing only the data in the specified registers, the processor execution cycle as well as the program code can be reduced. Thus, the performance of the processor can be significantly improved.

Claims (6)

An apparatus for executing a block data transfer instruction inside a processor after receiving decryption information including N bits, the apparatus comprising: The device An adder that receives the N bit decryption information and adds all of the N bits to produce an initial count value; A counter for receiving the initial count value and outputting a count control signal and then decreasing the value by one; A register unique number generator for generating a plurality of register unique numbers corresponding to bit positions in which the bit value of the N bit decoding information equal to an initial coefficient value is '1' according to the coefficient control signal; A memory unit for holding data; And And a register list including a plurality of register data and allowing a register list to receive the register unique number and to freely exchange data stored between a memory unit and a register having the corresponding register unique number. The method of claim 1, Generating an address signal according to the decryption information and outputting the address signal to the memory unit so that data can be freely exchanged between a register corresponding to the register unique number and an addressable memory in the memory unit according to the address signal; And a block data transfer instruction execution device further comprising an address counter. The method of claim 1, The register unique number generator Generate a register unique number equal to the initial count value and generate a register unique number according to the bit position of the N bit decryption information with a bit value of '1' until the counter is decremented to zero. And a block data transfer instruction execution device further comprising an N logical unit. A method for executing a block data transfer command in a processor after receiving N bit decryption information, the method comprising: Adding all N bits to form an initial count value; Generating a plurality of register unique numbers corresponding to bit positions of the N bit decoding information information having the same number of bit values as '1'; And Connecting a plurality of registers corresponding to the register unique number and a memory unit according to the register unique number to freely exchange data stored between the memory unit and the register; Block data transfer command execution method comprising a. The method of claim 4, wherein Generating the register unique number Performing a coefficient reduction operation of decreasing the initial count value by one until the initial count value becomes zero; And And generating a register unique number each time a bit value '1' is found in the N bit decoding information after each count reduction operation. The method of claim 4, wherein Generating an address signal according to the decryption information so that data stored in a register according to a register unique number and data in a memory unit having an address according to the address signal can be exchanged with each other; .