JPH02100175A - Vector processor - Google Patents

Abstract

PURPOSE:To shorten computing time when the storage of the arithmetic results is continuous to the same vector register by selecting and checking a flag that is controlled in the timing corresponding to the number of pipeline steps of each computing element. CONSTITUTION:When the computing element to be used with an instruction which is decoded at an instruction control part 2 is equal to an adder 11, a short write busy A flag 33 is selected. In the same way, a short write busy L flag 32, a short write busy M flag 34, and a write busy flag 31 are respectively selected with a logical computing element 12, a multiplier 13, and a computing element 14 which starts a storing action to a designated vector register right after the execution of an instruction is instructed. These selected flags are checked by a write busy check circuit 23, and these check results are set to an instruction execution instructing circuit 24. Then an instruction executing instruction is sent to an instruction executing part 1. Thus the storage of the arithmetic results is continuously carried out to the vector register and the total computing time is shortened.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention comprises an instruction execution unit composed of a plurality of vector registers and a plurality of arithmetic units with different numbers of pipeline stages, and an instruction execution unit that decodes instructions to be executed and generates information for instruction execution. The present invention also relates to a vector processing device comprising an instruction control section that instructs the execution of instructions while managing the states of resources such as vector registers and arithmetic units of the instruction execution section. [Prior art 1] Conventionally, this type of vector processing device sends an instruction execution instruction to an instruction execution unit and at the same time sends a flag (hereinafter referred to as read busy flag) indicating that a vector register that provides an operand of the instruction is being read. , sets a flag (hereinafter referred to as write busy flag) indicating that the calculation result is being stored in the specified vector register,
The state of the instruction execution unit is checked by checking these flags before sending a subsequent instruction execution instruction. Wait, and then send an instruction execution instruction after it is released. The arithmetic unit of the instruction execution unit performs addition, subtraction, 2 multiplication,
They each have functions such as logical operations and shift operations, and can operate on one element data of a vector register every clock in a pipeline configuration, and the number of pipeline stages generally differs depending on the operation function. Therefore, for an instruction that uses an arithmetic unit with a large number of pipeline stages, the write busy period from the instruction execution instruction becomes longer. In particular, as shown in Figure 3, the designation of the vector register that stores the calculation result used in the instruction execution unit is the designation of the vector register that should store the calculation result in the instruction that is checked in the instruction control unit. If it matches, the write busy of the vector register storing the operation result in the instruction execution unit is released, and then the instruction to execute the subsequent instruction is sent to the instruction execution unit, and the operation used in the subsequent instruction is By starting to store the operation result in the designated vector register after a clock period corresponding to the number of pipeline stages of the device, storage in the vector register was interrupted, resulting in idle time. Therefore, as shown in Figure 4, if an instruction that uses the smallest number of pipeline stages among various arithmetic units follows, it will be shorter than Write and G-Flag by 2092 equivalent to the minimum number of pipeline stages. If a flag (hereinafter referred to as the short write busy flag) is set from the execution instruction of each instruction, the reset of this flag is checked, and the execution instruction of the subsequent instruction is sent to the instruction execution unit, the storage of the operation result will not be interrupted. You can control it so that it doesn't need to be used. but,
As shown in Figure 5, when an instruction that uses an arithmetic unit with more pipeline stages follows, if the reset of the short write busy flag is checked and an instruction execution instruction is sent to the instruction execution unit, the operation result will be The storage of the data is interrupted and idle time is created. [Problems to be Solved by the Invention] When the above-described conventional vector processing device executes consecutive arithmetic instructions in which the same vector register designation for storing the arithmetic result is executed, the pipe of the arithmetic unit to be used in the subsequent instruction is The larger the number of line stages, the longer the calculation time will be as a result of the storage of the result of the preceding calculation and the storage of the result of the subsequent calculation, where no calculation result will be obtained, and the longer the calculation time will be. There are drawbacks. [Means for Solving the Problems 1] The vector processing device of the present invention is provided in correspondence with a plurality of arithmetic units for each of a plurality of vector registers, and indicates that an arithmetic result is being stored in a designated vector register. A plurality of short write busy flags are reset at a timing earlier than the write busy flag by a clock equivalent to the number of pipeline stages of the arithmetic unit, and the short write busy flag is selected according to the arithmetic unit to be used for the instruction being decoded in the instruction control unit. It has a selector, a check circuit that checks a selected short write busy flag, and an instruction execution instruction means that sends an instruction to execute a subsequent arithmetic instruction to an instruction execution section when the short write busy flag is reset.

[Effect]

Therefore, the designation of the vector register that is storing the operation result of the instruction being executed by the instruction execution unit and the designation of the vector register that should store the operation result of the instruction that is being decoded by the instruction control unit match, and the instruction execution unit Even if the number of pipeline stages of the arithmetic unit used by the instruction being executed is greater than the number of pipeline stages of the arithmetic unit that should be used for the instruction being decoded by the instruction control unit, the number of pipeline stages of the arithmetic unit used by the instruction being executed is The storage of the calculation result and the storage of the calculation result of the instruction being decoded by the subsequent instruction control unit can be performed continuously. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the vector processing device of the present invention, FIG. 2 is an explanatory diagram of flags when an addition instruction is executed, and FIG. Diagram when referring to busy flag 31,
Figure 4 shows that the subsequent instruction is an instruction using a logical operation unit, and the short write busy flag is 3 when checking the instruction execution instruction sending.
2 is checked. Figure 5 is a diagram when the subsequent instruction uses a multiplier and the short write busy flag 32 is checked when checking the instruction execution instruction sending.
This figure is a diagram explaining all the flags when an addition instruction is executed, and FIG. 7 is a diagram showing a case where the subsequent instruction uses a multiplier and the short busy M flag 34 is checked when checking the sending of an instruction execution instruction. This embodiment consists of an instruction execution section 1 and an instruction control section 2. The instruction execution unit 1 includes vector registers R0 to R7 having a plurality of entries, a crossbar switch IO, and an adder 1.
1, a logical arithmetic unit 12, a multiplier 13, and an arithmetic unit 14. Adder 11, logical operator 12. The number of pipeline stages of the multiplier 13 and the arithmetic unit 14 is unique to each arithmetic unit; It is assumed that the number of pipeline stages increases in the order of the adder ratio logical operator 13. It is assumed that the arithmetic unit 14 starts storing data in a designated vector register immediately after being instructed to execute an arithmetic instruction. The instruction control unit 2 includes an instruction register 20, a decoding circuit 21,
Read busy flag 30 and write busy flag 3
1, short write busy flag 32, short write busy A flag 33, short write to G flag 34, selector circuit 25, read busy check circuit 22, and write busy check circuit 23.
and an instruction execution instruction circuit 24. The read busy flag 30 indicates that a vector register providing the operand of the instruction being executed is being read, and is reset when the read is completed. light and g-
The flag 31 indicates that the calculation result is being stored in the designated vector register, and is reset when the storage in the designated vector register is completed. As shown in FIG. 2, the short write busy flag 32 is reset at a timing earlier than the write busy flag 31 by a clock equivalent to the number of pipeline stages of the logical operator 12, which has the shortest pipeline stage among the various arithmetic units. . The short write busy A flag 33 is reset at a timing earlier than the write busy flag 31 by a clock corresponding to the number of pipeline stages of the adder 11. The short write-to-G flag 34 is reset at a timing earlier than the write busy flag 31 by a clock corresponding to the number of pipeline stages of the multiplier 13. Conventionally, the read busy check circuit 22 uses a read busy flag 30 to check whether the designation of the vector register that provides the operand in the instruction being decoded by the instruction control unit 2 matches the designation of the vector register from which the instruction being executed is being read. Similarly, the write busy flag 31 is used to detect a match between the designation of the vector register in which the calculation result is to be stored by the instruction being decoded and the designation of the vector register in which the calculation result is stored by the instruction being executed. Check circuit 23
Based on these results, the instruction execution instruction circuit 24 sends an instruction execution instruction to the instruction execution unit l. Therefore, when the designation of the vector register that is storing the result of the instruction being executed matches the designation of the vector register that is to store the operation result of the instruction that is being decoded by the instruction control unit 2,
As shown in FIG. 3, the instruction execution unit 1 is storing the addition result of vector registers Ro and R+ in vector register R2, and the subsequent instruction stores the logical operation result of vector registers R2 and Rs in vector register R1. If it is an instruction, write busy flag 3 of vector register R1
1 is reset, an instruction to execute a subsequent logical operation instruction can be sent to the instruction execution unit 1. So vector register R? The calculation results cannot be stored continuously, resulting in empty time. Furthermore, if the write busy check circuit 23 does not use the write busy flag 31 but uses the short write busy flag 32, as shown in FIG. 4, if the same calculation as in FIG. 3 is performed, the vector The calculation results can be stored continuously in the register Ry. However, as shown in FIG.
7, and the subsequent instruction is being stored in vector register R4.
, Rs, the flag to be checked by the write busy check circuit 23 is set to short write and gihi flag 32.
In this case, since the number of pipeline stages of the multiplier 13 is larger than the number of pipeline stages of the logical operator 12, the storage of the operation results to the vector register R1 is not continuous, and empty time occurs again. In order to solve the above problems, as shown in Figure 6,
In addition, short write busy A occurs when an instruction execution instruction is sent.
Flag 33. The short write busy M flag 34 is set so as to be reset earlier than the write busy flag 31 by a clock corresponding to the number of pipeline stages of each arithmetic unit, and this is set for each vector register. As shown in FIG. 1, these flags are selected by the selector circuit 25 according to the number of pipeline stages of the arithmetic unit to be used for the instruction being decoded in the instruction control unit 2, and the selected flags are transferred to the write and g-check circuits. Check on 23,
The result is sent to the instruction execution instruction circuit 24, and an instruction execution instruction is sent to the instruction execution section 1. That is, if the arithmetic unit to be used for the instruction being decoded by the instruction control unit 2 is the adder 11, the short write busy A flag 33 is set, and if it is the logical arithmetic unit 12, the short write busy flag 3 is set.
2, short write busy M if multiplier 13
In the case of [4], an arithmetic unit that starts storing the flag 34 into a designated vector register immediately after an instruction execution instruction is issued, the write busy flag 31 is selected. For example, vector registers Ro, R as shown in FIG.
The + addition result is being stored in vector register R7,
If the subsequent instruction is an instruction to store the multiplication result of the vector register R4゜Rs in the vector register Ry, the short write and G flag 34 is selected from the number of pipeline stages of the multiplier 13.
The flag is checked, and an instruction execution instruction is sent from the instruction execution instruction circuit 24 to the instruction execution unit 1. As a result, the operation results are continuously stored in the vector register R1. [Effects of the Invention] As explained above, the present invention is capable of controlling the pipeline of each arithmetic unit at a timing corresponding to the number of pipeline stages of each arithmetic unit, depending on the number of pipeline stages of the arithmetic unit to be used for the instruction being decoded. By selecting and checking the flag, even if the storage of calculation results to the same vector register is specified consecutively, the calculation results can be stored without interruption.
Even when the number of pipeline stages of the arithmetic unit to be used in the subsequent instruction is larger than the number of pipeline stages of the arithmetic unit used in the preceding instruction, the storage of the operation result is performed without interruption, and therefore the same vector If the storage of calculation results in registers is specified consecutively, the overall calculation time can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the vector processing device of the present invention, FIG. 2 is an explanatory diagram of flags when an addition instruction is executed, and FIG. Diagram when referring to busy flag 31,
Figure 4 shows that the subsequent instruction is an instruction using a logical operation unit, and the short write busy flag is 3 when checking the instruction execution instruction sending.
2 is checked. Figure 5 is a diagram when the subsequent instruction is an instruction using a multiplier and the short write and gee-hi flag 32 are checked when checking the sending of an instruction execution instruction.
This figure is a diagram explaining all the flags when an addition instruction is executed, and FIG. 7 is a diagram showing a case where the subsequent instruction uses a multiplier and the short busy M flag 34 is checked when checking the sending of an instruction execution instruction. 1......Instruction execution unit 2...Instruction control unit R0-R1...Vector register 10...Crossbar switch++ ...
...... Adder 12 ...... Logical operator 13 ... Multiplier 14 ...... Arithmetic unit 20 ......Instruction register 21...
...Decode circuit 22 ... Read busy check circuit 23 ... Write busy check circuit 24 ...... Instruction execution Indication circuit 30...Read busy flag 31...Write busy flag 32
・・・・・・・・・・Short write busy flag 33・・・・・・・・Short light and G-A flag 34・・・・・・・・・・Short write busy M
Flag 4g1ff turret display 2nd command Ry-RO+R+ ~-R2JR3 command R7-f% + R. R7-R4*R5 Every minute R7←RO+R electric R7◆-R2LFb 4 Now R7-R, +R.

Claims (1)

[Claims] 1. An instruction execution unit composed of a plurality of vector registers and a plurality of arithmetic units with different numbers of pipeline stages, and a read busy flag indicating that a vector register providing an operand of an instruction is being read. It includes a write busy flag indicating that the operation result is being stored in the specified vector register, decodes the instruction to be executed, generates information for instruction execution, and stores the instruction execution unit's vector register and arithmetic unit. In the vector processing device, each of the plurality of vector registers is configured to correspond to the plurality of arithmetic units. is provided to indicate that the operation result is being stored in the specified vector register,
a plurality of short write busy flags that are reset at a timing earlier than the write busy flag by clocks corresponding to the number of pipeline stages of the arithmetic unit; and a plurality of short write busy flags that are reset by the arithmetic unit to be used for the instruction being decoded in the instruction control unit. A selector for making a selection, a check circuit for checking a selected short write busy flag, and an instruction execution instruction means for sending an instruction to execute a subsequent arithmetic instruction to an instruction execution section when the short write busy flag is reset. A vector processing device comprising: