JPH0690712B2 - Vector processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to an instruction processing unit including a plurality of vector registers and a plurality of arithmetic units, and information for executing an instruction by decoding an instruction to be executed. And a command decoding instruction unit for instructing execution of an instruction while managing the states of the vector register and the arithmetic unit of the instruction processing unit.

[Conventional technology]

Conventionally, a vector processing device of this type sends a command execution instruction to a command processing unit and, at the same time, a flag indicating that the vector register giving the operand of the command is being read (hereinafter referred to as a read busy flag), a calculation result. Is stored in the vector register indicating the operation unit that supplies the operation result (hereinafter referred to as the function flag), and the flag indicating that the operation result is being stored in the specified vector register (hereinafter referred to as the write busy flag). ) Is set, and these flags are checked before sending the subsequent instruction execution instruction, the status of the instruction processing unit is checked, and if the instruction execution instruction is not busy, the instruction execution instruction is sent. Waits until it is released, and then releases the instruction execution instruction. The operation unit of the instruction processing unit is
It has functions such as addition and subtraction, multiplication, logical operation, shift operation, etc., and can generally operate one element data of a vector register every one clock in a pipeline configuration, and the number of pipeline stages generally differs depending on the operation function. Therefore, the write busy period from the instruction execution instruction becomes longer as the instruction using the arithmetic unit having the larger number of pipeline stages is used. In particular, the specification of the vector register that stores the operation result used in the instruction processing unit matches the specification of the vector register that should store the operation result in the instruction that is being checked because it is instructed by the instruction decoding instruction unit. If it is, the instruction execution instruction is issued except that the instruction used by the instruction processing section and the instruction decoding instruction section specify the same operator to be used for the instruction being checked. The instruction execution instruction could not be sent until the write busy of the vector register that is storing the operation result is released, even if the busy of the arithmetic unit to be used and the vector register to be read has already been released. .

[Problems to be Solved by the Invention]

In the above-described conventional vector processing device, when the specification of the vector register for storing the calculation result is the same, and when consecutive calculation instructions using different calculation units are executed, the result of the preceding calculation is stored and the write busy of the vector register is reduced. Since the instruction to execute the subsequent instruction is sent to the instruction processing unit after it is canceled, there is a vacant time in which the operation result cannot be obtained between the preceding operation and the subsequent operation, resulting in a delay in the operation time as a whole. .

[Means for Solving the Problems]

In the vector processing device of the present invention, the designation of the vector register that is storing the result of the instruction being executed by the instruction processing unit and the designation of the vector register that should store the operation result of the instruction being decoded by the instruction decoding instruction unit match. And a pipeline stage number of the arithmetic unit outputting the result of the instruction being executed by the instruction processing unit, and a pipeline stage number of the arithmetic unit used by the instruction being decoded by the instruction decoding instruction unit. And a means for detecting the end of the reading of vector data that is supplying data to the arithmetic unit by the instruction being executed in the instruction processing unit, a coincidence of the designation of the vector register is detected, and a subsequent instruction If the number of pipeline stages of the arithmetic unit used in the above is greater than or equal to the number of pipeline stages of the arithmetic unit used in the preceding instruction, the instruction being executed by the instruction processing unit is supplying data to the arithmetic unit. Reading of torque registers and means for sending the instruction processing unit to execute instructions of the instruction being decoded by the time of completion.

[Action]

Since the execution instruction of the instruction being decoded is sent to the instruction processing unit when the reading of the vector register that is supplying data to the arithmetic unit by the instruction being executed by the instruction processing unit is completed, the operation time can be shortened.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the vector processing device of the present invention, and FIG. 2 is each busy flag 22, 2 when executing an add instruction.
FIG. 3 is a diagram showing the states of 3, 24, and FIG. 3 shows each flag 22, 23, by the conventional method when the multiply instruction is executed subsequently to the add instruction.
FIG. 4 is a diagram showing the state of 24, and FIG. 4 shows each flag 22, 23, 24 in the present embodiment in the case of executing a multiply instruction following an add instruction.
It is a figure which shows the state of.

This embodiment comprises an instruction processing unit 1 and an instruction decoding instruction unit 2. The instruction processing unit 1 is composed of vector registers R _{0 to} R ₅ , arithmetic units 10 to 12, and a crossbar switch 13. In this case, the arithmetic units 10, 11 and 12 are an adder, a multiplier and a logical arithmetic unit, respectively, and the number of pipeline stages is unique to each arithmetic unit. Here, it is assumed that the number of pipeline stages of the multiplier 11 is equal to or larger than the number of pipeline stages of the adder 10. The instruction decoding instruction unit 2 includes an instruction register 20, a decoder circuit 21, a function flag 22, a write busy flag 23, a read busy flag 24, a pipeline stage number comparison circuit 25, and a result storage register match detection circuit 26. A write busy check circuit 27, a read busy check circuit 28, a preceding instruction read busy reset detection circuit 30, a NAND circuit 31, an AND circuit 32, and an instruction execution instruction circuit 29. The decoder circuit 31 decodes the instruction in the instruction register 20. Function flag
22 is composed of an adder flag 22 ₁ , a multiplier flag 22 ₂ and a logical operation unit flag 22 ₃ , and the flag is set to the bit indicating the vector register number in which the operation unit stores the result when executing the operation, and It is reset when you supply the last entry in the vector. Light busy flag
23 indicates that the operation result is being stored in the specified vector register, and is reset when the storage of the operation result in the specified vector register is completed. The read busy flag 24 indicates that the vector register giving the operand of the instruction being executed is being read, and is reset when the reading is completed. The pipeline stage number comparison circuit 25 receives information on which arithmetic unit is being used in execution of the preceding instruction from the function flag 22, reads the pipeline stage number from a table, etc., and the pipeline stage number of the subsequent instruction is the decoder circuit. Obtained from the decode information of 21, the number of pipeline stages of the subsequent instruction is compared with the number of pipeline stages of the preceding instruction, and when the number of pipeline stages of the subsequent instruction is equal to or greater than the number of pipeline stages of the preceding instruction, "1" is output. The result storage register designation coincidence detection circuit 26 outputs "1" when it detects from the write busy flag 23 and the decoding information that the designations of the vector registers for storing the operation results of the preceding instruction and the succeeding instruction match. The preceding instruction read busy reset detection circuit 30 receives information indicating which arithmetic unit is used by the preceding instruction from the function flag 22, and when the read busy flag 24 is reset, the reading of the preceding instruction from the vector register ends. As a result, "1" is output. Light busy check circuit
27 and the write busy check circuit 28 check from the information of the write busy flag 23 and the read busy flag 24, respectively, that there is no conflict with the designation of the vector register to be used for reading in the subsequent instruction. The NAND circuit 31 includes a pipeline stage number comparison circuit 25 and a result storage register match detection circuit 2
6, AND of each output of the preceding instruction read busy reset detection circuit 30. The AND circuit 32 ignores the write busy of the write busy check circuit 27 when the output of the NAND circuit 31 is "1". The instruction execution instruction circuit 29 is a decoder circuit
21 output, AND circuit 32 output, and write busy check circuit 28 output are input, and when both the AND circuit 32 output and the write busy check circuit 28 output are "0", an instruction execution instruction is sent to the instruction processing unit 1. Send out.

Next, the operation of this embodiment will be described.

For example, instruction decode instruction unit 2 performs addition of the contents of the vector register R ₀ and R ₁ to the instruction processing unit 1, when conducted a command instruction to store the result in the vector register R _5, shown in Figure 2 Thus, the read busy flag 24 of the vector registers R ₀ and R ₁ , the function flag 22 ₁ of the adder 10 and the write busy flag 23 of the vector register R ₅ are set. The instruction processing unit 1 adds the contents of the vector registers R ₀ and R ₁ and stores the result in the vector register R ₅ . During execution of this addition in the instruction processing unit 1, the instruction decoding instruction unit 2 is connected to the vector register R ₂ and
Assuming that an instruction for multiplying each content of R ₃ and storing the result in the vector register R ₅ is input, the instruction decoding instructing unit 2 causes the vector register R _{5 to} read as shown in FIG.
The storage of the subsequent instruction (R ₅ ← R ₂ × R ₃ ) in the vector register R ₅ does not resume until T ₁ after the storage of the operation result in is completed. This is because the write busy flag 23 of the vector register R ₅ due to the preceding instruction is reset, and after checking this, to send the execution instruction of the succeeding instruction, the clock time corresponding to the pipeline stage number of the arithmetic unit used in the succeeding instruction or more, This is because new data is not sent to the vector register R ₅ . For this reason, the calculation time was slow as a whole. The purpose of the present invention is to shorten T ₁ .

In this embodiment, the preceding instruction read busy reset detection circuit 30 knows the time when the reading of the preceding instruction from the vector register is completed. This is the function flag 22
The vector register that finds the arithmetic unit that sets and supplies the vector data to the arithmetic unit can be uniquely known from the structure of the instruction processing unit 1. Since it can be seen that the vector register R ₅ of the adder flag 22 ₁ is set and the vector registers supplying the vector data to the adder 10 by the preceding instruction are R ₀ and R ₁ , vector register R ₀ , detects the lead busy reset R _1,
At this time, the preceding instruction read reset detection circuit 30 outputs "1". At this time, since the outputs of the pipeline stage number comparison circuit 25 and the result register coincidence detection circuit 26 are both "1", the output of the NAND circuit 31 becomes "0" and the write of the vector register R ₅ of the write busy check circuit 27. Busy is ignored by AND circuit 32. As a result, as shown in FIG. 4, the instruction execution instruction circuit 29 causes the read busy check circuit 28 to confirm that the subsequent instructions R ₅ ← R ₂ × R ₃ are not write busy for the vector registers R ₂ and R _3. It is checked and an instruction execution instruction is sent to the instruction processing unit 1.

Therefore, according to the present embodiment, the time T ₁ can be shortened as shown in FIG. 4 as compared with the time T ₁ shown in FIG. 3, and thereby the calculation time as a whole is also shortened.

If the number of pipeline stages of the arithmetic unit used in the preceding instruction is equal to the number of pipeline stages of the arithmetic unit used in the subsequent instruction and the vector registers for storing the calculation results are also the same, the time T ₁ is completely It can be easily inferred that it will disappear.

〔The invention's effect〕

As described above, the present invention compares the result of the instruction being executed by the instruction processing unit with the number of pipeline stages of the outputting arithmetic unit,
When the number of pipeline stages of the arithmetic unit used by the instruction being decoded by the instruction decoding instruction unit is equal or large, the reading of the vector register supplying data to the arithmetic unit by the instruction being executed by the instruction processing unit is completed. By sending the instruction execution instruction of the instruction being decoded to the instruction processing unit at the point of time, when executing consecutive instructions that store the operation result in the same vector register, the number of pipeline stages of the arithmetic unit used in the subsequent instruction precedes If the number of pipeline stages is greater than or equal to the number of pipeline stages used in an instruction, the operation time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the vector processing device of the present invention, and FIG. 2 is each busy flag at the time of executing an add instruction.
Fig.3 shows the states of 22,23,24, and Fig.3 shows each flag by the conventional method when executing a multiply instruction followed by a multiply instruction.
FIG. 4 is a diagram showing the states of 2, 23, and 24, and FIG. 4 shows each flag 2 in the present embodiment in the case of executing a multiply instruction following an add instruction
It is a figure which shows the state of 2,23,24. 1 ...... instruction processing unit, 2 ...... instruction decode instruction unit, R ₀ to R ₅ ...... vector register, 10 ...... calculator (adder), 11 ...... calculator (multiplier), 12 ...... calculator (Logical unit), 13 …… Crossbar switch, 20 …… Instruction register, 21 …… Decoder circuit, 22 …… Function flag, 22 ₁ …… Adder flag, 22 ₂ …… Multiplier flag, 22 ₃ …… Logic operation unit flag, 23 …… Write busy flag, 24 …… Read busy flag, 25 …… Pipeline stage number comparison circuit, 26 …… Result storage register specified match detection circuit, 27 …… Write busy check circuit, 28 …… Read busy check circuit, 29 ... Instruction execution instruction circuit, 30 ... Leading instruction read busy reset detection circuit, 31 ... NAND circuit, 32 ... AND circuit.

Claims (1)

[Claims] 1. An instruction processing unit composed of a plurality of vector registers and a plurality of arithmetic units, and an instruction to be executed is decoded to generate information for instruction execution. In a vector processing device having an instruction decoding instruction unit for instructing the execution of instructions while managing the state of the device, the specification of the vector register storing the result of the instruction being executed in the instruction processing unit and the instruction Means for detecting that the specification of the vector register for storing the operation result of the instruction being decoded in the decoding instruction unit matches, and a pipeline stage of the arithmetic unit outputting the result of the instruction being executed in the instruction processing unit And means for comparing the number of pipeline stages of the arithmetic unit used by the instruction being decoded by the instruction decoding instruction unit, and supplying data to the arithmetic unit by the instruction being executed by the instruction processing unit. Means for detecting the end of the reading of the vector data, and the coincidence of the designation of the vector register is detected, and the pipeline stage number of the arithmetic unit used in the subsequent instruction is equal to or more than the pipeline stage number of the arithmetic unit used in the preceding instruction. In this case, there is provided means for sending an execution instruction of the instruction being decoded to the instruction processing unit when the reading of the vector register supplying data to the arithmetic unit by the instruction being executed by the instruction processing unit is completed. A characteristic vector processing device.