JPS62232706A - Erasing device - Google Patents

Abstract

PURPOSE:To confirm a bit of inormation to be erased, by providing a means which reproduces the bit of information to be erase corresponding to the detection of the first erase command input by the first detecting means. CONSTITUTION:In an initial process when an erase standby switch 77 is turned on, a PB mode flag is set when no PB mode flag is set. By the setting of the flag, switches SW2 and SW3 are operated, and a reproduction is performed by connecting either a head 3-1 or 3-2 to a reproducing amplifier 6. Thus, since the reproduction of the bit of information to be erased corresponding to the first erase command input is performed, the bit of information to be erased can be confirmed.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention particularly relates to an erasing device for erasing information recorded on a recording medium.

<Prior Art> Conventionally, recording/reproducing apparatuses have been considered in which a recording/reproducing head is provided separately from an erasing head, or a recording/reproducing head is provided in combination with an erasing head. Conventionally, in such a device, when performing an erasing operation, the recording/reproducing head is moved to the track to be erased on the recording medium, and regardless of whether the operating mode at that time is the recording mode or the reproduction mode, By pressing the erase button, the erase operation was performed immediately.

<Problems to be Solved by the Invention> However, since the above-mentioned device performs the erasing operation with only one erasing command, there is a problem in that it is highly susceptible to erasing another track by mistake. Ta.

The present invention aims to solve such problems.

Means for Solving Problems> In order to achieve the above-mentioned objects, the present invention includes a first detection means for detecting a first erasure command input, and a first detection means for detecting a first erasure command input. a second detection means for detecting a second erasure command input in a state in which the second erasure command is detected; an erasing means for erasing information recorded on the recording medium based on a detection result of the second detection means; and reproduction means for reproducing information to be erased by the erasing means in response to detection of a first erasure command input by the first detection means.

Effect> In the above configuration, in the first state where the first erasure command input is obtained, erasure is performed only when the second erasure command input is obtained, and in the first state, the The information erased by the erasing means is reproduced. Therefore, the user should confirm the information to be erased in the first state by reproducing the information and displaying it on a monitor, for example. In the embodiments of the present invention, a recording and reproducing apparatus for recording still image video signals on a disk-shaped recording medium, specifically, a disk-shaped magnetic sheet, or reproducing the recorded still image video signals, will be described.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, l is a magnetic sheet on which the recording/reproducing track of the video signal, the track pitch, and the track position are determined in advance. In the case of a frame video signal, one field of video signal is recorded on each of two adjacent tracks to form a frame video signal. The magnetic sheet l is placed in a jacket (not shown) in advance, and the jacket is provided with a claw to prevent accidental erasure. 2.
is a DC motor for rotating the magnetic sheet l at a constant speed, 3
-1.3-2 is an inline type head that accesses two adjacent tracks, 3-1 accesses the outer circumferential side, and 3-2 accesses the inner circumferential side. 4 is a magnetic head 3-1.3-2
A magnetic head moving mechanism 5 moves the magnetic head 3-1 so as to access the track formed on the magnetic sheet l, and a magnetic head moving mechanism 5 moves the magnetic head 3-1 by the magnetic head moving mechanism 4 to access the innermost track on the magnetic sheet l. The state switches from off to on, and the microcomputer (hereinafter CP
(referred to as U) 40 is an innermost detection switch that outputs an L level signal, 6 is a reproducing amplifier for amplifying the signal detected by the magnetic head 3-1.3-2, and 7 is a signal from the reproducing amplifier 6. Level detector for detecting the average value of the output signal, 8
is a comparator that detects whether the output of the level detector 7 is higher than a threshold value set by a reference voltage source (not shown);
9 is a demodulation circuit for demodulating the output signal of the reproduction amplifier 6, lO
is a 1/2H delay circuit 1 that delays the output of the demodulation circuit 9 by 1/2 horizontal scanning period (hereinafter referred to as 1/2H);
1 is the horizontal synchronizing signal Hs y n from the output of the demodulation circuit 9
c, a synchronization signal separation circuit that separates synchronization signals such as the vertical synchronization signal Vsync; and 12, a synchronization signal separation circuit that detects a predetermined data signal from the output of the reproduction amplifier 6 in accordance with the timing of the synchronization signal separated from the synchronization signal separation circuit II. A data demodulator demodulates the data signal. The data signal is a signal for determining what kind of information is recorded on the track, for example, whether it is a field video signal or a frame video signal, and a signal for the date set by the user. , is a signal indicating an 11-digit number freely set by the user, and is recorded in a frequency band lower than that of the video signal at a position having a predetermined relationship with the part where the synchronization signal of the track is recorded. The reason why the demodulation circuit 9 and the data demodulation circuit 12 are provided separately here is as follows. That is, the video signal recorded on the magnetic sheet 1 is FM modulated, but data signals other than the video signal are FM modulated.
, 'i is a DPSK modulation method different from
ialP h a se S h f t K
e y i n g ) has been adopted. Therefore, the demodulation circuit 9 described above is an FM demodulation circuit, and the data demodulation circuit 1
2 is a DPSK demodulation circuit.

+3 is a monitor that reproduces the video signal so that it can be observed, and 13' is a printer that is connected to print the video signal. The printer 13' starts operating when the signal at the start signal input terminal becomes H level, and during operation, the busy signal output terminal is set at L level. In contrast to the data demodulator 12, 14 is a modulator that performs DPSK modulation on data output from CI"U3O, which will be described later, and is used to separate the synchronization signal from the video signal input from the video input terminal 18.
H s yn , V s y separated by 7
The modulated data is output to the recording amplifier 16 at a timing corresponding to nc.

15 is F for the video signal input from the video signal input terminal 18.
This is a recording amplifier that performs processing necessary for recording such as M modulation and outputs it to the recording amplifier 16. A reference signal generator 19 generates accurate reference pulses (60 Hz) for rotating the magnetic sheet 1 and an alternating signal for erasing.

Reference numeral 20 denotes a magnetic piece provided on the magnetic sheet 1 described above, and the DC motor 2 is synchronized with a reference signal generated by a reference signal generator 19 using a signal from the magnetic piece 20 as described later. Rotation control is performed. 21 is a magnetic piece 20 when the magnetic sheet l is rotated by the DC motor 2.
This is an r'G coil for detecting signals from.

22 is a waveform shaping circuit that shapes the waveform of the signal output from the I)G coil 21, and the output of the waveform shaping circuit 22 is input to a CPU 40 and a motor control circuit 23, which will be described later.

Reference numeral 23 denotes a control circuit for controlling the rotation of the DC motor 2, which outputs Vsync from the synchronization signal separation circuit 17 or the output signal of the reference signal generator 19, and the waveform shaping circuit 2.
2, that is, the phase relationship with the signal from the magnetic piece provided on the magnetic sheet l is in a predetermined relationship, for example, the phase of both is always 71! The rotation of the DC motor 2 is controlled so as to be in a shifted state. Here, when the magnetic head 3-1.3-2 performs a recording operation, SWI is the synchronization signal separation circuit 17.
The rotation of the DC motor 2 is controlled based on Vsync and the signal input from the waveform shaping circuit 22, that is, the signal from the magnetic piece 20 provided on the magnetic sheet 1. 3-1. When the reproducing operation is performed according to 3-2, SWI is the reference signal generator! 9
The DC motor 2 is switched to the side based on the reference signal from the reference signal generator 19 and the signal input from the waveform shaping circuit 22, that is, the signal from the magnetic piece 20 provided on the magnetic sheet l. Rotation is controlled.

23' is a driver that drives a step motor 24 for controlling the position of the head 3-1, 3-2 based on a signal from the CI'U 40, which will be described later. Head 3-1.3
-Move 2.

25' is a display circuit driven by a signal from the CPU 40, and as a display element, as shown in FIG. 1.3-2 7-segment display element to display the feed speed in 2 digits, Pn and LED to indicate the playback mode, R I': C, LED frame to indicate the recording mode. Display mode [” RAM Ic, l, E I) Display field mode FIELD, 1.E
I).

26 is a ROM in which the program of the CPU 40 is stored.
.

27 is a RAM in which data of CI) U 40 is temporarily stored. 28 is a timer driven by the CPU 40, and 29 is a crystal oscillator that generates a reference clock for the CPU 40. Note that 80 is a detection circuit connected to photocouplers 81 and 82 that constitute a detection switch for detecting whether or not the magnetic sheet 1 is inserted.

83.84 and SW6 are data signals (hereinafter referred to as I
83 is a circuit for displaying (referred to as D) on the monitor 13 and printer 13-, and 83 separates the Vsync and Hsync of the video signal input via SW5 to adjust the timing of the generated data characters. This is a synchronous separation circuit having the same configuration as the synchronous separation circuit shown as 17. 84 is a character generator for generating characters corresponding to data signals in synchronization with Vsync and Hsync separated by the synchronization separation circuit 83. When displaying the ID signal superimposed on the video signal on the monitor 13 and printer 13''; well, CPU 4
A control signal is applied from 0 to turn SW6 on, and a synchronization signal and a data signal are added by the adder shown as ■ in FIG. 1, and displayed at a specific position on the monitor 13 or printer 13-. The details will be described later.

85 is an erase signal generator for erasing signals on any track of the magnetic sheet l. Note that the AC signal for erasing is provided from the reference signal generator 19.

Here, the erasure signal generator 85 has a constant amplitude period T1 as shown in FIG. 29, and a subsequent attenuation period T.
2 and is connected to the recording amplifier 16.

SWI is a switch whose state is changed by a signal from the control circuit 30 that is driven based on a signal from the CPU 40. A video signal is input from the video signal input terminal 18, and Hs is input from the synchronization signal separation circuit 17. y n
c is being output, and when a signal indicating the recording mode is input from the CI'U, the synchronous signal separation circuit 17 and the motor control circuit 23 are connected, and the synchronous signal separation circuit The reference signal generator 19 and the motor control circuit 23 are connected to each other in the erasing mode.

SW2 is a switch whose state is changed based on a signal from the CPU 40, and is connected to the state where the head 3-1 is connected to the recording amplifier 16, the state where it is connected to the playback amplifier 6, and whether the head 3-1 is connected to the recording amplifier 16 or the playback amplifier 6. Switch between an intermediate state in which no connections are made.

Like SW2, SW3 is a switch whose state changes based on a signal from the CPU 40, and there are two states: connecting the head 3-2 to the recording amplifier 16, connecting the head 3-2 to the reproducing amplifier 6, and connecting the head 3-2 to the recording amplifier 16 and the reproducing amplifier. 6 and an intermediate state in which it is not connected to any of

When reproducing a video signal from the magnetic sheet 1, the SW4 is switched to the upper position in FIG. When the head 3-1 is connected and a field video signal is reproduced using only the head 3-1, the demodulation circuit 9 is switched to the upper side and the lower side in FIG.
The state where the CPU is connected to
This is a switch driven by 40.

SW5 connects the monitor 13 to the video signal input terminal 18 during recording.
This is a switch driven by the CPU 40 to connect the monitor 13 to SW4 during playback.

By the way, as mentioned above, the video signal recorded on or reproduced from the magnetic sheet 1 can be a field video signal consisting of only the 1 field, or a frame video signal consisting of two fields in pairs. However, in such a case, SW2. SW3. Switching of the states of SW4 and SW5 will be explained using FIG. 2.

Figure 2 shows SW2. SW3. SW4. It is a figure which shows the combination of the switching state of SW5.

During field playback, SW2 connects the head 3-1 to the playback amplifier 6, and switches SW3 to an intermediate state, that is, head 3-1.
-2 is not connected to either the playback amplifier 6 or the recording amplifier 16, and SW4 outputs the signal directly from the demodulation circuit 9 to the monitor 13 in odd fields, and l in even fields.
The signal is alternately switched for each field so that the signal is output to the monitor 13 via the /2+1 delay circuit 10, thereby preventing the occurrence of skew distortion.

Next, in frame reproduction, SW2 connects the head 3-1 to the reproduction amplifier 6 in odd fields, and is in an intermediate state in even fields, SW3 is in an intermediate state in odd fields, and connects the head 3-2 to the reproduction amplifier 6 in even fields. Connect to. Therefore, during frame reproduction, signals from either head 3-1 or 3-2 are alternately output to the reproduction amplifier 6 for each field.

In this case, SW4 is switched to the upper side in FIG. 1, and the signal from demodulation circuit 9 is directly output to monitor 13.

In any of the above-mentioned field playback and frame playback states, SW5 is driven so that monitor I3 is connected to SW4.

Next, in field recording, SW2 connects the head 3-1 to the recording apparatus 16, and SW3 is in an intermediate state.

Therefore, during field recording, recording is performed by the head 3-1.

In frame recording, SW2 connects the head 3-1 to the recording amplifier 16 in odd fields and is in an intermediate state in even fields; SW3 is in an intermediate state in odd fields, and connects the head 3-2 to the recording amplifier 16 in even fields. Connecting. In frame recording, the combination of heads 3-1 and 3-2 can also be reversed.

Further, in both field recording and frame recording, during recording, the SW 5 is switched so that the monitor 13 is connected to the video signal input terminal 18 so that the video signal to be recorded can be observed on the monitor 13. In addition, if this occurs, SW
4 may be in any state.

Next, the erase mode will be explained. In the erase standby state, which will be described later, SWI is on the reference signal generator side, SW
5 is connected to the upper side in FIG. 1, and is in the same state as the playback mode.At this time, when performing field erasing, for example, when erasing only the track on which the magnetic head 3-1 is currently active. In this case, at the same time as erasing starts, a control signal is sent from the CPU 40 so that SW2 is placed on the recording amplifier side and SW3 is placed in an intermediate state.Furthermore, an erase signal trigger pulse is sent from the PU 40 to the erase signal generator 85, and the head 3- Send the erase signal only to !.

Next, a description will be given of frame erasing in which tracks being accessed by heads 3-1 and 3-2 are simultaneously erased. When erasing a frame, an erasing signal is sent to the heads 3-1 and 3-2 at the same time, so the CPU 40 sends a control signal so that SW2 and SW3 are both on the recording amplifier side. and cp
A trigger pulse from u40 generates an erase signal, which flows to both heads via the recording amplifier.

Furthermore, in this embodiment, when field erasing is performed, the erasure is performed by head 3-1, but when field erasing is performed using head 3-2, SW2 is in the intermediate state, and SW2 is in the intermediate state.
It is only necessary to control W3 so that it is on the recording amplifier side.

Next, the switches 51 to 78 shown in FIG. 1 will be explained.

In giving this explanation, the external appearance of the apparatus of this embodiment shown in FIGS. 3 and 4 will also be explained.

FIG. 3 is a front view of the apparatus of this embodiment, and FIG. 4 is a front view of a remote control device used in the apparatus of this embodiment.

The switches 51 to 79 and 72 shown in FIG. 1 are the switch group provided in the device shown in FIG. 3, the switch group provided in the remote control device shown in FIG. The switch 11T is provided in both the remote control device shown in FIG. 1 and the remote control device shown in FIG. Note that the switches provided in the device shown in FIG. 3, which in FIG. 1 are only provided in the remote control device shown in FIG. The signal generated by operating the switch provided only in the remote control device shown in Fig. 4 is shown in Fig. The light is converted into light and input to the CPU 40 of the device shown in FIG. 3 via the remote control light receiving section 45 provided in the device.

It should be noted that the method of arranging the switches 51 to 79 can be considered in various other variations of this embodiment, and is not limited to this embodiment.

In FIGS. 1 to 4, 41 is a power switch, 42
is a slot for inserting the magnetic sheet 1; when the inject button 43 is turned on while the magnetic sheet 1 is inserted into the slot 12, the slot opens automatically and the magnetic sheet 1 is injected. 43 is the inject button, 4/IA, 440 are the above-mentioned 1) 11,
L Ishi D, I? 1", C, LED, 45 is a remote control light receiving unit that receives a signal from the remote control I/roll device shown in FIG. 4, 46 is an interval mode display L E D, which lights up when interval playback is executed. is a display I that indicates whether field playback or recording, frame single playback or recording is set;
■ζD, 25 is the 2-digit 7-segment I-1 described in +iit,
1 shi■), 5(l A, 5 fl +1.50 C
are LEDs that display the operating states of a program playback setting switch 58, an interval time setting switch 57, and a program track setting switch 62, which will be described later.

51 is a REC mode switch for setting the recording mode and checking whether the track accessed by the head in the recording mode is recorded or unrecorded; when the switch is turned on, the track accessed by the head is (If the track being accessed by head 3-■ has already been recorded during field recording, or the track being accessed by head 3-1 or 3-2 during frame recording) has been recorded), REC
, LED blinks, indicating that the track that the head is accessing is unrecordable, and if it has not been recorded yet, or if the control circuit 30 determines that no video signal is input, the RE C, 1, ED lights up, indicating that recording is possible.

52 is R E that determines the timing to perform the recording operation.
C switch and N E C mode setting switch 51
When the recording mode is set by , and the switch 51 is turned on, recording is performed on the magnetic field 1-1. Furthermore, if continuous recording has been set in advance by a track feed speed setting switch 56, which will be described later, the switch 5! Head 3- is automatically turned on while
Continuous recording is performed while 1.3-2 is shifted.

Reference numeral 53 is a I) [3 mode setting switch for setting the playback mode, and when the switch 53 is turned on, ['n, L I': D lights up to indicate the playback mode.

54 is a track UP switch, and by operating the switch 54, the driver 23' is controlled, the step motor 24 is rotated, and the head 3-1, 3-2 is moved by the head moving mechanism l+, so that the head 3- 1
．． 3-2 to change the track that the head is accessing more toward the inner circumference. Further, when recording is performed in frames using a field/frame setting switch 59, which will be described later, the recording progresses two tracks at a time. When playback is set, when the track Ul) switch 54 is turned on, the heads 3-1, 3-2 are shifted by two tracks, and the 7-segment LED 25 also displays the track number shifted by l-rack. Instead, the track number shifted by two tracks is displayed, and when field recording or playback is set, press the track UP switch 5.
4 is turned on, the heads 3-1, 3-2 are shifted one track at a time toward the inner circumference, and the shift number shifted by one track is also displayed on the seven segment LED 25.

In addition, when the recording mode is set, the operation of the track UP switch 54 causes the head 3-! .

When head 3-2 is shifted, if the track accessed by head 3-1.3-2 has already been recorded, REC.

RED 44 +3 performs a blinking display. 55 is a track DOWN switch which is opposite to the track UP switch 54 and is used to change the access of the heads 3-1, 3-2 toward the outer circumference.

When the switch 55 is also set to frame recording in the same way as the track UP switch 54, when the switch 55 is operated and the tracks on the outer circumference of track 1 and the track on the outer circumference of track 2 are being subjected to frame recording, The track number shifted by 2 tracks is displayed on the 7 segment LED 25 instead of the track number shifted by 1 track, and when field recording or playback is set and the switch 55 is operated, a trick will occur. The shifted track number will be displayed.

Further, in the case where the recording mode is set in advance in the same way as explained in the above-mentioned track U I) switch 54, when the head 3-1, 3-2 is shifted by operating the track DOWN switch 55, REC if the accessed track has already been recorded.

The LED 44B performs a blinking display.

56, when recording and reproducing, it automatically switches whether to perform such operations continuously or sporadically while shifting the head, and also determines how many times per second the operations are performed when performing them continuously. This is a track feed speed setting switch for setting the track feed speed shown in FIG.

When the switch 56 is pressed once and turned on, the track feed speed is displayed instead of the track number on the 7-segment LED 25, and in this state, the track feed speed setting switch 56 is turned on again within the predetermined time clocked by the timer 28 shown in FIG. is turned on, each time the switch 56 is turned on, the 7-segment LED 2
For example, "5" indicates continuous recording or playback of 2 screens per second, "5" indicates continuous recording or playback of 5 screens per second, or continuous recording or playback of 10 screens per second. "/a" indicating that playback is to be performed and "8" indicating that recording or playback is to be performed one-off are cyclically displayed. Also, by turning on and then turning off the switch 56, the track feed speed is displayed instead of the track number on the 7-segment LED 25, and when the timer 28 completes the measurement of the predetermined time without turning on the switch 56 again. Yes, E D
25 returns from the state where the track feed speed is displayed to the state where the normal track number is displayed.

Furthermore, when the track feed speed is changed by the switch 56, if frame video recording is set in advance by the field/frame setting switch 59 and the REC mode setting switch 51, continuous recording of 10 screens per second is not set. .

57 is an interval time setting switch. That is, the interval time setting switch is used to set the interval time for track forwarding when continuous playback is performed but the playback interval time is relatively long, or when program playback is set by the program track setting switch 58 described later. and
63-72 within 10 seconds after the switch is turned on! Set the interval time using the 0 key switch.

Incidentally, when any switch other than the IO key switches 62 to 72 is turned on after the interval time setting switch 57 is turned on, the interval time setting is automatically canceled. Reference numeral 58 denotes a program playback setting switch for setting a program playback mode in which the order of playback tracks is programmed in advance and the playback operation is performed continuously at the interval time interval set by the interval time setting switch 57.

To specify the order of playback tracks, first turn on the switch 58 to set the program playback mode, and then operate the track UP switch 54 and track DOWN switch 55 to select the track being accessed by the heads 3-1 and 3-2. This is done by changing the number of the desired track, reproducing the video of the desired track, checking it on the monitor 13, and turning on a program track setting switch 62, which will be described later, to memorize the number of the track being checked on the monitor 13. Reference numeral 59 denotes the aforementioned field/frame setting switch, and each time the switch is turned on, the field recording or reproduction mode and the frame recording or reproduction mode are alternately switched.

Note that when the continuous recording mode of 10 screens per second is set in advance by the REC mode setting switch 51 and the track feed speed setting switch 56, and frame recording is selected by the field/frame setting switch 59, The track advance speed is automatically changed to a continuous recording mode of 5 screens per second.

That is, compared to field recording, during frame recording the head 3-1.3-2 must be shifted two tracks at a time, so when recording 10 screens per second, 20 tracks per second are required. In other words, taking into consideration the time to record the video signal, the head shift for two tracks must be performed in 4/60 seconds, but such a high-speed head shift is difficult, so this implementation was carried out. In the example, continuous recording of frames for 10 screens per second is prohibited.

Reference numeral 60 is a start switch for performing continuous interval playback or program playback. When the start switch is turned on, if interval playback is set, the recorded tracks will be played back sequentially starting from the first track during the interval time. Interval playback is started according to the interval time set by the setting switch 57 and the ten key switches 63 to 72, and when program playback is set, program playback is started. Reference numeral 61 denotes a stop switch for stopping the reproduction operation started by the start switch 60, and when the switch 61 is turned on during program reproduction, the reproduction of the program is stopped while the track being reproduced at the time is being reproduced.

62 is the aforementioned program track setting switch.

Reference numeral 73 is a switch for starting ID setting in the recording mode and for switching whether or not to display the ID contents in the playback mode. That is, by turning on the switch 73 in the recording mode, it becomes the ID setting mode, and by turning on the switch 73 in the playback mode, it is possible to switch between displaying or not displaying the contents of the ID. I can do it. 74,75
．． Reference numerals 76 indicate a switch that is turned on when setting the ID and setting the year, a switch that is turned on when setting the month, and a switch that is turned on when setting the day when the ID setting mode is entered by the switch 73. . In FIG. 1, for convenience, the switches 74, 75, 76 and the aforementioned switches 57, 58, 62 are shown as independent switches, but in this embodiment, the switches 74, 75, and 76 are shown as independent switches as shown in the remote control device r in FIG. , 75.76 are also used as switches 58, 57.62, respectively. That is, the switch 57 is used to set the program using the interval time setting switch 58, and the switch 62 is used to set the program track independently of the ID setting of January 9, 2015, so in this embodiment, the switch is also used. This reduces the number of switch members and improves operability and reliability.

In addition, various other combinations can be considered when the switch is also used.

77 is an erase standby switch for temporarily placing the device in an erase standby state when erasing information recorded on the magnetic sheet l; 78 is for executing an erase operation in the erase standby state set by the erase standby switch 77; This is the erase switch. Reference numeral 79 is an all-track erase standby switch that sets a mode for erasing all tracks.

When erasing the information recorded on the sheet I, the switch 77 is first turned on to set an erasing standby state. In such a state, the reproduction mode is automatically set, so that the video recorded on the track to be erased can be confirmed on the monitor 13 or on the printer 13' before erasing is executed.

In addition, in the standby state, the lO key switches 63 to 72
By operating , you can specify the number of tracks to be erased consecutively. Next, by turning on the erase switch 78, at least one of the heads 3-1 and 3-2 is connected to the recording amplifier 16, and the information recorded on the track is erased by the erase signal shown in FIG. 32 generated from the erase signal generator 85. will be deleted. Further, by turning on the all-track erase standby switch 79 and then turning on the erase switch 78, all tracks are automatically erased.

Next, the operation of the embodiment of the present invention will be explained using the flow charts shown in FIGS. 5 to 20, 23, and 25 to 27.

First, when the power switch 41 shown in FIG. 3 is pushed in, the power of the device shown in FIG. 1 is turned on, power is supplied to each part of the circuit, and operation is started.

#l: Then, in FIG. 5, the register S described later becomes “0”.
", the PB mode flag is set, the track feed speed is initially set to 2 screens per second, and the interval time is set to 3 seconds. Therefore, when the power is turned on, continuous playback mode is automatically set in advance. Ru.

#2: Detect whether a jacket having a magnetic sheet 1 is pushed in or not. When the jacket is pushed in, the flow branches to #3, and when it is not pushed in, the flow skips #3 and branches to #4.

#3: When the jacket having the magnetic sheet 1 is being pushed in in #2, the DC motor 3 is driven.

#4: Detect whether the head 3-1 is accessing the 50th track by detecting whether the switch 5 shown in FIG. When the head 3-1 is not accessing the 50th track, the flow branches to #5, and the step motor 24 shown in FIG. 1 is driven. The loop of #4 and #5 is repeated so that the head 3-1 accesses the 50th track.

#6: When the head 3-11 accesses the 50th track, the flow reaches this step, and in this step, the register N for accessing the memory (RAM 27) is set to 50.

#7: In this step, it is detected whether the DC motor 2 is being driven. When the jacket having the aforementioned magnetic sheet 1 is inserted, the DC motor 2 is being driven by executing #3, so the flow advances to step #8 and the field flag is set. When the jacket is not inserted, the flow proceeds without passing through #3, so the DC motor 2 is not driven. Therefore, the flow returns to #2 to detect whether a jacket is inserted or not.

#8: When the DC motor 4 is being driven in #7, a field flag is set. Therefore, the LED 44A indicating the field mode shown in FIG. 3 lights up, and a display indicating the field mode is performed. That is, in this embodiment, when the power is turned on and the jacket is inserted, the field mode is automatically set.

#9: Detect the output of the level detection circuit 7 shown in FIG. 1 to determine whether the track being accessed by the head 3-1 is a recorded track or not.

Here, since the track that the head 3-1 is accessing has already been recorded, when the output of the level detection circuit 7 becomes H level, the flow advances to #lO, and the output of the level detection circuit 7 becomes L level. The flow is #! Proceed to step 6.

Here, #16 will be explained first.

#! 6: Set “oooo” to address N in memory. Here, "0000" indicates that the track corresponding to the memory address is unrecorded.

Next, the flow from #10 onwards will be explained.

#lO: When the output of the level detection circuit 7 is at H level in #9, reproduces the signal recorded on the track,
The ID signal is taken in from the data demodulator 12.

#11: Detect the contents of the ID signal to determine whether the video signal recorded on the track is a field video signal or a frame video signal. If it is a field video signal, the flow advances to #15, and if it is a frame video signal, the flow advances to #12.

#12: In this step, it is determined whether the video signal of the track that the head 3-1 is accessing is an inside track or an outside track of the frame video signal. Flow is # if it is an inside track! Proceed to 4. If it is an outside track, the flow advances to #13.

#13: If the video signal of the track that the head 3-1 is accessing is a track outside the frame video signal, set the memory address N to "0011". Note #l
When proceeding to this step for the first time, N is set to 50 in #6.

#14: In the case of the frame video transmission video inner track, set the memory address N to "0010".

#! 7: When the head 3-1 is shifted to the first track and it is detected that N=1, the flow is #2.
If N=1, the flow advances to #18.

#I8: When it is detected in #17 that N=1 is not true, the l trough 2 minute head 3-1 is shifted to the outer circumferential side.

#19: When the head 3-1 is shifted toward the outer circumferential side in #18, it is subtracted from N to obtain N.

#20: If N=1 is detected in #17, that is,
When the head 3-1 accesses the first track provided on the outermost periphery and the presence or absence of recording is set in the memory, the data at the N address of the memory, that is, the first address of the memory is read here and is "0011". ”, specifically the first
If the track is the outer track of the two tracks that make up the frame video signal, the flow advances to #21;
Otherwise, the flow proceeds to #23.

#21: If it is detected in #20 that the first track is a track outside of the tracks constituting the frame video signal, the flow advances to this step. In this step, if the data at address N+1 of the memory, that is, the second address of the memory, is read and it is "0010", specifically, the second track is the inner track of the two tracks that make up the frame video signal. In case #2
Proceed to step 2.

#22: When frame video signals are recorded on two tracks, the first track and the second track, the flow moves to this step. Therefore, the field flag set in #8 is cleared and the field mode is changed to frame mode. Therefore, the field frame display LED-48 shown in FIG. 3 lights up to indicate the frame mode.

#23. #24: The register N indicating the address of the memory mentioned above is connected to the 2-digit 7-segment LED shown in Figures 1 and 3.
25.

This display allows the user to recognize the track number that the head 3-1 is accessing.

When this flow ends, the process jumps to the next flow shown in A. The flowchart shown in FIG. 6 will be explained below.

#A-1: Detects whether the REC mode setting switch 51 is turned on, and when the switch 51 is turned on, the flow calls subroutine ■ to set the recording mode, and when it is not turned on, the flow calls #A-1. Proceed to A-2.

#Δ-2: It is detected whether the REC switch 57 is turned on, and when the switch 52 is turned on, subroutine (2) is called, and when it is not turned on, the process proceeds to #A-3.

#Δ-3: Detect whether the PB mode setting switch 53 is turned on, and when the switch 53 is turned on, subroutine O is called, and when it is not turned on, the process proceeds to #A-4.

#A-4:) When the rack UP switch 54 is turned on, the flow calls subroutine (2), and when it is not turned on, the flow advances to #A-5.

#A-5:) When the rack DOWN switch 55 is turned on, the flow calls subroutine (2), and when it is not turned on, the flow advances to #A-6.

#A-6: When the l-rack feed speed setting switch 56 is turned on, the flow calls subroutine [F], and when it is not turned on, the flow advances to #A-7.

#A-7: When the interval time setting switch 57 is turned on, the subroutine ◎ is called, and when it is not turned on, the process proceeds to #A-8.

#A-8 When the nib program setting switch 58 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-9.

@A-9 When the nib program track setting switch 62 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-10.

#A-1o: When the field frame setting switch 59 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-11.

#A-11 When the start switch 60 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-12.

#A-12 When the stop switch 61 is not turned on, the subroutine [phase] is called, and when it is not turned on, the process advances to #A-13.

#A-13: When the jacket detection switch (corresponding to the detection circuit 80 in Fig. 1) is turned on, jump to subroutine ■, and when it is not turned on, jump to #A-14.
Proceed to.

#A-14 Clear the Niprogram playback mode flag and the program playback execution flag.

#A-15: When any of the 10 key switches 63 to 72 is turned on, subroutine (2) is called, and when it is turned on, the process proceeds to #A-16.

#A-16: When the ID switch 73 is on, call subroutine 0, and when it is on, call #A
Proceed to -17.

#A-17+ When the year setting switch 74 is on, subroutine ■ is called, and when it is on, #
Proceed to A-18.

#A-18: When the month setting switch 75 is on, subroutine ■ is called, and when it is on, #
Proceed to A-19.

#A-19: When the date setting switch 76 is turned on, subroutine ■ is called, and when it is turned on, #
Proceed to A-20.

#A-20: When the erase standby switch 77 is turned on, subroutine (2) is called, and when it is turned on, the process advances to #A-21.

#A-21: When the all-track erase standby switch 79 is on, subroutine (2) is called, and when it is on, the process advances to #A-13.

As explained above, after the head 3-1 accesses the first track of the magnetic sheet by executing the flow shown in FIG. 5, the flow jumps to the flow shown in FIG. While detecting the state of each switch shown in Figures 3 and 4, the flow shown in ■ is repeatedly executed until the state of each switch changes, and the subroutine corresponding to the operated switch is called. .

Here, the subroutine [F] called when the track setting feed speed switch 56 is turned on will be explained using FIG.

FIG. 7 is a flowchart showing a subroutine executed when the switch 56 for changing the track setting feed speed is turned on.

#F-1. The set value of the track feed speed is read from the #F-2+ memory, and the set value is set in a track number display buffer (not shown).

Therefore, the two-digit 7-segment LE shown in Figure 3
The track feed speed is displayed on D25. If the flow comes to this step for the first time, the flow rate is 2 per second at #l.
Since the track advance speed on the screen is set, select “2”.
” is displayed.

#F-3:) When the rack feed speed setting switch 56 is on, the flow repeats #F-3, and when the switch 56 is turned off, the flow moves to #F-4.

As mentioned above, once the track feed speed setting switch 56 is turned on, the two-digit 7-segment LED 25 shown in FIG. 3 switches from displaying the track number to displaying the track feed speed.
Next, the track feeding speed is changed by turning on the switch 56 again.

#F-3 is provided so that the track feed speed is switched only when the switch 56 is turned on, once turned off, and then turned on again as described above.

#F-4. #F-5. #F-6. #F-7: In these steps, the track feed speed setting switch 56 is turned on, and the 2-digit 7-segment LED 25 shown in FIG.
If the switch 56 or any other switch is not turned on for a predetermined period of time (2 seconds) after the display changes from the track number display to the track feed speed display, the setting of the track feed speed is canceled. These steps are designed to help you.

Predetermined time (2 seconds) after timer l starts counting
When the track feed speed setting switch 56 is turned on during this period, the flow progresses from #F-7 to #F-10, and when timer 1 completes timing, or when another switch is turned on, the flow advances from #F-7 to #F-10. The flow advances from -6 to #F-8.

#F-8: Clear the count value of timer 1.

#F-9: Contrary to #F-1, the two-digit 7 shown in Figure 3
The display of the segment LED 25 is returned to displaying the track number.

#F-10: Clear the count value of timer 1.

#F-II: Check whether the track feed speed setting value is single (once recorded or played back, the head is shifted by 2 troughs in field mode, and the head is shifted by 2 tracks in frame mode and then stopped). Detected, if single, go to LJ#F-12, if not single, go to #F-13
The flow continues.

Note that, as described above, when the flow reaches this step after the power switch 41 is turned on, the track feed speed is previously set at 2 screens per second in #l.

#F-12:l- If the rack feed speed setting value is single, change the setting value to 2 screens per second, return to #F-1, display the changed track feed speed, and return to #F-1 as described above. Execute steps 3 to #F-7.

@F-13 It is detected whether the NiDrac feed speed setting value is 2 screens per second, and if it is 2 screens per second, the flow proceeds to #F-14, and if it is not 2 screens per second, the flow proceeds to #F-15.

#F-14 Change the track feed speed setting value to 5 screens per second, return to #F-1, display the changed track feed speed, and execute the above-mentioned steps #F-3 to #F-7.

5F-15:) Detect whether the rack feed speed setting value is 5 screens per second. If it is 5 screens per second, go to #F-16. If it is not 5 screens per second, that is, 10 screens per second is set. Then the flow advances to #F-17.

#F-16: Determine whether the PB mode flag is set. If the PB mode flag is set, that is, if the playback mode is set, #F-18
If the PB mode flag is reset, that is, if the recording mode is set, the flow advances to #F-19.

#F-17: Change the track feed speed setting value to single, return to #F-1, display the changed track feed speed, and execute the above-mentioned steps #F-3 to #F-7.

#F-18: In the playback mode, regardless of whether the video signal recorded on the track of the magnetic sheet 1 is a field video signal or a frame video signal, field playback is performed during continuous track feeding. Therefore, if it takes track feed speed setting value every second! The screen changes to °0 and the flow returns to 9F-1.

#F-19: Detects whether or not the field flag is set, and if the field flag is set, that is, if track advance is set at 5 screens per second in recording mode and in field mode, #F is detected. The flow branches to -18.

Also, if the field flag is not set, that is, the track feed speed setting value of 5 screens per second is set in recording mode, and in frame mode, #F-17
The flow advances to change the track feed speed setting to single.

Therefore, in the above-mentioned subroutine [F], when the track feed speed setting switch 56 is turned on, the track feed speed is displayed on the two-digit 7-segment LED 25 shown in FIG. 3 for a predetermined period of time (2 seconds). The track advance speed is changed by turning on the switch 56 again within the time.

In addition, the range of changes is single, 2 screens per second, and 5 screens per second when in frame recording mode, and single, 2 screens per second, and 5 screens per second when in other than frame recording mode.
There are 4 types of screens, 10 screens per second.

The scope of this change is head 3-1.3-2 shown in FIG.
This is related to the track shifting ability of the moving mechanism, etc., and is set in advance to an appropriate range depending on the track shifting ability.

Next, using FIG. 8, while executing the subroutine shown in FIG. 6, the track UP switch 54. TRACK DOWN
The subroutines ① and ② that are called when the switch 55 is turned on will be explained. First, a flow called when the track UP switch 54 is turned on will be described.

#D-I: When the flow reaches this step, detect whether the track being accessed by the head 3-1 is the innermost track or not, and whether the register number N is 50. Determine by.

As a result, if N is not 50, go to #D-2;
If it is 0, the flow advances to #D-34, which will be described later.

@D-2: Determine whether the PB mode flag is set. When the PB mode flag is set, that is, in the playback mode, it is #D-8; when the PI3 mode flag is not set, that is, in the recording mode, it is #D-8.
The flow advances to -3.

#D-3: JMo+)-(7)N+1 address h<”oo
It is detected whether or not the N+! track is unrecorded. If it is unrecorded, the flow branches to #D-4; if it has been recorded, the flow branches to #D-7.

#D-4: No. N+! The track was unrecorded #
If it is determined in D-3, it is determined in this step whether or not the field flag is set, and if it is set, the process goes to #D-6, and if it is not set, the process goes to #D.
The flow advances to -5.

#D-5: When it is determined in #D-4 that the field flag is not set and the mode is frame mode, this step is reached. In this step, it is detected whether the N+2nd content of the memory is 'oooo', and if it is '0000', that is, the N+2nd content is
If 2 tracks are unrecorded, go to #D-6, “o
ooo", that is, if the N+2 track has already been recorded, the flow advances to #D-7.

By executing steps #D-3 to #D-5, if both consecutive two tracks are unrecorded in frame mode, at least one of the two consecutive tracks will be moved to #D-6. #D- if it has been recorded
The flow advances to 7.

#D-6: In the field mode, the track that the head 3-1 is accessing; in the frame mode, the track that the head 3-1 is accessing, and the track that is being accessed! If the track being accessed by the head 3-2 on the inner track side is unrecorded, that is, if it is recordable, the flow reaches this step, and the RECLED shown in FIG.
44B lights up.

#D-7: Head 3-1.3-2 opposite to #D-6
If the track to be accessed and recorded has already been recorded, a warning is displayed by blinking the RECLED 44B shown in Figure 3 to make the user aware that recording is not possible. I do.

#D-8: If the PB mode flag is set in #D-2, the flow reaches this step and the field flag is set.

For the meaning of this step, see #D-9゜#D-10.
#D=+3 will be explained.

#D-9: Memory address N is -0011”, i.e. #13
As explained above, it is detected whether the track that the head 3-1 is accessing is the outermost track of the two tracks that make up the frame video signal, and if it is the outermost track of the two tracks. If the track is on the outer circumferential side, the flow proceeds to #D-13.

#D-10: Detects whether address N+1 of the memory is "0010", that is, whether the track being accessed by the head 3-2 is the inner track of the two tracks constituting the frame video signal; If the track is on the inner side of the two tracks, the flow proceeds to #D-11, and if it is not on the outer side, the flow proceeds to #D-13.

That is, if the inner track of the two tracks making up the frame video signal is erased or a new video signal is recorded after erasing, the track accessed by the head 3-1 will make up the frame video signal. Even if it is the outer track of the two tracks, the head 3
It happens that the track being accessed by -2 is not the inner track of the two tracks. Therefore, in this case, when shifting the head 3-1, 3-2 to the inner circumferential side, it is necessary to shift only one track and reproduce the erased or track on which the video signal is newly recorded after the erased.

However, in such a case, the head 3-1°3-2 is
When only the track is shifted to the inner circumferential side, the head 3
A frame video signal is not necessarily recorded on the track accessed by -1.3-2, and completely different field video signals may be recorded thereon. In this case, if the field flag is reset, a problem arises in that two separate field video signals are reproduced as frame video signals. Therefore, the above #D-
In this embodiment, by providing 8 steps, when the head is shifted to the inner circumferential side, the field mode is set by setting the field flag in advance in this step. It is possible to solve the problem that the signal is reproduced as a frame video signal.

#D-11; In this step, it is detected whether register N is 49 or not, and if N is 49, #D-11;
If N is not 49, the flow branches to #D-12.

#D-12: The flow reaches this step when frame video signals are being recorded on the two tracks accessed by the heads 3-1 and 3-2. If such a recording is made, track U
When the P switch is turned on, the driver 23 is driven to shift the heads 3-1 and 3-2 by one track in this step, and then in #D-13, the driver 23 is driven to shift the heads 3-1 and 3-2 by one track. -Shift 2. Further, as described above, N is updated by l each time the heads 3-1, 3-2 are shifted.

[)-13; Similar to #D-12, head 3-1.3
-2 is shifted by 1 trough by 2 minutes.

tD-14: Similarly to #23, display N on the 2-digit 7-segment LED 25 shown in FIG.

In this embodiment, these steps are #D-12 and #D-13.
Heads 3-1 and 3-
When a frame video signal is recorded in the accessed track 2, the track number displayed on the LED 25 is updated by 2, and when a field video signal is recorded, the track number displayed on the LED 25 is updated. The track number on the magnetic sheet will be updated by l.
It is possible to display whether a field video signal or a frame video signal is being recorded on the top.

Additionally, if this step is also provided between #D-12 and #D-13, if frame video signals are recorded on the two tracks accessed by heads 3-1 and 3-2, Even if there is, when the track UP switch 54 is turned on, the track number displayed on the LED 25 will be updated one by one.

#D-15; Determine whether the PB mode flag is set. #D-16 if set
If it is not set, the flow branches to #D-19.

If set, branch to #D-15-1.

#D-15-1: Here, the CPU 40 reproduces the data output from the data demodulator R312 in FIG. D times signal RA
Import into M27. The flow advances to #D-15-2.

#D-15-2: Here, it is determined whether the mode is one in which the ID is superimposed on the video signal and monitored. Details of this mode will be explained using FIG. 20. If it is in this mode, proceed to #D-15-3; otherwise, proceed to #D-15-4.

#D-15-3: When the flow reaches this step, the mode is in which the ID is superimposed on the video signal and monitored, so the CPU reads the playback ID signal from the RAM 27,
A character pattern is generated by controlling the character generator 40 and superimposed on the reproduced video signal on the monitor. The flow advances to #D-15-4. In other words, at this point, the ID DA"rΔ times the signal recorded in the currently accessed track is displayed on the monitor.

#I)-15-4, if the automatic track feed flag is not set, go to #D-20, if it is, go to #
The flow branches to D-16.

#D-16; Memory address N is 0011” It is determined whether the track that the head 3-1 is accessing is the outermost track among the tracks where the frame video signal is recorded. As repeated above, corresponds to the track number that head 3-1 is accessing after moving heads 3-1 and 3-2.Here, the content is "0011" at address N in the memory.
”, the flow branches to #D-17; if not “0011”, the flow branches to #D-19.

#D-17; The contents of memory address N+1 are “00”
10'', that is, the track being accessed by head-3-1 is determined to be the inner track of the two tracks on which the frame video signal is recorded.

Here, if the memory address N+1 is "0010", the flow branches to #D-18, and if it is not "0010", the flow branches to #D-19.

#D-18; When the flow reaches this step via #D-16 and #D-17, heads 3-1 and 3-2
Since frame video signals are recorded in the two tracks accessed after moving, the field flag set in #D-8 is cleared and the frame playback mode is entered. Note that this step is executed only if the automatic track advance flag is set. (
If the automatic track feed flag is not set, the flow branches from #D-15-4 to @D-20, so the field flag remains set in #D-8, and field playback is performed. ) #1. )-+9: In this step, it is determined whether or not the automatic track feed flag is set, and if it is set, the process returns to #D-20, and if it is set, the process returns from this subroutine (RTS). .

The automatic track advance flag is a flag that is set in subroutine ■, which will be described later. When calling subroutine ■ or ■, which will be described later, while running a program that repeats playback while automatically forwarding tracks, the automatic track advance flag is set by subroutine ■, which will be described later. , ■ is provided for extraction.

#D-20; Import the track feed speed setting value from memory.

#D-21; Determine whether or not the track feed speed setting value is single, and if it is single, #D-21;
34, if it is not single, the flow branches to $D-22.

#D-22; Determine whether the track feed speed setting value is 2 screens per second, and if it is 2 screens per second, check #
D-23, if not 2 screens per second # I) -2
The flow branches to step 4.

#D-23, WAIT TIME in CPU40
Set the R register to 28.

#D-24: Track feed speed setting value is 5 per second
Determine whether it is a screen or not, and if there are 5 screens per second, #D
-25, and if it is not 5 screens per second, the flow branches to #D-26.

#D-25; Set WAIT TIMER17 register to lO.

#D-26; If 10 screens per second is set as the l-rack feed speed setting value, the flow reaches this step and the WIT TIMER register is set to 4.

Note that the WAIT TIMER registers set in #D-23, #D-25, and #D-26 are used to control the track feed speed, and are set in #D-3, which will be described later.
1° #D-32 is subtracted every time the magnetic sheet l is rotated once by the DC motor 2.

#D-27; Determine whether or not the REC execution flag is set, and if it is set, #D-28;
If not set, the flow branches to #D-31. Here, the REC execution flag is a flag that is set in subroutine ■, and is a WAIT flag that is set when subroutine ■ is called during the execution of a program that repeats recording while automatically sending tracks.
This is provided to obtain the time equivalent to the time required for recording by subtracting 2 or 5 from the TIMER register in #D-29 and #D-30. That is, in the recording mode, the rotation state of the magnetic sheet 1 is detected from the PG coil 21 to determine the timing for recording the signal to be recorded from a predetermined position on the magnetic sheet, and to record the signal on the magnetic sheet 1. It is set up for the purpose of

Subtract 2 from the TIMER register, and if not set, subtract 5 from the WAIT TIMER register. Here, if 10 screens per second is set as the track feed speed, the WAIT TIMER register is set to 4, but such a setting is possible only in field mode, so in this case, the WAIT TIMER register is set to 4.
Five is never subtracted from the TIMER register.

#D-31; Detects whether or not there is a pulse from the reference signal generator 19 shown in FIG. (Repeat the flow.

#D-32: WAI”r Subtract 1 from the contents of the TIMER register.

#D-33; Determine whether the contents of the WΔDOI'TIMER register are 0 or not, and if it is O, branch to #D-34; if not, branch to #D-31 do.

In steps #D-32 and #D-33, the timer for controlling the track feed speed is set to WAIT"1.
” IMER register and reference signal generator 19. Therefore, the contents of the WAIT TIMER register are used as the waveform shaping circuit 2 that shapes the output of the PG coil 21.
Compared to the method of configuring a timer by subtracting according to the output of 2, stable and more accurate clock operation can be performed. That is, although the output of the I'G coil 21 may include errors due to uneven rotation of the magnetic sheet 1, the output of the reference signal generator 19 is substantially free of such errors. Further, when performing interval recording, it is desirable to stop the rotation of the DC motor 2 during the interval time in order to save power consumption.

When performing such an operation, in the method of subtracting the WA (T TIMER register) according to the output of the waveform shaping circuit 22,
Although it is not possible to measure the interval time over time, the method of this embodiment makes it possible to perform a stable timekeeping operation even when such an operation is performed.

#D-34: Determine whether or not the REC execution flag is set, and if it is set, return (RTS) to the original program that called the subroutine ■; if not set, # Branch to D-35.

#D-35; Determine whether or not the track UP switch 54 is on, and if it is on, further shift the track accessed by the heads 3-1 and 3-2 to the inner circumferential side. Therefore, the flow branches to #D-1, and when it is off, the flow branches to #D-36.

#D-36; To determine whether or not the track DOWN switch 55 is on, and when it is on, shift the track accessed by the head 3-1.3-2 to the outer circumferential side. Then, it branches to #E-1 of subroutine (2), and when it is off, it branches to #D-37.

#D-37; If the PB mode flag is set, go to #D-38; otherwise, go to the subroutine ■
Return to the program that called.

Clear. Then the subroutine Return to the porogram that called ◎.

In the above example, #D-23 is passed regardless of whether it passes through #D-12 in PB mode or not.
, 25, and 26, the value set in WAIT TIMER is not changed, and if #D-12 is passed by the time required to perform one track feed, the track feed speed will be delayed. However, in order to match this, in #D-27, #D-12
If the track feed speed has passed, the track feed speed can be adjusted without any problem by subtracting the time required for head feed of 2 troughs from WATE TIMER.

Next, subroutine (2) executed when the track down switch 55 is turned on will be explained.

Steps #E-1 to #E-13 of subroutine (2) are similar to steps #D-1 to #D-13 of subroutine (◎), so a detailed explanation will be omitted.

However, subroutine ■ is track DOWN switch 55.
Head 3-! when turned on! , 3-2, to shift the track accessed by #E-
1, it is detected whether N=1, and in #E-9, the memory (N-1) battery is "0010", that is, the (Nth)
-1) Detect whether the track is the inner track of two tracks constituting the frame video signal, and #E-
10, the memory address (N-2) is "001 bit", that is, it is detected whether the (N-2)th track is the outer track of the two tracks constituting the frame video signal;
Also, in #E-11, it is detected whether or not N=2, and #E-11 detects whether or not N=2.
For E-12 and #E-13, head 3-1 for l track,
Shift 3-2 to the outer circumferential side.

Next, with reference to FIG. 9, subroutine (2) which is called when the field/frame changeover switch 59 and the REC mode setting switch 51 are turned on will be explained.

#J-1: When it is detected in #A-10 shown in FIG. 6 that the field/frame changeover switch 59 is turned on, the flow advances to this step, and in this step, the field flag is set. If it is set, go to #J-2, if it is not set, go to #J-4
The flow branches.

#J-2; When the field flag is set in #J-1, the field flag is cleared in this step.

#J-3; Determine whether or not the PB mode flag is set. If it is set, the flow branches to #J-8; if not, the flow branches to #J-5.

#J-4: When it is detected in #J-1 that the field flag is not set, the field flag is set in this step.

If the PB mode is not set, that is, in the recording mode, and the field flag is cleared in #J-2, the frame recording mode is entered, and subroutine 0. ■, 10 per second as explained in [F]
Continuous recording of the screen is not possible. Therefore, the subroutine■
When switching from field mode to frame mode, if the track feed speed is set to 10 screens per second,
Such switching should be prohibited.

Therefore, according to this embodiment, #J-6 and #
When a track feed speed of 10 screens per second is set by J-7, the track feed speed setting value is automatically changed to a track feed of 5 screens per second.

#J-5, l-rack feed speed setting value CPU40
Incorporate into.

#J-6: If the track feed speed setting value taken in #J5 is 10 screens per second, the flow branches to #J-7, and if it is not 10 screens per second, the flow branches to #J-8.

#J-7; l-Rack feed speed setting value 5 per second
Change to screen.

#J-8; Field/frame setting switch 5I
If the switch continues to be turned on, this step is repeated, and only when the switch turns off from on, returns to the step shown in #A-1 in FIG.

Next, subroutine (2) called when the REC mode setting switch 51 is turned on will be explained.

#B-1; RE in #A-1 shown in Figure 6
When it is detected that the C mode setting switch 51 is turned on, the flow branches to this step, and the P mode shown in FIG.
I3. LED/14A goes out and the PB mode flag is cleared.

@ 11-5-1; This step requires CPU40
controls the character generator 84 to temporarily stop character generation.

#n-5-2: Determine whether or not it is the ID setting mode. If it is the setting mode, proceed to #13-5-3; otherwise, proceed to #B-6'.

#n-5-3.0 PU 40 reads the set ID from RAM 27 and controls character generator 84 to generate a character pattern. Therefore, [D] is displayed on the monitor 13 superimposed on the video signal input from the video signal input terminal 18. The flow then proceeds to #B-6'.

#11-6'; REC mode setting switch 51
Repeat this step as long as it continues to be on.
When the switch is turned off, the flow branches to #13-7.

#Loaf, when the REC mode setting switch 51 is turned off, it is determined in this step whether the field flag is set, and if the field flag is set, the step shown in #A-1 in FIG. 6 is performed. The flow returns to #J-5 of subroutine ■ when the field flag is not set, and #J
By executing steps -6 to #J-8, when the track feed speed setting value is 10 screens per second, it is automatically corrected to 5 screens per second. Therefore, when the REC mode is set by the EC mode setting switch 51 and the frame mode is set, the track feed speed setting value is limited to a maximum of 5 screens per second.

Next, using FIG. 10, I'll mode setting switch 5:
We will explain the subroutine ◎ that is called when % is turned on.

#C-1: #A-31: Ot shown in Figure 6
, 1te 1) [1 When it is detected that mode setting switch 5-3 is turned on, the flow branches to this step!
The ECLED is turned off and the field flag is set once. That is, separate field video signals are recorded in the two tracks accessed by heads 3-1 and 3-2, and a frame recording mode is set in which the PL3 mode flag is cleared and the field flag is reset. In this case, 1) 11 mode setting switch 53
In this step, in order to prevent separate field video signals from being interlaced and played back when the track being accessed by the heads 3-1 and 3-2 is immediately played back after detecting that the Field flags are set.

#C2; When the memory address is "001", it is detected whether the accessed track for the head is on the outer side of the two tracks where the frame video signal is recorded, and if it is "0011". To #C-3 “0011
”, the flow branches to #C-5.

#c-:(; It is detected whether the memory address N+1 is "0010", that is, the track being accessed by the head 3-2 is the inner track of the two tracks where the frame video signal is recorded, and "00IO ”, the flow branches to #C-4; if not “00.10”, the flow branches to #C-5.

#C-4; Head 3- in #C-2 and #C-3
When it is detected that frame video signals are recorded on the two tracks that are being accessed by 113-2, the flow reaches this step, the field flag is cleared, and the frame mode is set.3. C-5, 3rd
At the pH shown in the figure, L E I ) 4 I I A lights up, the PB mode flag is set, and the regeneration operation is started.

:C-5-1; In this step, the CPU 40 controls the character generator 84 to temporarily stop generating characters.

The CPU 40 also outputs the I demodulated by the data demodulator 12.
D DATA is stored in the RAM 27.

#B-5-2; Determine whether or not it is in ID display mode, and if it is in display mode, proceed to #C-5-3;
If not, proceed to #C-6'.

#C-5-3; The CPU 40 reads the ID demodulated by the data demodulator 12 from the RAM 27, and reads the ID demodulated by the character generator 8.
4 to generate a character pattern. Therefore, the ID is displayed on the monitor I3 superimposed on the video signal reproduced from the magnetic sheet. Then the flow is #C
-Proceed to 6.

#C-6; If the I'll mode setting switch 53 continues to be turned on, this step is repeated, and if it is turned off, #Δ- is set via #A14 shown in FIG.
Return to 1.

Next, using Fig. 11, set the interval time setting switch 5.
Subroutine 0, which is called when 7 is turned on, will be explained. First, in the subroutine ##G-0, the timer '1' is initialized to 0 and the interval time '1'1 is displayed on the 7-segment LED 25.

#G-1; When it is detected in #A-7 of FIG. 6 that the interval time setting switch 57 is turned on, the timer T' is initialized to 0, and then the flow reaches this step, Furthermore, when the 10 key switches 63 to 72 are turned on, the signal goes to #G-2, and the 10 key switches 63 to 72 are turned on.
When 72 is not turned on, the flow branches to #G-3.

#G-2; Interval time Ti! Interval time 'r set by 0 key switches 63 to 72
Transforms into i.

sc-: s + +o Determine whether or not the switches other than the key switches 63 to 72 are turned on.
Branch to 5.

#G-4, detects whether or not the interval time setting switch 57 is on, and when it is on, #G-
1 is not turned on, the flow branches to #A-1 shown in FIG.

#G-5: Increase the aforementioned 'r' by 1. The flow shifts to #G-6 at 1 second m.

However, T' is a timer that is incremented by 1 every second, and no addition is made if less than one second has elapsed.

#G-6; Determine whether 'I' is 10 or not, and
If ' is 10, 'r' is added to #A-1 shown in Figure 6.
is not 10, branches to #G-1 and returns to # above.
Repeat the loop of G-1, #G-3, #G-5 and #G-6 (Return to #A-N when '1' becomes lO).

Therefore, in the above-mentioned subroutine ■, if the pond switch is not turned on within 10 cycles after the interval time setting switch 57 is turned on, the process returns to #A-1 shown in item x1 and the interval time setting is canceled. .While executing the subroutine ◎, of course the interval time'
I' i is 2 digits 7 segments 1, E l) 25
Gm is displayed, but #G -61,: It is #A
The display of the interval time Ti required to return to -1 is stopped.

Also, in this subroutine ■, the interval time ′
When I"i is set to "C)", an external trigger mode is set in which an operation is performed when connecting to a blink, for example, as described in subroutine (2) as a reproduction operation.

Next, subroutine (2) called when the REC switch is turned on will be explained using FIG. 12.

#N-1; When it is detected that the REC switch 52 is turned on in #A-2 of FIG. 6, the flow reaches this step, and it is detected whether the January 3 mode flag is cleared or not. However, if it is not cleared, the flow returns to #A+4 shown in Fig. 6 (r
<"rs) When it is cleared, the flow branches to #N-2.

Therefore, if the REC mode is not set, no recording will be performed even if the REC switch 52 is turned on.

#N-2, it is determined whether the N address of the memory is "oooo", that is, whether the track being accessed by the head 3-1 is unrecorded or not, and if it is not unrecorded, as shown in FIG. The flow returns to #-14, and if it is unrecorded, the flow branches to #N-3.

#N-3; It is determined whether the field flag is set, and if it is set, the flow branches to #N-5; if it is not set, the flow branches to #N-4.

#N-47 This step will be performed when the frame recording mode is set, but the memory N+I M
It is determined whether the track number is "0000", that is, whether the track being accessed by the head 3-2 is unrecorded. If it is not unrecorded, the flow goes to #A-14 shown in FIG. return. If it happens again, please let us know in advance! ≧■riC, 1, ED4
4B is blinking.

This track was also unrecorded. In this case, the flow branches to #N-6.

#N-5; Magnetic sea!・L on one track on 1
A field worth of video signals is recorded by the head 3-1. At this time, SW6 shown in FIG. 1 is turned off and the output of the character generator 84 is no longer output to the monitor. Also, 0001 is set in the memory address N.

#N-6; When the flow reaches this step, the frame recording mode is set, so the video signal for one field is sent to each of the two tracks on the magnetic sheet 1 to the head 3-1.3-. Recorded by 2. 0011 is set at memory address N and 0010 is set at address N-1-1.#
SW6 is turned off similarly to N-5. Next, the step motor 24 is driven to shift the head 3-1, 3-2 inward by one track.

Note that when #N-5 and #N-6 are executed, SW2 to SW5 are driven as explained in FIG. Also #N-6
When step q is executed, the CPU 40 reads the set ID from the RAM 27, and outputs it to the data modulator 14, so that the ID modulated by the data modulator 14 into a DPSK signal is Recording amplifier 1
6, where it is superimposed on the video signal and ID recording is performed. However, the display mode of [0] is the 20th display mode described later.
In the case of Figure C), even if the data is set, the ID
will not be recorded. However, DATA indicating whether it is the inner track, outer track, or field recording of the frame
is simply recorded together with the video signal. Also the second
Even in the display mode of Figure 0 a) and b) #N-5. #N-
By executing step 6, the I[DATA signal no longer appears on the monitor because SW6 is turned off during recording.

@N-7: The REC execution flag is set and SW6 in FIG. 1 is turned on.

By executing #N-1 to #N-7, when the set ID is generated by the character generator 84, superimposed on the video signal, and output to the monitor, the REC
The character signal that is generated only during execution is SW in Figure 1.
6 will turn it off and the characters will disappear. At #N-7, SW6 is turned on again, so 10 DATA is displayed again.

#N-8; Call subroutine ◎ and head 3-
If 1 is accessing a track other than the 50th track, #
The flow moves from DL#D-2 to #D-3. Then #D-3 to #D-1
Execute 4 and move heads 3-1, 3- to the inner circumference side by one track.
Move 2. #N-6 in frame recording mode
Since the heads 3-1 and 3-2 have been moved to the inner circumferential side by l track in advance, even in the frame recording mode, the head 3-1 can record the track next to the track recorded in #D-14. to access. Further, when the track recorded by the head 3-1.3-2 has been recorded, the RECSLED 44B shown in FIG. 3 blinks to warn the user.

The flow then branches from #D-15 to #D-19 and #
The flows shown in #D-20 to #D-34 are executed via D-19.

That is, if the track feed speed setting value is single, the flow branches from #D-21 to #D-34, and returns to #N-9 according to the REC execution flag set in advance in #N-7. .

If 2 screens or 5 screens per second are set, subtract the WAIT TIMER register by the time necessary for recording in #D-28, and then
TIMER Regis evening count shite W A 1
'I"I' I M E When the I Selezisk becomes O, the flow is from #1)-33 to #D-3/I to the REC execution flag set in #N-7 in the same way as above. Follow the instructions to return to #N-9.

#N-9; Clear the REC execution flag.

#N-10; This step is similar to #D-20, and the set value of the track feed speed is read from the memory.

#N-It; If the set value of the track feed speed is single, go to #N-12. If not, go back to #A-14 shown in FIG. 6.

#N-+2: ) When the rack feed speed is set to single, this step is repeated as long as the REC switch 52 is turned on, and subroutine ■ is executed again to control so that no recording is performed. .

#N when the track feed speed is set to other than single and the REC switch 52 is turned on.
-11 to #-1 via tI to #-1, #A-2
The subroutine (with) is skipped 11 degrees and the above-described flow is executed, and as long as the REC switch 52 is on, recording is performed continuously at the set track feed speed. If the REC switch 52 is turned off, the flow is #A-
1/l, #Δ-! , the process proceeds to #A-2, but the continuous recording ends without calling subroutine (2) in #A-2.

Next, the subroutine (2) called when the program setting switch 58 is turned on will be explained using FIG.

$11-1; When it is detected that the program setting switch 58 is turned on in #A-8 of FIG. 6, this step is reached, and it is determined whether or not the 13B mode flag is set, and the set When it is set, it is #H-2, and when it is not set, it is #H-2.
#A-11, shown in the figure: Return (RTS).

This step is provided to prohibit program settings in the recording mode. That is, in this embodiment, when programming and setting, a playback mode is selected in advance, so that program settings can be made while checking the video recorded on the magnetic sheet 1, for example, on a monitor.

Further, by automatically setting the Pal mode flag when the program setting switch 58 is turned on, the operation to the reproduction mode can be performed automatically.

In this case, a CALL C that calls the subroutine ◎ may be provided to perform the same steps as the subroutine ◎, that is, in place of the step shown in #11-1.

@ll-2; No. [41] where the program is stored
When a program is played back in the program track memory indicated by Jl, the register (2) indicating the address where the track number to be played next is stored is set to 0.

#II-:S; Sets the program playback mode flag indicating the program playback mode and returns to #-1.

Next, the 15th subroutine ■ is called when the program track setting switch 62 is turned on after the program playback mode is set by the subroutine ■.
This will be explained using figures.

#I-1; Determine whether the program playback mode flag is set, and if it is set, #■-2
is not set, the flow branches to #A-1.

Therefore, when the program playback mode is not set by the program setting switch 58, no program setting operation is performed even if the program track setting switch 62 is turned on.

#T-2: The same contents as the contents of the register S (initialized as S:() when the power is turned on in #l) indicating the start address where the program of the program track memory is stored are stored in the register M. Write.

#I-3; The data in the program track memory at the address stored in register M is
stored at a larger address. In other words, the data indicating the track number stored in the program track memory is stored at an address larger by l than the address where the data is stored.

#l-4; Write the value obtained by adding 1 to the contents of register M to register I.

#I-5; Subtract 1 from the contents of register M.

#I-6; Determine whether the contents of register M are 0 or not,
If it is 0, the flow branches to #■-7, and if it is not O, the flow branches to #I-3.

The flow from #I-3 to #1-6 is repeated, and when the contents of register M become 0, all data stored at each address in the program track memory is transferred to an address larger by l. Therefore, repeat the flow and #! When the flow branches from -6 to #1-7, no data is stored at address l of the program track memory.

#I-7; The number of the track that the head 3-1 is accessing is stored at address l of the program track memory. Therefore, by turning on the program track setting switch 62, the number of the track where the video being accessed by the head 3-1 and being reproduced is recorded is programmed.

#I-8; Add 1 to the contents of register S. By executing this step, register S always has #■
The first address (largest address) where the data of the program track memory moved by executing the flow from -3 to #I-6 is stored.

#I-9; If the program track setting switch 62 is turned on, repeat this step, and if it is turned off, return to #A-1.

If the user wants to continue setting programs, turn on the track UP switch 54 or the track DOWN switch 55 to set the heads 3-1, 3-.
Program settings can be made by changing the track being accessed in step 2 and turning on the program setting switch 62 while checking the reproduced video when the desired track is played back.

Note that each time the program setting switch 62 is turned on, the 14th
The data stored at each address of the program track memory shown in the figure is stored at an address larger by l. Also, during program setting, the contents are exactly the same as the register S register (2).

Next, by turning on the program setting switch 58 and the program track setting switch 62, the
1-fr-+ //2Iechurutei 2imonni lfuru l and Interval playback in which recorded tracks are played back at a set interval time in order from the track being accessed by head 3-1. The programs executed when performing the above will be explained using FIGS. 16 to 18.

First, the subroutine (2) called when the start switch 60 is turned on will be explained with reference to FIG.

#-i; When it is detected that the start switch 60 is turned on in #A-11 of FIG. 6, the flow reaches this step, and it is detected whether the PB mode flag is set and the PB mode flag is set. When the mode flag is not set, the flow branches to #A-1, and when the PB mode flag is set, the flow branches to #-2. Therefore, in this embodiment, if the playback mode is not set in advance, interval playback and program playback cannot be performed, so even if the start switch 60 is turned on by mistake during the recording mode, interval playback and program playback will start. It is possible to prevent this from happening.

Also, if you provide a step similar to the step shown in subroutine ◎ instead of -1 in #, you can make it possible to start playing the interval playback program immediately by simply turning on the start switch 60 without setting the playback mode in advance. .

-2 to #: It is determined whether or not the program reproduction mode flag is set, and if it is set, the flow branches to #-13. If it is not set, the flow branches to #-4.

Here, the flow will be described when the program playback mode flag is not set, that is, when interval playback is performed.

-4 to #; Determine whether the N address of the memory is "oooo", that is, the track accessed by head 3-1 is unrecorded, and if it is unrecorded, it must be 16 unrecorded at #. The flow branches to #■(-5. Here, first,
Assuming that the track being accessed by the head 3-1 is unrecorded, the flow from #1 to #16 will be explained.

According to this embodiment described below, when the track being accessed by the head 3-1 is other than the 49th or 50th track, the interval playback is performed from the track to the track being accessed by the head 3-1. When it is the 49th or 50th track, only the tracks that have been recorded sequentially from the 1st track are played back, but between #-2 and #-4, the head 3-1 is moved to the 1st track. If a step of driving the step motor 24 is inserted to access the tracks, only the tracks that have been recorded sequentially from the first track are always reproduced.

Therefore, when the head 3-1 is not accessing the first track but is accessing another track, it is extremely effective for automatically performing interval playback sequentially from the first track to perform a search.

-6 to #: Sets the automatic track advance flag indicating that interval playback is in progress.

-7 to #; It is determined whether or not the field flag is set, and if it is set to #18, the flow branches to #■ (-9).

#-8; It is determined whether the track that the head 3-1 is accessing is the innermost track by detecting whether N is 50, and it is detected that N is 50. In this case, the flow branches to #-10, and if 50 is not detected, the flow branches to #K-11.

-9 to #; Indicates whether the track that the head 3-1 is accessing is one track outside the innermost circumference.
The determination is made by detecting whether or not 49.
When 9 is detected, the flow branches to #-10 and when 48 is not detected, the flow branches to #-11.

-10 for ≠; In this step, the interval time T set by executing subroutine ■
It is determined whether or not i is "O". As will be described later, when the interval time Ti is "0", the head 3-
In this mode, when the interval time Ti is set to "O" for such a mode, the flow shifts to #A-1, and when it is not set to "0", the flow shifts to #-. The flow branches to 12.

tK-11; Call subroutine ■, #D-1
The flow shown in ~#D-18 is executed.

When subroutine O is called in subroutine ■, the PB mode flag is set, so the flow branches from #D-2 to #D-9, and at #K-4, the track accessed by head 3-1 is checked. When it is determined that a track on the outer circumference side of the frame and one track inner circumference than this track is the inner track of the two tracks on which the frame video signal is recorded, and that the head 3-1 is not accessing the 49th track. Heads 3-1 and 3-2 are @
When the heads 3-1 and 3-2 are shifted inward by two tracks by D-12 and #D-13 and no discrimination is made, the heads 3-1 and 3-2 are shifted inward by one track by #D-13.

If a frame video signal is recorded in the track being accessed by the heads 3-1 and 3-2, the field flag is cleared and the flow moves from #D-19 to #D-14.

#-12; Call subroutine ■#E-1~
The flows shown in #E-13 and #D-14 to #D-19 are executed, and the tracks on the outer circumferential side adjacent to the track accessed by the head 3-1 at -4 in # and the outer circumferential side by one more track are executed. When frame video signals are recorded on two of the tracks, the heads 3-1 and 3-2 are #E-
12, #E-13 shifts the track by two tracks toward the outer circumference; otherwise, #E-13 shifts only one track toward the outer circumference.

Also, # is the same as -11 (if a frame video signal is recorded in the track being accessed by 3-L3-2, the field flag will be cleared and the flow will be as follows)
Move from #D-19 to #K-13.

-13 to #: Determine whether the track being accessed by the head 3-1 is the outermost track by detecting whether the content of register N is 1, and if it is detected that it is 1. If it is detected, the flow branches to #-14, and if l is not detected, the flow branches to #-12. Therefore, if the flow branches to #K-12 at #K-8 or #-9, that is, head 3-
When the head 3-1 is accessing the 49th track or the 50th track, the head 3-1 is controlled to access the 1st track by repeating steps -12 to # and -13 to #. .

-14 to #; Clear the automatic track feed flag.

As explained above, the flow from #K-14 to #K-14 is executed, and when the flow branches from #K-4 to #K-5, the head 3-1 moves to the track where the video signal is recorded. Tracks on which no video signals are recorded are essentially skipped without being played back.

Furthermore, by executing the flow from #14 to #K-14, when the flow branches from #K-4 to #K-5, the two tracks being accessed by heads 3-1 and 3-2 are #D-1 if a frame video signal is recorded
Since the field flag is cleared in 8,
Frame playback mode is automatically set. Further, when a field video signal is recorded on the track being accessed by the head 3-33-2, the field playback mode is automatically set. Therefore, during interval playback, the most appropriate playback mode is automatically set according to the recording method of the video signal.

-5 to #: The interval time Ti set in subroutine O is fetched from the memory into the register T' of the CPU 40.

-15 to #; Interval time T in the same way as -10 to #
Detect whether i is “0” and if it is “0”, #K
-17, and if not "0", the flow branches to 3 to 1'16. Here, the following explanation will be given on the assumption that the external trigger mode is not set.

# -16; Timer 1 starts timing operation and proceeds to # -18.

-xs to #; It is detected whether or not the timer l has clocked for 1 second. If the timer is being counted, the flow branches to #K-19, and if it is in the middle of counting, the flow branches to #-20.

-20 to #; It is detected whether the stop switch 61 is turned on, and if it is turned on, the flow branches to #A-1; if it is not turned on, the flow branches to #A-21. Here, when the flow branches to #A-1, steps #A-1 to #A-12 are executed again, so when the stop switch 61 is turned on in the normal state, the flow is #A-1.
The subroutine [phase] will be called from step 12.

The subroutine [phase] will be explained below using FIG. 17.

#M-1; Detects whether the program playback mode flag is set and returns #A if it is not set.
-14, and if set, the flow branches to 8M-2.

8M-2; It is detected whether or not the program playback execution flag is set. If it is set, the flow branches to 4M-3; if it is not set, the flow branches to #M-4.

1M-3; Make the contents of register ■ the same as the contents of register S.

1M-4; Set register S to 0 and then execute 4M-3.

This subroutine [phase] will be described in more detail in the program playback mode. Below, #K-21 and later will be explained in detail.

-21 to #; Detects whether the track UP switch 54 is on, and when it is detected that it is on, calls subroutine ■ and shifts the heads 3-1 and 3-2 to the inner circumferential side and turns it on. If it is not detected, the flow branches to #-22.

-22;) It is detected whether the rack DOWN switch 55 is on, and when it is detected that it is on, subroutine (2) is called, and the heads 3-1 and 3-2 are shifted to the outer circumferential side. When it is not detected that it is on, the flow branches to #-18.

-19 to #; subtract 1 from T'.

-23 to #; -24 to # when T' is "0",
When T' is not "0", the flow branches to #-16.

Therefore, by executing the steps #15 to -23 described above, turning on the track UI' switch 54 and track DOWN switch 55 during interval playback will record data on the track adjacent to the track being played. You can play back the videos that are on the screen. In that case, by keeping switch 54 or switch 55 on, the tracks being played can be automatically updated sequentially according to the track feed speed set in subroutine [F], and the number of tracks during interval playback can be updated automatically. You can also easily play back the video in front of the screen.

Furthermore, in this embodiment, before turning on the switches 54 and 55, when playing back a video recorded on a track adjacent to the track being played back by turning on the track UP switch 54 and the track DOWN switch 55, When the remaining time of the interval time Ti of the track being played in is played back, the flow moves from # -23 to # -24 and is updated to play a new track. As shown by the dotted line,
By jumping the flow to -5 at #, it is possible to reset the interval time T' so that the image updated by the switches 54 and 55 can be reliably observed for a certain period of time.

When the interval time T' ends and the track to be played is updated, it is detected whether or not the program playback mode is set, and if it is set, it is set to -3 in #. If not, the flow branches to #-6.

Next, about the routine ◎ that branches when the program playback mode flag is set at -2 in #, the 18th
This will be explained using figures.

#O-1; Detects whether the contents of register S is “0” and when “O” is detected, transfers “0” to #A-1.
When it is detected that this is not the case, the flow branches to #O-2.

As mentioned above, register S stores the start address of the program in the program track memory, and the content of register S is "0" if no program is stored in the program track memory. Since it shows the current value, when it is “0”, the A in Fig. 6
Return to

#O-2; Register! It is detected whether the content of is “O” or not, and when “0” is detected, it is sent to #O-3 and “0” is detected.
”, the flow branches to #O-3.

As mentioned above, register I stores the address of the track memory where the track number to be played next is stored when program playback is executed.
When executing program playback, l is subtracted every time one step program playback is executed, as shown in #0-14 below.

Therefore, the flow branches to #O-2, and the register! The fact that is detected as "O" indicates that the program has been set and the register S is not "0", and that the steps of program playback have been executed. In other words, when the program playback is executed - times, #0
-3, the flow branches to #0-5 while the program playback is being executed -3.

#O-3, take the interval time Ti set in subroutine ■, detect whether the interval time Ti is “On”, and if it is “0”, the flow starts from routine 0 #
Returning to A-1, the program playback operation ends.

Therefore, in the external trigger mode set by setting the interval time to "O", the program playback operation is stopped after the program playback has been executed one time.

Also, during normal program playback when the interval time Ti is set to a value other than "0", #
The flow moves to O-4.

#O-4, write the contents of register S to register ■.

Program operation is started again.

#O-, j; Data (■) at the address of the program track memory set in register I (data written to the address set in register ■ of the program track memory is shown in parentheses) Read out.

#O-6, subtract data (1) from N indicating the track number currently being accessed by the head 3-1, and if it is less than “On, #O-7
, if it is smaller, the flow branches to #O-8.

#O-7: Set field flag. This set is for prohibiting head feeding in the frame mode like #D-8.

#O-8; Shift the heads 3-1 and 3-2 by one track in the outer circumferential direction.

#O-9; Detects whether the data (1) is equal to N indicating the track number that the head 3-1 is accessing. If they are equal, the data is changed to #0-10. If not, the data is smaller than N indicating the track number. If (I) is larger, the flow branches to #0-11.

#0-10. Heads 3-1 and 3-2 in the inner circumferential direction
Frame playback and field playback are automatically performed depending on whether the video signal recorded from the start is a frame video signal or a field video signal.

Furthermore, by repeating #0-6 to #0-1o, Herad 3
-1 is controlled to access the track programmed in the program track memory.

#0-14; Subtract 1 from register ■.

#0-15; The program playback execution flag is set. This step allows the flow to be branched by determining whether the program reproduction mode flag is set at 9 or -24.

The flow then ambles to #K-5.

Therefore, when branching to routine ◎ at -3 in #, it is first determined whether or not a playback program is actually set, and then it is determined whether or not the external trigger mode is set, and the external trigger mode is set. When this is the case, the program is executed only one way; otherwise, the program is played repeatedly.

Next, a flow when the external trigger mode is set will be explained. When the external trigger mode is set, the flow branches from #-15 to #K-17.

#K-17'; Detects whether the printer connected as an external device is busy (executing a print operation) or not, and if it is busy, sends a message to #A-1; if it is not busy, sends a message to #. The flow branches at 18'.

#K-18', Sends a print start signal to the printer as an external device. The print start signal is executed by setting the signal level of a terminal connected to the printer to H level.

#119'; 150m5ec wait #120'
: When the printer is busy, the flow branches to #-21', and when it is not busy, the flow branches to #K-24.

Detects whether the stop switch 61 is turned on or not. If the stop switch 61 is not turned on, the flow goes to @20', and when it is turned on, the flow returns to #A-1.

When executing steps 9K-17' to #K-21' described above, if the printer connected as an external device is busy, the flow returns to #A-1 as described above.
The flow shown in FIG. 16 is repeated until another switch is turned on again. If the start switch 60 is turned on again while repeating the flow shown in FIG. , will execute #117' again.

In addition, if a printer is not connected as an external device, use the printer 1 shown in Figure 1 in #K-17'.
3' Throat! The terminal into which the signal from the G signal output terminal is input becomes the oven and becomes I (level).Therefore, even though the external trigger mode is set, if a device such as a printer is not connected, the head 3- 1.3
The track being accessed by -2 continues to be played,
The track being played is not updated.

Also, if a printer is connected as an external device and the printer is not busy,
When the flow advances to K -18', send the print start signal to the printer and then change # to 1 shown in -19.
The printer operation starts after waiting for 50 m s p c, and if the printer becomes busy, the printer operation continues until the printer operation is finished or the stop switch 60 is turned on. 21' (Repeat, when the printer operation is finished, the flow branches from #-120' to $-24, and program playback is set by detecting whether the program playback mode flag is set. If program playback is set, the flow branches to #-3 mentioned above, and if program playback is not set, the flow branches to #K-6. When the stop switch 60 is turned on, the flow is as described above.

Further, if the external trigger mode is selected when program playback is set, the program playback operation is stopped after the program playback has been executed three times as described in #O-3.

Further, according to this embodiment, even if the external trigger mode is selected and program playback is not set, since -10 is set in #, the head 3 -
1. When the playback is performed in sequence from the accessed track in 3-2 to the last track, the playback operation is stopped.

Therefore, in external trigger mode, regardless of whether programmed playback is set or not, the playback operation stops after the normal playback is performed, so the printer is used as a device that performs external triggers. When using , only −-way printing is performed.

On the other hand, in modes other than external trigger mode, even if program playback is set or not, playback starts again from the beginning after playback is performed in a predetermined order. will be held. Therefore, when such a playback device is used in a mode other than the external trigger mode, so-called endless playback can be performed because playback is performed repeatedly in a predetermined order.

Further, although a printer is shown as an external device in this embodiment, it may be a device having an electric transmission function, or any other device as long as it processes a reproduced signal.

Next, the case of setting an ID will be explained.

When the IO main key switches 63 to 72 are turned on in the flow (2), the flow branches to the subroutine (2) shown in FIG.

#R-1; #R if the PB mode flag is set
The process branches to -10 and returns to the flowchart (2). Therefore, in a mode other than the recording mode, even if the IO main key is turned on, virtually nothing is executed in this subroutine. If the PB mode flag is not set, that is, if it is in recording mode, the flow branches from #R-1 to #R-2.

#R-2: Here, ID setting mode, that is, ID is superimposed on the video signal, and it is determined whether the mode is monitoring mode or not. The method for setting this mode will be described in detail with reference to FIG. 20. If this mode is not selected, the process branches to @R-10 and returns to #A-1 in the flowchart shown in FIG. If this mode is selected, the process branches to #R-3.

#R-3; The CPU 40 retrieves the set position from the register P of the RAM 27 for storing the set position indicating where on the monitor the ID set here is to be displayed.
The data corresponding to the turned-on switch among the 10 key switches 63 to 72 is written and stored in the address corresponding to the set position in the RAM 27. Then CP
U40 controls character generator 84 to display the data on monitor B according to the read set position.

#R-4; Here, wait until the 10 key switches 63 to 72 are turned off once. If the switches that were turned on are turned off, the flow advances to #R-5.

#R-5, where the setting position of data other than the year, month, and day of the ID is o-i as shown in FIG.

Since there are 11 points up to, if the register P is equal to IO, the process branches to #R-6, otherwise it branches to #R-7.

#R-6; Here, register P is set to 0, and D
The setting position of ATA is initialized.

#R-7; Here, 1 is added to the value of register P and D
The ATA setting position moves to the next setting position.

#R-7-1; The data and data at the position stored in register P blink (blink).

#R-8; In this step, it is determined whether the IO key switches 63 to 72 are turned on, and if they are turned on, the process branches to #R-3 and the 10 key switches are activated according to the flow described above. set I
D is displayed on the motor 13.

If it is not turned on, the process branches to #R-9.

#R-9; Here, it is determined whether any switches other than the 10 key switches 63 to 72 are turned on, and if they are not turned on, the process branches to R-8. If it is turned on, it branches to #R-11.

#R-9-1; Stop blinking the ID displayed on the monitor. Flow proceeds to #R-10.

#R-11; Here, register P at the ID setting position
Set 0 to #R-9-1 and initialize the ID setting position.
Proceed to.

#R-10; Return to the flow of ■.

As explained above, when the PB mode flag is not set and the ID setting mode, that is, the mode in which the set ID can be monitored, the 10 key switch 6
Each time a switch 3 to 72 is turned on, the CPU 40 controls the character generator 84 to generate data at a position determined by the register P.

Next, the ID switch 73 will be explained.

When the switch 73 is turned on, the subroutine ◎ shown in FIG. 20 is called from the flow shown in . Here, subroutine ◎ will be explained.

#Q-1; Here, determine whether or not the PB mode flag is set, and if it is set, #Q-2
Otherwise, the process branches to #Q-7.

#Q-2. Here, it is determined whether the mode is ID display mode, that is, whether the mode is such that the ID is output on the monitor superimposed on the video signal. If in ID display mode, go to #Q-4, otherwise go to #Q
- Branch to 3.

#Q-3; Here, the CPU 40 controls the character generator 84 to stop displaying the ID output from the generator 84. From here, the flow advances to #Q-6.

#Q-4, here, the CPU 40 imports the reproduced ID from the RAM 27, and the flow is #Q-5.
Proceed to.

#Q-s; Here, the CPU 40 controls the character generator 84 based on the reproduced ID, and causes the character generator 84 to output the reproduced ID as a character pattern as shown in FIG. 21(a). The flow then proceeds to #Q-6.

#Q-6; Here, if the switch 73 is turned on, the process waits; if it is turned off, the flow proceeds to the next step and returns to the flow of (2).

#Q-7; PB mode flag is not set.
First, when in recording mode, it is determined whether or not it is in ID setting mode. That is, if the ID is in a mode in which the character generator 84 outputs a character pattern superimposed on the video signal, the flow advances to #Q-9. Otherwise, the flow advances to #Q-8.

#Q-8, where the character “ID” is the character generator 84
If it is likely to be determined whether or not the mode is being output by
The flow advances.

#Q-9, in this step, the CPU 40 uses the character generator 8
4 to stop displaying the ID, and the character generator 8 generates a two-character pattern "ID" as shown in FIG. 21(b).
4 to set the "ID" character display mode. The flow then proceeds to #Q-6. That is, when the ID switch 73 is turned on in the ID setting mode, the "ID" character display mode is set.

#Q-1o; - In this step, the CPU 40 controls the character generator 84 to stop displaying all character patterns as shown in FIG. 21(C). Then the flow is #Q-6
Proceed to.

#Q-11; If the flow reaches this step, I
Since it is neither the D setting mode nor the "ID" character display mode, that is, the mode is set to stop displaying the ID on the monitor, the CPU 40 takes in the set ID from the RAM 27, controls the character generator 84, and displays the set ID. The character generator 8 uses the ID as a character pattern as shown in Fig. 21(a).
Output from 4. That is, the ID setting mode is set by this step. The flow then proceeds to #Q-6.

As explained above, each time the ID switch 73 is turned on, the I
The display format of D will be rewritten.

In other words, in the playback mode, the ID switch 73
ID display mode in which the playback TD DATA is superimposed on the video signal and monitored every time you turn on the playback ID
The ID non-display mode in which no data is output will be repeated. Specifically, I shown in FIG. 21(a)
The ID non-display mode shown in D display mode (c) is repeated. In addition, when in recording mode, there is an ID setting mode that displays all IDs to be set, and an “ID setting mode” that displays all IDs to be set.
The "ID" character display mode in which only characters are displayed and the mode in which no ID is displayed on the monitor are repeatedly switched each time the ID switch 73 is turned on. Specifically, as shown in FIG. (a).

The modes shown in (b) and (C) will be switched repeatedly. The ID display in the recording mode will be further described below. FIG. 21(a) in recording mode.

When recording a video signal in the mode shown in (b), the ID is modulated with the video signal in #N-5 and #N-6 in FIG. 12, is modulated into DPS, and is further frequency-multiplexed with the video signal and recorded. It turns out. Also, Figure 20 (C)
When recording a video signal in this mode, I
D data is not recorded. However, DATA indicating whether it is inside or outside the frame or field recording is always sent together with the video signal.

That is, in this embodiment, depending on the number of times the ID switch is pressed, the monitor 1 is
It is possible to switch the display related to ID 3.

In addition, in this embodiment, in the recording mode in which the ID is recorded together with the video signal, there is an ID setting mode in which the display shown in FIG. 21(a) is performed, and in the ID setting mode in which the display shown in FIG.
The reason for providing these two display modes will be explained below.
It is possible to set the year, month, date and 11-digit number, but if you try to display all the ID information as shown in Figure 21 Ca'), it will occupy a considerable area on the screen of the monitor 13. Therefore, there is a problem that the viewing of the image may be obstructed, so a display mode as shown in FIG. 21(b) is provided to solve this problem.

Next, a method of displaying the reproduced ID in the reproduction mode will be explained. That is, in the recording mode, the image shown in FIG. 21 (
A display method for reproducing the ID recorded together with the video signal when the modes shown in a) and (b) are set by the [> switch 73 will be described. In the playback mode, when the head is moved to a new track, the ID recorded on that track will be played back on the monitor 13. This is done by demodulating the ID reproduced by the data demodulator 12 shown in FIG. 1, reading this output by the CPU 40, and further driving the character generator 84. Here, the ID read by the CPU 40 is held in the RAM 27 by the CPU 40. The display of such 10 is shown in FIG. 21(a).
However, in this embodiment, the characters stored in the RAM 27 are displayed in the following two modes I) and II).

I) A first display mode that is displayed when an ID recorded in which only the year, month, and date are set as ID data and no other data is set is played back.

(2) A second display mode when playing back an ID in which the date and other numerical data are set together as IDDΔTA.

The ID display in I) is shown in FIG. 22(a).

FIG. 22(b) shows the ID display in (2).

That is, for ■), only the year, month, and day are displayed at the bottom right of the monitor, and for ■), the year, month, date and other data are displayed at the bottom right of the monitor. Therefore, the ID information is always displayed in the lower right corner of the monitor screen to prevent it from interfering with the video signal as much as possible.

Further, in this embodiment, the display is displayed in the lower right corner of the screen, but it may be displayed anywhere as long as it is in the corner of the screen.

In order to execute this operation, after reading the output signal of the data demodulator 12 shown in FIG.
It is sufficient to generate the characters after confirming that all data other than the daily amount has not been set. In other words, the above I), If
), the CPU 40
controls character generator 84.

Also, if it is determined that data other than the date is not the DATA recorded by this device, the 22nd
The display shown in Figure (b) is performed.

This is ok (known check code ID DATA
This can be determined by recording it as such.

Next, a case will be described in which the year, month, and day are set as the ID. In the flow (2), when the year setting switch 74 is turned on, the flow jumps to the subroutine (2) shown in FIG.

#S-1; If the PB mode flag is set here, the flow advances to #5-14 and returns to the flow of (2). If not set, proceed to #S-2.

#S-2: Now ID setting mode, i.e. video °
It is determined whether the mode is to superimpose ID data on a signal and output it to a monitor or printer. If it is not in this mode, proceed to #5-14 and return to the flow of (2). If this mode is selected, proceed to #S-3.

#5-37 Here, 1 of the year setting position on the monitor 13
Blinking of the number in the 10th digit of the year setting position means that the character in the position shown in ■ in Figure 24 (a) blinks. This means that the CPU 4
This is accomplished by 0 controlling the character generator 84 to generate or not generate a character at this position. This is done by well-known interrupt processing. The flow then proceeds to #S-4.

#S-4; At this point, wait until the switch 74 is turned off. When switch 74 is turned off, the flow is #S-
Proceed to step 5.

#S-57 Here, it is determined whether the 10 key switches 63 to 72 are turned on. If the IO primary key switch is turned on, the flow advances to #S-6. If not, proceed to #5-12.

#S-6; Here, the CPU 40 writes the input data from the IO main key switch to the RAM 27, and controls the character generator 84 to create a character pattern at the year setting position shown as ■ in FIG. 24(a). generate. The flow then proceeds to #S-7.

#S-7; Blink the first digit of the year setting position. This means that the characters at the position shown in Figure 24 (■) blink.

Blinking is performed by CPU 40 controlling character generator 84. The flow proceeds to #S-8.

#S-8; At this point, wait until the 10 key switch is turned off. When the 10 key switch is turned off, the flow advances to #S-9.

#S-9; Here, it is determined whether the IO main key switch is turned on. If it is turned on, the flow goes to #5-10; otherwise, the flow goes to #5-13.

#5-10; C if the 10 key switch is turned on
The PU 40 writes the data input by the lO main key switch to the RAM 27, and controls the character generator 84 to generate a character pattern at the position shown in ■ in FIG. 24(a), which is the first digit of the year setting position. generate. Then the flow is #
Proceed to 5-11.

#5-11; The CPU 40 controls the character generator 84 to stop the character from blinking at the year setting position. This allows the user to know that the year setting has been completed. Flow proceeds to #5-14.

#5-12. If the 10 key switch is not turned on in #S-5, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, FuDr- branches to #S-5, so repeat steps #S-5゜#5-12, and if switches other than the 10 keys are turned on, go to #5- Proceed to step 11.

#5-13. Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, the flow branches to #S-9, and if it is turned on, the flow branches to #5-11. Therefore, until a switch other than the 10 key is turned on, #S-9. By repeating steps #5-13, the characters at the year setting position continue to blink, prompting the user to set the year using the 10-key switch.

#5-14; If the PB mode flag is set, if the mode is ID setting mode, and if the blinking is stopped by #5-11, the flow returns to step (2) through this step.

As explained above, when the year setting switch 74 is turned on, the number that is the 10th digit of the year setting position starts blinking to inform the operator of the position where data is set. Here, by inputting numbers using the 10-key switch, the data input at the blinking position is generated as a character pattern by the character generator 84, and the CPU holds the data in the RAM 27.

When the setting for the 10th digit is completed, the number at the 1st digit starts blinking, and the DAT is placed at this position in the same way.
Settings for A are performed. Here, when the setting of the first digit is completed, the year setting mode ends and the process returns to the flow shown in ■, but it is also possible to proceed to the flow shown in ■ and enter the month setting mode.

Next, the setting of the month's DATA will be described in detail with reference to subroutine (2) shown in FIG.

In the flow (2), when the switch 75 is turned on, subroutine (2) is called and the month DATA setting mode is entered.

#T-1; If the PB mode flag is set here, the flow advances to #T-16 and returns to the flow of (2).

If the PB mode flag is not set, the flow proceeds to #T-2.

#T-2; Here, it is determined whether the mode is an ID setting mode, that is, a mode in which ID data is superimposed on a video signal and output to a monitor or printer. If it is not in this mode, proceed to #T-16 and return to the flow of (2). If this mode is selected, proceed to #"r-3.

#T-3; Here, blink the 10th digit number at the column setting position on the monitor. The blinking of the 10th digit number at the column setting position means that the character at the position shown by ■ in FIG. 24(a) blinks. This is CPU40
is performed by controlling the character generator 84 to generate or not generate characters. The flow then proceeds to #T-4.

#T-4; At this point, wait until the row setting switch 75 is turned off. When the switch 75 is turned off, the flow advances to #T-5.

#T-5; Here, it is determined whether the lO key switches 63 to 72 are turned on. If the IO key switch is on, the flow proceeds to #T-6; otherwise, the flow proceeds to #T-13.

#T-6; Here, it is determined whether the data input by the 10 key switch is 2 or more. If the number is 2 or more, the flow proceeds to #T-14, otherwise the flow proceeds to #T-7. In other words, in the case of column settings, the flow is branched according to the number set in this step in order to accept the first digit number only when the first number input is "1" or "O". .

#T-7; Here, the CPU 40 stores the input data in the RAM.
27 and controls the character generator 84 to write the character pattern to the position shown in ■ in FIG. 24(a), that is, #.
It is generated at the position blinked at T-3. Flow proceeds to #T-8.

#T-8; Here, blink the first digit number at the column setting position. This means that the character at the position indicated by ■ in FIG. 24(a) blinks. The flow is #T-
Proceed to step 9.

#T-9; Wait until the 10 key switch is turned off. When the lO key switch is turned off, the flow advances to #T-10.

#T-10; Here, it is determined whether the 10 key switch is turned on. If it is turned on, the flow advances to #T-II; otherwise, the flow advances to #T-15.

#T-11; Here, the CPU 40 writes the data inputted by the 10 key switch in #T-5 or #T-10 into the RAM 27, and writes a character in the position shown in FIG. 24, which is the first digit of the column setting position. The generator 84 is controlled to generate a character pattern, and then the flow is #T-12.
Proceed to. In addition, when branching to this step from #T-14, by executing #T-14゜#T-11,
At T-5, the data input by the lO key switch is displayed in the first digit, and "0" is displayed in the tenth digit.

#T-12; Stops blinking of data at column setting position and displays that force setting is completed.

Flow proceeds to #T-16.

@T-13; This step requires 1 in #T-5.
Branches if the 0 key switch is not turned on. Here, it is determined whether any switches other than the IO key are turned on. If it is not turned on, it branches to #T-5, and if it is turned on, it branches to #T-12. That is, lO
#T-5 until the key switch or other switch is turned on. #T
-13 is repeated, and if the 10th key switch is turned on, the flow branches to #T-6, and if any other than the 10th key switch is turned on, the flow branches to #T-12.

#T-14; The process branches to this step when it is determined in #T-6 that the input data is "2" or more. Here, the CPU 40 stores data “O” in the RAM 27.
” and input the character generator 8 to the io digit of the column setting position.
4 to generate a character pattern "θ". The flow advances to #T-11.

#T-15; Here, it is determined whether any switches other than the IO key are turned on. If it is not turned on, branch to #T-1o, if it is turned on, it branches to #T-1o.
Branches into 12.

@T-16; Return to the flow of ■.

As explained above, when the switch 75 is turned on, the 10th digit at the month setting position first blinks, thereby first indicating the position at which data to be input using the 10 key switch is to be set. If two or more pieces of data are input here, "0" is automatically set in the 10th digit and the input data is automatically set in the 1st digit. Of course, if there is an input of 1 or less, 10
Needless to say, the next blinking position that is input in the 1st digit moves to the 1st digit, and the next data input using the 10 key is set to the 1st digit. Therefore, according to this embodiment, when setting the month, it is possible to easily set the force by taking advantage of the fact that 2 or more is never set in the 10th digit.

Further, in #T-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

Furthermore, when the setting of the next first digit is completed, the process returns to the flow shown in (2) in this example, but it is also possible to proceed to the subroutine (2) shown in FIG. 26 and enter the day setting mode.

Next, the day data setting will be described in detail with reference to FIG. When the switch 76 is turned on in the flow (2), the day data setting mode is called and the flow jumps to (2).

#U-1; If the PB mode flag is set here, the flow advances to #U-16 and returns to the flow of (2). # if the PB mode flag is not set
Proceed to U-2.

#U-2; Here, it is determined whether the mode is the ID data SET mode, that is, the mode in which the ID data is superimposed on the video signal and output to the monitor or printer.

If you are not in this mode, proceed to @U-16.
Return to the flow of ■. If you are in this mode,
#Proceed to U-3.

#U-3; Here, blink the 10th digit number at the fixed sunset position on the monitor. 4. Blinking the 10th digit number at the setting position is the character at the position shown in ■ in Figure 24 (a). means blinking. This is CPU40
is executed by controlling the character generator 84 to generate or not generate characters.

The flow then proceeds to #U-4.

#U-4; At this point, the date setting switch 76 is turned off.
wait until it appears. When switch 76 is turned off, the flow advances to #U-5.

#U-5, here it is determined whether the IO key switches 63 to 72 are turned on. If the IO key switch is turned on, the flow advances to #U-6; otherwise, the flow advances to #U-13.

#U-6: Here, it is determined by the 10 key switch whether the input data is 4 or more. If it is 4 or more, the flow goes to @U-14, otherwise #U-
Proceed to step 7. In other words, in the case of column settings, the numbers set in this step are set in order to add a first digit number only when the first number entered is 3", "2", "l", or "O". Branch the flow accordingly.

#U-7; Here, the CPU 40 sends the input data to RA
M27 and controls the character generator 84 to generate a character pattern at the position shown by ■ in FIG.

The flow proceeds to #U-8.

#U-8; Here, blink the first digit of the sunset position. This means that the characters at the positions indicated by ■ in FIG. 24(a) blink. Flow is #U-9
Proceed to.

#U-9; At this point, wait until the 10 key switch is turned off. When the 10 key switch is turned off, the flow advances to #U-10.

#U-10; Here, it is determined whether the 10 key switch is turned on. If it is on, the flow goes to @U-11, otherwise to @U-15.

$U-11; Here, the CPU 40 writes the data input by the 10 key switch in #U-5 or #-10 to the RAM 27, and generates a character at the position shown in Figure 24 ■, which is the first digit of the fixed sunset position. 84 to generate a character pattern, and the flow then proceeds to #U-12. In addition, if #U-14 force V branches to this step, by executing #U-14゜$U-11,
At #U-5, the data input by the lO key switch is displayed in the first digit, and "0" is displayed in the tenth digit.

@U-12; Stops blinking of the sunset fixed position data and displays that the date setting is completed.

Flow proceeds to #U-16.

#U-13; This step includes 1 in #U-5.
Branches if the 0 key switch is not turned on. Here, it is determined whether any switches other than the 10 key are turned on.

If it is not turned on, it branches to #U-5, and if it is turned on, it branches to #U-12. i.e. until the 10 key switch or other switch is turned on.
U-5. The flow of #U-13 is repeated (repeat, if the IO key switch is turned on, the flow branches to # "l'-6", and if any key switch other than 10 keys is turned on, the flow branches to #U-12) .

@U-14: The process branches to this step when it is determined in #U-6 that the input data is "4" or more. Here, the CPU 40 stores data in the RAM 27.
0" is written, and the character generator 84 is controlled to generate a character pattern "0" in the 10th digit of the column setting position. The flow advances to #U-11.

#U-15; Here, it is determined whether any switches other than the IO key are turned on. If it is not turned on, branch to #U-10; if it is turned on, it branches to #U-10.
Branches into 12.

#U-16; Return to the flow of ■.

As explained above, when the switch 76 is turned on, the 10th digit at the date setting position first blinks, thereby first indicating the position where the data to be input using the 10 key switch is to be set. If 4 or more data is entered here, "O" will be automatically set in the 10th digit and the input data will be set in the 1st digit.Of course, if 3 or less is entered 10 for
Needless to say, the next blinking position that is input in the 1st digit moves to the 1st digit, and the next data input using the 10 key is set to the 1st digit. Therefore, according to this embodiment, when setting the day, it is possible to easily set the day by taking advantage of the fact that 4 or more is never set in the 10th digit.

Further, in #U-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

In the embodiment described above, the display is blinked to indicate the setting position, but the setting position may be indicated by other methods such as changing the brightness or changing the color.

Next, the erase sequence will be explained. When erasing data, the erase execution switch 78 and erase standby switch 77 shown in FIG. 1 are used. That is, when erasing is to be executed, the switch 77 is used to put the data into an erase standby state in advance, and then the erasure is executed only when the erase execution switch 78 is turned on. Furthermore, there are two modes for erasing: a mode in which a plurality of tracks are continuously erased, and a mode in which only a single track is erased. Hereinafter, the above operation will be described in detail based on the flowchart (2) shown in FIG. In the flowchart A in FIG. 1, when the switch 77 is turned on, the flow calls subroutine (2) and proceeds to #V-1. At this point, the erase standby state is set, but at this time, the buffer memory E for storing the number of erased tracks contains “
FF" is set. Also, the track number accessed by the head 3-1 on the two-digit 7-segment LED 25 that displays the track number is approximately 2.
The track number display LED blinks (2H) at a cycle of Hz.
z period) allows the operator to confirm that the erase standby mode has been set.

In other words, compared to a method that uses a dedicated display element to indicate that the erase standby state is in effect, the method of this embodiment not only eliminates the need to use such a dedicated display element, but also displays the track number. By changing the display format of the display, the standby state for erasing is displayed, making it easier to recognize the track number that is about to be erased. In addition, in this embodiment, 7 segments L
Although the standby state for erasure is indicated by blinking the display of the ED25, it is of course possible to use other liquid crystals as the display element, and in addition to blinking, the color and brightness of the display may be changed. Various methods are possible, such as changing the form of displayed characters.

In addition, if there is a display that displays other information than the track number, such as the number of free tracks, the display format of the display can be changed as described above to enable the erase standby state. It may be possible to display a certain thing.

The flow then proceeds to #v-2.

#V-2, here it is determined whether or not the PB mode flag is set, and if it is set, the flow advances to #v-4; otherwise, it is determined that the switch 77 is turned off. After confirmation, the flow advances to #v-3.

#V-3; Here, the subroutine ◎ for setting the playback mode described above is called, the playback mode is set, and the flow advances to #v-4. Therefore, when the erase standby switch 77 is turned on, #V- By executing #2 and #V-3, the playback mode is set and the erase standby state is set.

#V-4; Here, it is determined whether the switch 78, that is, the erase execution switch is turned on. @V-4-1 if it is on, #V-1 if not
The flow advances to step 5.

#V-4-1; Here, the branch destination of this step is determined by a switch that is prepared in advance in the case (not shown) of the magnetic sheet 1 and that determines the presence or absence of a claw. In other words, this claw has the function of preventing accidental erasure, and if it is broken off, it is promised in advance not to erase the data. Therefore, if the accidental erasure prevention is set, the flow advances to #V-18. If not set, the flow advances to #v-5.

#V-5; In this step, it is determined whether or not the value set in buffer memory -E (hereinafter referred to as E) for storing the number of erased tracks is "0". The buffer memory E is previously set to "FF" in #v-1, but the setting value can be changed in #V-15, which will be described later. Here, the value set in buffer memory E is “O”! In some cases the flow is #V-1
If not, the flow proceeds to #V-5-1. Next, #v-5-1 will be explained.

@V-5-1; In this step, it is determined whether the value set in the buffer memory E is "FF". If it is "FF", the flow proceeds to #v-6, and if it is not "FF", the flow proceeds to #V-5-2.

#V-5-2; Set the field flag and set the field playback mode.

The flow proceeds to #U-6.

#V-6; Here, display the track number 7
The blinking of the segment LED 25 switches from the 2 Hz set in #v-1 to the fast cycle of 5 Hz. In addition, when performing continuous track erasing, the set track number is displayed on the 7-segment LED 2 instead of the track number being accessed by the head 3-1 in #V-17, which will be described later.
5, but even in such a case, by executing #v-6, the 7 segment LED
Switching is automatically performed so that the track number is displayed at 25. Therefore, the user can confirm which track is currently being erased during continuous track erasing.

At #V-7, :,, knee, the cPU 40 controls the erase signal generator 85 to generate an erase signal, and erase is executed. In addition, when performing erasing, switch 2 shown in Fig. 1 is pressed.
, the switch 3 is controlled to connect at least one of the heads 3-1, 3-2 to a recording amplifier. Here, if the field flag is set, that is, in the field reproduction mode, the erase current flows only to the head 3-1 shown in FIG. If the flag is cleared, that is, if frame playback is selected, the heads 3-1. An erasing current flows simultaneously to both of the signals 3-2, and the video signal for one frame of one track, in other words, for two adjacent tracks, is erased.

In addition, in this embodiment, erasure in frame mode is executed only when the flow advances from @V-5-1 to #v-6 without passing through #V-5-2. There is. In other words, in #V-5-1, the value of buffer memory E is “FF”.
", that is, when the continuous erase mode described later is not selected.

#V-8; Wait until erasing is completed.

When erasing is completed, the flow advances to #V-8-1.

@V-8-1; Here, it is determined whether E is equal to "FF". If it is equal to “FF”, it is single erase mode, so the flow goes to #V-18; otherwise, continuous track erase is set, so the flow goes to #V-18.
Proceed to step 9.

#V-9: Here, the value of buffer memory E is subtracted by 1. Flow proceeds to #V-10.

#V-10; In this step, it is determined whether the value of buffer memory E is larger than O.

That is, the number of tracks to be erased when continuous track erasure is set is detected, and if it is greater than 0, the flow proceeds to #V-11; otherwise, it is assumed that continuous track erasure has ended. Proceed to #V-18.

#V-11; In this step, it is determined whether the stop switch 61 is turned on. If it is turned on, the flow branches to #V-18, and if it is not turned on, the flow proceeds to lt#V-12. That is, the continuous erasing mode, which will be described later, is selected, and if the stop switch 61 is operated while this mode is being executed, the continuous erasing can be interrupted. Flow then proceeds to @V-12.

#V-12: In this step, it is determined whether N of the track number buffer memory is 50 or more, that is, whether the track being accessed by the head 3-1 is the final track. If so, the flow proceeds to #V-18 and the erase operation is terminated. If not, the flow proceeds to #V-13.

#V-13; By executing this step, the track position accessed by the heads 3-1, 3-2 moves one track toward the inner circumference. Also head 3-
1. With the movement of 3-2, N+1 is set to N in the track number memory. Then the flow is #V-5-
Branches into 2.

Therefore, when continuously erasing tracks, #V-5-2 to #V-1 are used until the stop switch 61 is turned on or until the innermost track is erased.
3 (7) 70- is repeated until the value of the buffer memory E becomes O, that is, until the erasure of the set number of tracks is completed.

Next, the flow after #V-15 for setting the continuous erase mode executed as described above will be explained.

#V-15; 10 shown in 63 to 72 in Figure 1
It is determined whether any of the key switches is turned on or not. If it is turned on, the flow proceeds to #V-16; if not, the flow proceeds to #V-15-1.

#V-16; In this step, the continuous track erase mode will be set. In other words, the number input using the 10 key switches 63 to 72 becomes the number of tracks on which continuous erasure is to be performed. In the erase track number buffer E, the numerical value of the turned on IO key is set in the 1's digit. Flow then proceeds to #V-17.

#V-17; 7 segment L in this step
The value of E is displayed on ED25. This situation will be explained with reference to FIG. 28. In #V-15, the value of the lO key switch turned on first is set to the 1 digit of E (#V-
16) and is displayed at the 1's digit of the LED 25 in this step, as shown in FIG. 25(a). Here, before reaching the display shown in FIG. 22(a), the track number is displayed on the display and is blinking.

Further, F set to E is displayed as "0". The value displayed on the display is 2Hz at $V-1.
Since the blinking operation continues to be repeated, the display "8I" shown in FIG. 25(a) will blink. Flow then proceeds to @V-17-1.

#V-17-1; At this point, wait until the 10 key switch is turned off. When turned off, the flow is @V-15
Proceed to -1.

#V-15-1; Here, it is determined whether the erase standby switch 77 is turned on. If it is turned on, the flow advances to #V-18, and if it is not turned on, the flow advances to #V-15-2.

That is, by turning on the erase standby switch 77, the erase standby state set in #V-1 is automatically canceled by turning on the switch 77 again and in the steps after #V-18. Therefore, there is no need to provide a dedicated release switch.

@V-15-2; : Soldering iron, switches 78 and 10
Determine whether any switch other than the key is turned on. If it is turned on, the flow branches to #V-18, and if it is not turned on, the flow branches to #v-4.

In other words, the erase standby state is automatically canceled by turning on any switch other than the IO key as well in steps #V-18 and subsequent steps. Therefore, there is no need to provide a dedicated release switch. Therefore, there is no need to go out of your way to provide a separate switch. Above (7)
#V-15-1. If you pass step #V-15-2 with No, you will have to repeat the steps described above from #v-4, but the 7-segment LED 25 has already been set to the 25th
The operation when executing the steps after #v-4 when "81" shown in the figure is displayed will be explained.

When the lO key switch is turned on in #V-15, the number input by the switch in #V-16 is set to the first place in the buffer memory E, and the number that was previously set in the first place is stored in the buffer memory E. The number set in the 10th place disappears.

For example, if the "5" key of the 10 key switches is turned on, #V-16. #V
-17, the display shown in FIG. 28(b) is displayed on the 7-segment LED 25. Of course, the value set in the buffer memory E in this case is 15.

Next, when a good value "2" is similarly input to the IO main key switch, the display shown in FIG. 25(c) is produced. In the above table, 1, 5.2 of the 10 key switches are turned ON in order in the erase standby state.

The display shown by the LED 25 in the case of Furthermore, the displayed numerical value matches the value set in E as it is. That is, when a value of "2" or more is set using the 10-key switch, this is equivalent to selection of the continuous erase mode, and the set value becomes the number of tracks on which continuous erase is performed. This situation can be seen in the flow description above if the value of buffer memory E is greater than 0 at #V-10, the flow is #V-1
If the track number N is smaller than 50, the track is UP Lte #V-5-21, m. Continuous erasure is performed by executing steps 6 and subsequent steps. In other words, at 5v-tt, if the stop switch 61 is not turned on, erasing will continue until the value of E becomes equal to 0 or until track 50, which is the innermost track, is erased. become.

Then after performing the steps described above run #
V-18 to #V-20 will be explained.

@V-18; 7 segment LED 25 at the knee
stops blinking and displays track number N on the display. The flow then reaches #V-19. In other words,
This step erase standby state is released.

#V-19; If the switch 77 is turned on, the process waits; if the switch 77 is turned off, the process proceeds to #■-20.

@V-20; At this point, the flow returns to the flow shown in 8 of FIG.

As explained above, when performing erasing, in this embodiment there are two modes: a mode in which erasing is performed only once, a mode in which it is performed continuously, and a mode in which erasing is performed after specifying the number of tracks to be erased consecutively in advance. However, for erasing when the number of erase tracks is not set using the 10-key switch, the value of E in #V-5-1 is set to "F" in advance.
F”, it moves to #v-6 without going through #V-5-2. Therefore, if the field flag is cleared in the erase standby state, it is set in frame mode. In other words, if the field flag is set, erasure of two tracks will be performed in field mode.In other words, if the field flag is set, erasure of two troughs will be performed. If the 2 tracks used for playback are played in field mode, 1 track of the playback track will be erased.However, the number of erased tracks is set by the 10 key switch. If "O" is set from the 10 key switch, erasure in field mode is always executed via #V-5-2.However, if "O" is set from the 10 key switch, Erasure is not executed because the branch branches to Of the two tracks constituting the frame image, only the outer track is erased by one track.

Therefore, it is possible to erase only the signal recorded on one of the two tracks constituting a frame image.

Furthermore, when performing continuous track erasing, it is generally assumed that new information such as a video signal is recorded on the erased track. When track erasure is completed, the head 3-1 is located on the last erased track, so when recording new information, the user operates the track UP switch 54 and track DOWN switch 55 to erase the information. It is necessary for the head 3-1 to access the track on which it started.

Therefore, the next step is to execute continuous track erasing, and when this is completed, the flow for realizing a function that is extremely effective in terms of operability is to have the head 3-1 automatically access the track where continuous erasing has started. is shown in FIG. The flow shown in FIG. 29 is similar to #V-18 shown in FIG.
#V-1977) This is a flow inserted between each step.

First, when subroutine V is executed, the track number N that is being accessed at that time in #v-1 is stored in memory N'. After the erasure is executed according to the flow described above and reaches #V-18, the flow shown in FIG. 29 is executed. That is, in #V-18-1, it is determined whether the number of the track that the head 3-1 is accessing at that time matches the number of the track stored in the memory N' in #V-1, and if they match. If not, #V-18-2. #V18-3 is executed, the head 3-1 is controlled to access one track on the outer periphery, N is set to N-1, and memory N is displayed on the 7-segment LED 25. Then the flow returns to #V-18-1 and head 3
The number of the track that −1 is accessing is memory N.
#V-18-2. until it matches the track number stored in '. #Repeat V-18-3, head 3
-1 accesses the track that started erasing #V1
The flow branches from 8-1 to #V-19, and the above-mentioned #V
-19 and subsequent steps are executed. Therefore the 29th
By executing the flow shown in the figure, the head 3-1 automatically accesses the track where erasing started when erasing is completed, so it is possible to omit the operation of manually searching for the position where erasing started at the time of next recording. I can do it.

Furthermore, when performing continuous erasing, the video to be erased is played back for a certain period of time, the operator is made to confirm this, and after determining whether or not the stop switch 61 is turned on, the erasing operation for that track is started. is extremely effective in preventing accidental erasure.

To realize this function, one track is UP in @V-13 of subroutine V shown in FIG.

Preferably, a step for a delay of about 1 second is provided in the step immediately after #v-6 after N+1 is executed until #v-7 is executed, and furthermore, during this delay, the stop switch 61 is Determine whether or not is turned on,
If it is not turned on, go to #v-7, if it is turned on, go to #V-
What is necessary is to provide a step that branches to 18.

By providing such a step, it is possible to confirm the video signal to be erased, so that if a video that is not desired to be erased is played back, continuous erasing can be interrupted by turning on the stop switch 61. Therefore, the probability of erroneous erasing is dramatically reduced.

In addition, when performing continuous erasing, in the above-mentioned embodiment, the flow branches from #V5-1 to #V5-2 in subroutine ①, and by executing #V5-2, all tracks are erased one track at a time in field mode. However, in order to shorten the execution time of continuous erasing, it is necessary to erase two tracks at least once during continuous track erasing by sending an erasing signal to two heads simultaneously in frame mode. is valid. An example in this case will be described below.

First, in FIG. 30, the flow shown in FIG. 30(a) is changed to #V-6 shown in FIG. This step is inserted between the step #V-7, and the flow shown in FIG. 30(b) is the step #V-11. This step is inserted between steps #V-r2. Next, the flow will be explained.

After subroutine (2) shown in FIG. 27 is executed up to #v-6, #V-6-1 is executed following #v-6. In this step, it is determined whether the number of erased track buffers E is 2 or more, that is, whether continuous tracks /i''r have been deleted.If it is 2 or more, the flow is #V-
Proceed to 6-2, otherwise proceed to #V-7. #
V-6-2i: Oite, E i, l: Set E-1 and clear the field flag. The flow is #v-
It reaches 7. Here, an erase signal is generated at #V-7 shown in FIG. 27. In this case, if the field flag is set, the
If the erase signal is supplied to the other head, that is, the head that is performing field playback, and the field flag is cleared, the erase signal will be supplied to both heads 3-1 and 3-2 at the same time. . After the erase is completed, #v-8 to #V-11 are executed as described above, and if the continuous erase operation is not completed, the flow reaches #V-11-1 from @V-11, and the field Determine whether the flag is set. If continuous track erasure is not set and the field flag is set, the flow advances to #V-12 and follows the flow described above.

Also, if continuous track erasure is set in #V-11-1 and the field flag is not set, as described above, two tracks have been erased in #V-7. The flow reaches V-11-2, N is set to +1, and the head 3-1°3-2 moves toward the inner circumferential side of the l track. After that the flow is #V
-13, and the head further moves toward the inner circumferential side of the l track according to the above-described flow.

By doing so, when performing continuous erasing, erasing is performed in frame mode until the number of remaining tracks for continuous erasing becomes 1, so that the execution speed of continuous erasing can be increased. However, in this case, if you want to check the video to be erased before executing the erase, following #v-6,
When the field flag is set, it is necessary to select heads 3-1 and 3-2 in Figure 1 for a certain period of time so that head 3-1 performs field reproduction and head 3-2 performs field reproduction. It is. Also #V
-2. #Skip step V-3 and switch to PB mode, R
In particular, by switching between the EC mode and the EC mode, it may be possible to select a mode in which the reproduced video to be erased during continuous erasure is confirmed and a mode in which the reproduced video is not confirmed. In other words, select a mode in which the images to be erased are not confirmed when performing continuous erasing, and repeat the flow shown in Fig. 30 (a) and (b) in the second mode.
When added to the flow shown in FIG. 7, the time for continuous erasing becomes the shortest, and this is an extremely effective means when erasing all tracks.

Next, subroutine (2) executed when the all-track erase standby switch 79 is turned on will be explained with reference to FIG.

#W-1: The 7-segment LED 25 flashes m, l yo:='' (ALL-ERASE) at 2 Hz, indicating that the all-track erase standby state is in effect.

#W-2: Determine whether or not the PB mode flag is set, and if it is not set and the flow branches to #W-4 if the flow goes to #W-3.

#W-3-1: Clear the PB mode flag to prohibit reproduction of the magnetic sheet 1.

#W-3-2: Detects that the switch 79 is turned off and proceeds to #W-4.

#W-4: Determine whether the erase switch 78 is on or not. If it is on, the flow branches to #W-9; if not, the flow branches to #W-5.

#W-5: All track erase standby switch 79
Determine whether or not is turned on. If it is on, #W-7
If it is not on, the flow branches to #W-6.

#W-6: Determine whether any switches other than switch 79 are turned on. If it is on, the flow branches to #W-7, and if it is not on, the flow branches to #W-4.

#W-7: Stop the blinking of LED25, and
5 to display N, that is, the track number accessed by the head 3-1.

#W-8: If the switch 79 is turned off at the same time, the process returns to ■.

$W-9: When the erase switch 78 is turned on in #W-4, the flow branches to this step. In this step, it is determined whether or not there is an erroneous erasure prevention claw (not shown). If there is, the flow branches to #W-10; if not, the flow branches to #W-7.

#W-10: Determine whether N is l'', that is, the track number being accessed by head 3-1 is “l”, and if it is “l”, transfer to $W-12 “ # if not l”
The flow branches to W-11.

#W-11: Heads 3-1, 3-2 are moved to the outer circumferential side by one track, 1 is further subtracted from N, and the flow returns to #W-10. Therefore #W-10. #W-11
By repeatedly executing , the flow branches to #W-12 only when the number of the track accessed by the head 3-1 reaches l.

#W-12: Flashing N on LED25 (5Hz)
let This allows the user to know which tracks have been erased when all tracks are erased.

#W-13: Field flag is cleared and frame mode is set. Therefore head 3-1.3-2
The track is erased using both.

#W-14: Ko (7) Both 2 steps are #V-7. #
Same as V-81W-15.

#W-16: Since both heads 3-1 and 3-2 are used and two tracks are erased without moving the head, in this step the head is moved two tracks to the outer circumferential side and further N is erased. Add 2 to .

#W-17: Determine whether or not N is 50. If N is 50, the flow branches to #W-7; if not, the flow branches to #W-12, and erasing of all tracks is completed. Until #W-
Steps 12 to #W-17 are repeated.

As explained above, in the all track erase mode which is executed by turning on the erase switch after turning on the all track erase standby switch, clear the PB mode flag before erasing and check the video to be erased. In addition, the magnetic head 3-1. Since erasing is performed two tracks at a time using both methods 3-2, the time required to erase all tracks is extremely short compared to the method of erasing one track at a time. Furthermore, when erasing all tracks, the head is moved to the end of the track (in this example, the outermost circumference) and then all the tracks are sequentially erased toward the opposite end. When attempting to erase all tracks, no matter which position the head 3-1 is accessing, all tracks can be surely erased.

Further, during erasing, the number of the track being accessed by the head 3-1 is displayed on the LED 25, so that the user can recognize how much erasing is being performed.

In the embodiments described above, the magnetic sheet 1 is used as the recording medium, but an optical recording medium may be used. A magneto-optical recording medium or other recording medium may also be used. As the recording means, means depending on the recording medium may be used, for example, in the case of an optical disc, an optical head may be used.

In this embodiment, step $A-20 shown in FIG. 6 detects the state of the erase standby switch 77 as the first detection means for detecting the first erase command input, and the first erase command input is detected as the step $A-20 shown in FIG. In the detected state, the erase switch 7 is activated in the subroutine ■ called from #A-20 as a second detection means for detecting the input of the second erase command.
The step #v-4 detects the state of No. 8, and the erasing means for erasing the information recorded on the recording medium based on the detection result of the second detection means generates an erasing signal in the subroutine #v-. There are 7 steps.

Furthermore, the first subroutine (2) called when the erase standby switch 77 is turned on serves as a reproducing means for reproducing the information to be erased by the erasing means in response to the detection of the first erase command input by the first detecting means. In the process,
When the PB mode flag is not set, subroutine O is called to set the PB mode flag (that is, sw2.sw3 shown in FIG. 1 is operated to operate at least one of the heads 3-1 and 3-2. Connect with playback amplifier 6) #V-2. #V-3.

Further, in this embodiment, the first detection means and the second detection means are means for detecting the states of separate switches, but instead of providing the erase switch 78, the first detection means and the second detection means are used as means for detecting the states of separate switches. Erase standby switch 77
Erase standby switch 7 as a means of detecting the state of
7 may be pressed twice, for example, to execute erasing.

Furthermore, according to this embodiment, as described above, the user can confirm the information to be erased by setting the playback state before executing the erase. Furthermore, in this embodiment, if you check the information to be erased and do not want to erase it, the erase standby switch 77 or the erase switch 78 is activated.
It is possible to cancel without erasing by turning on the other switches.

<Effects of the Invention> As explained above, according to the present invention, erasing is performed for the first time in a two-step operation, which not only prevents erroneous erasing of information recorded on a recording medium, but also eliminates the possibility of accidentally erasing information recorded on a recording medium. Since the information to be deleted is played back in response to the input of the deletion command, the user can confirm the information to be deleted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing combinations of switching states of SW2 to SW5 shown in FIG. 1, and FIG. 3 is a front view of the device of this embodiment. 4 are front views of the remote control device used with the device, FIGS. 5 to 20, 23, and 25.
Figures 27 to 27 and 29 to 31 are C shown in Figure 1.
Flowchart of PU40, Fig. 21, Fig. 22, Fig. 2
Figure 4 is a diagram for explaining the ID signal displayed on the monitor, Figure 28 is a diagram for explaining the flow of Figure 27,
FIG. 32 is a diagram for explaining signals generated from the erase signal generator 85 shown in FIG. 1. 1-m-Magnetic sheet 3-1.3-2---Head 40--1 CPU

Claims (1)

[Scope of Claims] A first detection means for detecting a first erasure command input; and a second detection means for detecting a second erasure command input in a state in which the first detection means detects the first erasure command input. 2 detection means;
Erasing means for erasing information recorded on a recording medium based on the detection result of the second detecting means; and erasing means for erasing information recorded on the recording medium in response to detection of a first erasing command input by the first detecting means. 1. An erasing device comprising: a reproducing means for reproducing information that is deleted.