JPS62232705A - Erasing device - Google Patents

Abstract

PURPOSE:To interrupt an erasing operation, by providing a control means which removes a state where the first erase command is inputted corresponding to a command other than the second erase command input. CONSTITUTION:At the turning on time of an erase standby switch 78 in the state where the turning on of an erase standby switch 77 is detected, an erasing signal is impressed for the first time, on head 3-1, and 3-2, and the erase of a bit of recording information on a recording medium is performed. At such a time, when switches other than the switches 77 and 78 are truned on, in the first state where the turning on of the switch 77 is detected, the first state is automatically removed. In this way, the erasing operation can be interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention particularly relates to an erasing device for erasing information recorded on a recording medium.

<Prior Art> Conventionally, recording/reproducing apparatuses have been considered in which a recording/reproducing head is provided separately from an erasing head, or a recording/reproducing head is provided in combination with an erasing head. Conventionally, in such a device, when performing an erasing operation, the recording/reproducing head is moved to the track to be erased on the recording medium, and regardless of whether the operating mode at that time is the recording mode or the reproduction mode, By pressing the erase button, the erase operation was performed immediately.

<Problems to be Solved by the Invention> However, since the above-mentioned device performs the erasing operation with only one erasing command, there is a problem that there is a high possibility of erasing another track by mistake. there were.

The present invention aims to solve such problems.

Means for Solving the Problems> In order to achieve the above-mentioned object, the present invention provides a method in which when a second erasure command input is obtained in a first state where the first erasure command input is obtained. The erasing device erases information recorded on a recording medium, and is characterized by comprising a control means for canceling the first state in response to a command other than inputting the second erasure command.

Effect> In the above configuration, in the first state where the first erasure command input is obtained, erasure is performed for the first time when the second erasure command input is obtained, and the second erasure command input is obtained in the first state. When a command other than the erase command input is input, the first state is automatically canceled, and even if a second erase command input is obtained after such cancellation, no erase is performed.

<Example> The present invention will be described in detail below with reference to the drawings. In the example of the present invention described below, a still image video signal is recorded on a disk-shaped recording medium, specifically, a disk-shaped magnetic sheet. A recording and reproducing apparatus that records or reproduces a recorded still image video signal will be described.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, l is a magnetic sheet on which the recording/reproducing track of the video signal, the track pitch, and the track position are determined in advance. In the case of a frame video signal, one field of video signal is recorded on each of two adjacent tracks to form a frame video signal. The magnetic sheet 1 is placed in a jacket 1 (not shown) in advance, and the jacket is provided with a claw to prevent accidental erasure, and by breaking the claw in advance, the erasing operation is prohibited in the same way as an audio cassette. be done.

2 is a DC motor for rotating the magnetic sheet 1 at a constant speed;
3-1.3-2 has an inline type head house that accesses two adjacent tracks, 3-1 is on the outer circumferential side, 3-2
accesses the inner circumferential side. 4 is a magnetic head 3-1.3-
2 is a magnetic head moving mechanism that moves the magnetic head 3-1 to access the track formed on the magnetic sheet 1; 5 is a magnetic head moving mechanism that moves the magnetic head 3-1 to access the innermost track on the magnetic sheet 1; The state switches from off to on, and the microcomputer (hereinafter C
(referred to as PU) 40 is an innermost detection switch that outputs an L level signal, 6 is a reproducing amplifier for amplifying the signal detected by the magnetic head 3-1.3-2, and 7 is a signal from the reproducing amplifier 6. a level detector that detects the average value of the output signal;
8 is a comparator that detects whether the output of the level detector 7 is higher than a threshold value set by a reference voltage source (not shown); 9 is a demodulation circuit that demodulates the output signal of the reproduction amplifier 6; 1;
0 is 1/2 horizontal scanning period (hereinafter referred to as 1/2 H)
an l/2H delay circuit that delays the output of the demodulation circuit 9 by
11 is a horizontal synchronizing signal Hsync from the output of the demodulation circuit 9;
A synchronization signal separation circuit 12 separates a synchronization signal such as a vertical synchronization signal Vsync, and a synchronization signal separation circuit 12 detects a predetermined data signal from the output of the reproduction amplifier 6 in accordance with the timing of the synchronization signal separated from the synchronization signal separation circuit 11. This is a data demodulator that demodulates data signals. The data signal is a signal for determining what kind of information is recorded on the track, for example, whether it is a field video signal or a frame video signal, and a date set by the user. signal, freely set by the user! ! The signal indicates a digit number and is recorded in a frequency band lower than that of the video signal at a position having a predetermined relationship with the portion of the track where the synchronization signal is recorded. The reason why the demodulation circuit 9 and the data demodulation circuit 12 are provided separately here is as follows. That is, the video signal recorded on the magnetic sheet l is FM
However, data signals other than video signals use the DPSK modulation method (Derferatia), which is different from FM modulation.
1Phase 5hft Keying) is adopted. Therefore, the demodulation circuit 9 described above is an FM demodulation circuit, and the data demodulation circuit 12 is a DPSK demodulation circuit.

C3 is a monitor that allows you to reproduce and observe video signals! 3' is a printer connected to print the video signal. Nao printer! 3' is the signal of the start signal input terminal! (Operation starts when the level is reached, and the busy signal output terminal is set to L level during operation. 14 is a modulator that performs DI'SK modulation on data output from CI"U3O, which will be described later. H s yn and V s are separated by the synchronization signal separation circuit 17 from the video signal input from the video input terminal 18.
The modulated data is output to the recording amplifier 16 at a timing corresponding to y n c.

15 is F for the video signal input from the video signal input terminal 18.
This is a recording amplifier that performs processing necessary for recording such as M modulation and outputs it to the recording amplifier 16. Reference numeral 19 denotes a reference signal generator, which generates accurate reference pulses (60 Hz) for rotating the magnetic sheet 1 and an alternating signal for erasing.

Reference numeral 20 denotes a magnetic piece provided on the above-mentioned magnetic sheet l, and as will be described later, the signal from the magnetic piece 20 is used to synchronize with the base C1 C generated by the reference signal generator 19. Rotation control of the DC motor 2 is performed. 21 is an I'G coil for detecting a signal from the magnetic piece 20 when the magnetic sheet 1 is rotated by the DC motor 2.

22 is a waveform shaping circuit that shapes the waveform of the signal output from the G coil 21, and the output of the waveform shaping circuit 22 is input to a CPU 40 and a motor control circuit 23, which will be described later.

Reference numeral 23 denotes a control circuit for controlling the rotation of the DC motor 2, which receives the output signal from the synchronization signal separation circuit 17 or the reference signal generator 19, and the waveform shaping circuit 2.
I) Rotate the C motor 2 so that the output of the motor 2, that is, the phase relationship with the signal from the magnetic piece provided on the magnetic sheet i is in a predetermined relationship, for example, the phase of both is always shifted by 7H. Control. Here, when a recording operation is performed by the magnetic head 3-1.3-2, SWl is the synchronization signal separation circuit 17.
The rotation of the DC motor 2 is controlled based on Vsync and the signal input from the waveform shaping circuit 22, that is, the signal from the magnetic piece 20 provided on the magnetic sheet l, and the rotation of the DC motor 2 is controlled in advance. When the reproducing operation is performed according to 3-1.3-2, SWI is the reference signal generation Zs.
+9 side, and the DC motor is activated based on the reference signal from the reference signal generator 19 and the signal input from the waveform shaping circuit 22, that is, the signal from the magnetic piece 20 provided on the magnetic sheet l. The rotation of 2 is controlled.

23' is a driver that drives a step motor 24 for controlling the position of the head 3-1, 3-2 based on a signal from CI''U3O, which will be described later. Head 3-1.3
-Move 2.

25' is a display circuit driven by a signal from the CPU 40, and as a display element, as shown in FIG. .2-digit 7-segment display element that displays the feed speed of 3-2, PB and LED that display the playback mode, RFC and LED that display the record mode FRA that displays the frame mode
M E, L E D Display field mode F
It consists of IELD and LED.

26 is R where the program of CI' U 40 is stored.
OM.

27 is R where the data of the CPU 40 is temporarily stored.
It is AM. 28 is a timer driven by the CI'U 40, and 29 is a crystal oscillator that generates a reference clock for the CPU 40. Note that 80 is a detection circuit connected to photocouplers 81 and 82 that constitute a detection switch for detecting whether or not the magnetic sheet 1 is inserted.

83.84 and SW6 are data signals (hereinafter referred to as 1.
83 is a circuit for displaying a video signal (referred to as ``V'') on the monitor 13 and printer 13-.
This is a synchronous separation circuit that separates sync and Hsync, and has the same configuration as the synchronous separation circuit shown as 17. 84 is V separated by the synchronous separation circuit 83.
This is a character generator for generating characters corresponding to data signals in synchronization with SYNC and HSYNC. monitor! 3 and the printer 13-, when the ID signal is superimposed on the video signal and displayed, a control signal is given from the CPU 40, SW6 is turned on, and the synchronization signal and data signal are sent to the adder shown as ■ in Fig. 1. Added and monitor! 3 or at a specific location on the printer 13'. The details will be described later.

85 is a magnetic sheet! This is an erasing signal generator for erasing the signal on any track of the . Note that the AC signal for erasing is provided from the reference signal generator 19.

Here, the erasure signal generator 85 has a constant amplitude period T1 as shown in FIG.
2 generates an attenuated signal formed by the recording amplifier! Connected to 6.

SWI is a switch whose state is changed by a signal from the control circuit 30 that is driven based on a signal from CI) U 40, and a video signal is input from the video signal input terminal 18, and the synchronization signal separation circuit! 7 to II s y
n c is output, and CI)
When a signal indicating the recording mode is input from U, the synchronization signal separation circuit 17 and the motor control circuit 23 are connected, and the synchronization signal separation circuit 17 does not output II sy n c or CF'U40 The reference signal generator 19 and the motor control circuit 23 are connected when a signal indicative of the reproduction mode is inputted from the controller or when the erase mode is selected.

SW2 is a switch whose state changes based on a signal from the CPU 40, and is connected to the state in which the head 3-1 is connected to the recording amplifier 16, the state in which it is connected to the reproduction amplifier 6, and the state in which the head 3-1 is connected to the recording amplifier I6 or the reproduction amplifier 6. Switch between an intermediate state in which no connections are made.

Like SW2, SW3 is a switch whose state changes based on a signal from the CPU 40, and there are two states: connecting the head 3-2 to the recording amplifier 16, connecting the head 3-2 to the reproducing amplifier 6, and connecting the head 3-2 to the recording amplifier 16 and the reproducing amplifier. 6 and an intermediate state in which it is not connected to any of

When reproducing a video signal from the magnetic sheet 1, SW4 is switched to the upper position in FIG. When the head 3-1 is connected and a field video signal is reproduced using only the head 3-1, the demodulation circuit 9 is switched to the upper side and the lower side in FIG.
The state where the CPU is connected to the CPU and the state where it is connected to the 1/2H delay circuit are alternately switched for each field.
This is a switch driven by 40.

SW5 is the video signal input terminal for the monitor 13 when recording! 8
This is a switch driven by the CPU 40 to connect the monitor 13 to SW4 during playback.

By the way, magnetic sheets! As mentioned above, the video signal recorded on or reproduced from the sheet I may be a field video signal consisting of only one field, or a frame video signal consisting of two fields in a pair. SW2 in SW3. Switching of the states of SW4 and SW5 will be explained using FIG. 2.

Figure 2 shows SW2. SW3. SW4. It is a figure which shows the combination of the switching state of SW5.

During field playback, SW2 connects the head 3-1 to the playback amplifier 6, and switches SW3 to an intermediate state, that is, head 3-1.
-2 is not connected to either the playback amplifier 6 or the recording amplifier +6, and SW4 is set to return in the odd field: J! A signal is output directly from the J circuit 9 to the monitor 1: the heron, and in the even field it is sent to the monitor 13 via the 1/2H delay circuit 10.
The output signal is alternately switched for each field to prevent skew distortion from occurring.

Next, in frame reproduction, SW2 connects the head 3-1 to the reproduction amplifier 6 in odd fields, and is in an intermediate state in even fields, SW3 is in an intermediate state in odd fields, and connects the head 3-2 to the reproduction amplifier 6 in even fields. Connect to. Therefore, during frame reproduction, signals from either head 3-1 or 3-2 are alternately output to the reproduction amplifier 6 for each field.

In this case, SW4 is switched to the upper side of FIG. 1, and the signal from demodulation circuit 9 is directly output to monitor I3.

In any of the above-described field reproduction and frame reproduction states, SW5 is driven so that the monitor 13 is connected to SW4.

Next, in field recording, SW2 connects the head 3-1 to the recording apparatus 16, and SW3 is in an intermediate state.

Therefore, during field recording, recording is performed by the head 3-1.

In frame recording, SW2 connects the head 3-1 to the recording amplifier 16 in odd fields and is in an intermediate state in even fields; SW3 is in an intermediate state in odd fields, and connects the head 3-2 to the recording amplifier 16 in even fields. Connecting. In frame recording, the combination of heads 3-1 and 3-2 can also be reversed.

Further, in both field recording and frame recording, during recording, the SW 5 is switched so that the monitor 13 is connected to the video signal input terminal 18 so that the video signal to be recorded can be observed on the monitor 13. In addition, if this occurs, SW
4 may be in any state.

Next, the erase mode will be explained. In the erase standby state, which will be described later, SWl is on the reference signal generator side;
5 is connected to the upper side in FIG. 1, and is in the same state as the playback mode. At this time, field erase, for example, erases only the track being played by the magnetic head 3-1. A case will be described.In this case, at the same time as erasing starts, a control signal is sent from the CPU 40 so that SW2 is on the recording amplifier side and SW3 is in an intermediate state.
Furthermore, an erase signal trigger pulse is sent from the CPU 4Q to the erase signal generator 85, so that the erase signal is sent only to the head 3-■.

Next, a description will be given of frame erasing in which tracks being accessed by heads 3-1 and 3-2 are simultaneously erased. When erasing a frame, an erasing signal is sent to the heads 3-1 and 3-2 at the same time, so the CPU 40 sends a control signal so that SW2 and SW3 are both on the recording amplifier side. and cp
A trigger pulse from u40 generates an erase signal, which flows to both heads via the recording amplifier.

Furthermore, in this embodiment, when field erasing is performed, the erasure is performed by head 3-1, but when field erasing is performed using head 3-2, SW2 is in the intermediate state, and SW2 is in the intermediate state.
It is only necessary to control W3 so that it is on the recording amplifier side.

Next, the switches 51 to 78 shown in FIG. 1 will be explained.

In giving this explanation, the external appearance of the apparatus of this embodiment shown in FIGS. 3 and 4 will also be explained.

FIG. 3 is a front view of the apparatus of this embodiment, and FIG. 4 is a front view of a remote control device used in the apparatus of this embodiment.

Switches 51 to 79 and 72 shown in FIG. 1 are switches 1 and 1I provided in the device shown in FIG.
The switches are divided into the group of switches provided in the remote control device shown in g, the device shown in FIG. 3, and the group of switches provided in the remote control device shown in FIG. 4, but they all have the same functions. The same reference numerals are used in FIGS. 1 to 4 to refer to switches having the same structure.

Note that the switches provided in the device shown in FIG. 3, and in FIG. 1, the switches provided only in the remote control device shown in FIG. 4, are connected to the CPU 40 via a line. For convenience, the signals generated by operating the switch provided only in the remote control device shown in FIG.
: is converted into infrared light and input to the CPU 40 of the device shown in FIG. 3 via the remote control light receiving section 45 provided in the device.

It should be noted that the method of arranging the switches 51 to 79 can be considered in various other variations of this embodiment, and is not limited to this embodiment.

In FIGS. 1 to 4, 41 is a power switch, 42
1 is a slot for inserting the magnetic sheet 1; when the inject button 43 is turned on while the magnetic sheet 1 is inserted into the slot 1I2, the slot 1I2 is automatically opened and the magnetic sheet 1 is injected. 43 is the above-mentioned inject button, 44A and 44B are the above-mentioned I) port, and LEDSR, respectively.
EC, LED, 45 is a remote control light receiving part that receives a signal from the remote control device shown in FIG. 4, 46 is an interval mode display LED that lights up when interval playback is executed, 48 is field playback or recording, frame playback To display whether recording or recording is set, press L! ζD125 is the aforementioned two-digit 7-segment t, E D .

50Δ, 5013, and 50C are LEDs that display the operating states of a program playback setting switch 58, an interval time setting switch 57, and a program track setting switch 62, which will be described later, respectively.

51 is an RFC mode switch for setting the recording mode and checking whether the track accessed by the head in the recording mode is recorded or unrecorded; when this switch is turned on, the track accessed by the head is (If the track being accessed by heads 3 to 1 has already been recorded during field recording, or the track being accessed by heads 3-1 or 3-2 during frame recording) has been recorded), REC,
The LED flashes to indicate that the track that the head is accessing is unrecordable, and if the track that the head is accessing is not recorded, or if the control circuit 30 determines that no video signal is input, the REC and LED lights. Lights up to indicate that recording is possible.

52 is a REC that determines the timing to perform the recording operation.
This is a case where the recording mode is set by the RIEC mode setting switch 51, and when the switch 51 is turned on, recording is performed on the magnetic sheet l.
, and a track feed speed setting switch 56, which will be further described later.
Continuous recording is performed while the head 3-1.3-2 is automatically shifted during the period when the switch 51 is on in 145 j17 where continuous recording is set in advance.

53 is a 1) [3 mode setting switch for setting the playback mode, and when the switch 53 is turned on, P B , L E I ) indicating the playback mode are lit.

54 is a track Ul) switch;
By operating the driver 23', the step motor 24 is rotated, and the head moving mechanism 4 moves the heads 3-1, 3-2, thereby moving the heads 3-1. :Shift 1-2 to change the track accessed by the head toward the inner circumference. Further, when recording is performed in frames using a field/frame setting switch 59, which will be described later, the recording progresses two tracks at a time. When playback is set, when the track UP switch 54 is turned on, the heads 3-1, 3-2 are shifted two tracks at a time.
Also available in 7 segment LED25! Instead of the track number shifted by one track, the l track number shifted by two tracks is displayed, and when field recording or playback is set, when the track UP switch 54 is turned on, the head 3-1. 3-2 is shifted toward the inner circumferential direction one track at a time, and the 7-segment LED2
Even on 5! The shift number shifted for each track is displayed.

In addition, when the recording mode is set and the track UP switch 54 is operated, the head 3-1°3-2
REC if the track accessed by the head 3-1.3-2 has already been recorded when the head 3-1.3-2 is shifted.

RED44B performs a blinking display. 55 is a track DOW switch which is opposite to the track UP switch 54 and is used to change the access of the heads 3-1, 3-2 toward the outer circumference.
It is an N switch.

When the switch 55 is also set to frame recording in the same way as the track UP switch 54, when the switch 55 is operated and the tracks on the outer circumference of track 1 and the track on the outer circumference of track 2 are being subjected to frame recording, The track number shifted by 2 tracks is displayed on the 7-segment LED 25 (not the track number shifted by 2 tracks), and when field recording or playback is set and the switch 55 is operated! The track numbers shifted track by track are displayed.

Also, in the case where the recording mode has been set in advance as described above with respect to the track UP switch 54, and when the head 3-1.3-2 is shifted by operating the track DOWN switch 55, I if the track is already recorded? E.C.

The LED 44B performs a blinking display.

56, when recording and reproducing, it automatically switches whether to perform such operations continuously or sporadically while shifting the head, and also determines how many times per second the operations are performed when performing them continuously. This is a track feed respeed setting switch for setting the track feed speed shown.

When the switch 56 is pressed once and turned on, the track feed speed is displayed instead of the track number on the 7-segment 1-LED 25, and in this state, the first
If the track feed speed setting switch 56 is turned on again within the predetermined time clock determined by the timer 28 shown in the figure,
7 segment LED each time the switch 56 is turned on
25 indicates, for example, "2" indicating continuous recording or playback of two screens per second, "5" indicating continuous recording or playback of five screens per second, continuous recording or playback of 10 screens per second, etc. "1B" indicating that playback is to be performed, and "8" indicating that recording or playback is to be performed one-off, are cyclically displayed. Also, by turning on and then turning off the switch 56, the track feed speed is displayed instead of the track number on the 7-segment LED 25, and the timer 28 is displayed without turning on the switch 56 again.
When the measurement of the predetermined time by
25 returns from the state where the track feed speed is displayed to the state where the normal track number is displayed for one summer.

Furthermore, when the track feed speed is changed by the switch 56, if frame video recording is set in advance by the field/frame setting switch 59 and the RFC mode setting switch 51, continuous recording of 10 screens per second is not set. .

57 is an interval time setting switch. That is, the interval time setting switch is used to set the interval time for track forwarding when continuous playback is performed but the playback interval time is relatively long, or when program playback is set by the program track setting switch 58 described later. and
An interval time is set using the IO key switches 63 to 72 within 10 seconds after the switch is turned on.

Incidentally, when any switch other than the 10 key switches 62 to 72 is turned on after the interval time setting switch 57 is turned on, the interval time setting is automatically canceled. Reference numeral 58 denotes a program playback setting switch for setting a program playback mode in which the order of playback tracks is programmed in advance and the playback operation is performed continuously at the interval time interval set by the interval time setting switch 57.

To specify the order of playback tracks, first turn on the switch 58 to set the program playback mode, then operate the track UP switch 54 and track DOWN switch 55 to select the head 3-! .

3-2, change the track being accessed, play the video of the desired track, check it on the monitor 13, and turn on the program track setting switch 62, which will be described later, to check the number of the track you are checking on the monitor 13. This is done by memorizing it. Reference numeral 59 denotes the aforementioned field/frame setting switch, and each time the switch is turned on, the field recording or reproduction mode and the frame recording or reproduction mode are alternately switched.

Note that if the continuous recording mode of 10 screens per second is set in advance by the REC mode setting switch 51 and the track feed speed setting switch 56, and the frame recording is selected by the field/frame setting switch 59, the track feed will start. The speed is automatically changed to continuous recording mode of 5 screens per second.

That is, compared to field recording, during frame recording the head 3-1.3-2 must be shifted two tracks at a time, so when recording 10 screens per second, 20 tracks per second are required. In other words, taking into consideration the time to record the video signal, the head must be shifted for two tracks in 4/60 seconds, but such a high-speed head shift would be cumbersome, so this implementation was carried out. In the example, continuous recording of frames for 10 screens per second is prohibited.

Reference numeral 60 is a start switch for performing continuous interval playback or program playback. When the start switch is turned on, if interval playback is set, the recorded tracks will be played back sequentially starting from the first track during the interval time. Interval playback G play is started according to the interval time set by the setting switch 57 and the ten key switches 63 to 72, and when program playback is set, program playback is started. 6 Summer is a stop switch that stops the playback operation started by the start switch 60, and when the switch 61 is turned on during program playback, it stops the playback of the program while continuing to play the track that is being played at that time. .

62 is the aforementioned program track setting switch.

Reference numeral 73 is a switch for starting ID setting in the recording mode and for switching whether or not to display the ID contents in the playback mode. That is, turning on the switch 73 in the recording mode 1 thus enters the ID setting mode, and turning on the switch 73 in the playback mode allows switching between displaying or not displaying the ID contents. I can do it. 74,75
．． Reference numerals 76 denote a switch that is turned on when setting the year as the ID when the ID setting mode is entered by the switch 73, a switch that is turned on when setting the month, and a switch that is turned on when setting the day. In FIG. 1, the switches 74, 75, 76 and the aforementioned switches 57, 58, 62 are shown as independent switches, respectively, for convenience, but in this embodiment, the switches 74, 75, 76 and the switches 57, 58, 62 are shown as independent switches, respectively, as shown in the remote control device of FIG. 75 and 76 are also used as switches 58 and 57 and 62, respectively. In other words, the switch 57 is used to set the program using the interval time setting switch 58, and the switch 62 is used to set the program track independently of the TD setting for January 9, 2018, so in this embodiment, the switch is also used. This reduces the number of switch members and improves operability and reliability.

In addition, various other combinations can be considered when the switch is also used.

77 is an erase standby switch for temporarily putting the device into an erase standby state when erasing information recorded on the magnetic sheet 1; 78 is an erase standby switch for executing the erase operation in the erase standby state set by the erase standby switch 77; This is the erase switch. Reference numeral 79 is an all-track erase standby switch that sets a mode for erasing all tracks.

When erasing the information recorded on the sheet I, the switch 77 is first turned on to set an erasing standby state. In such a state, the reproduction mode is automatically set, so that the video recorded on the track to be erased can be confirmed on the monitor 13 or on the printer 13' before erasing is executed.

In addition, by operating the 10 key switches 63 to 72 in the standby state, the number of tracks to be successively erased can be designated. Next, by turning on the erase switch 78, at least one of the heads 3-1 and 3-2 is connected to the recording amplifier 16, and the information recorded on the track is erased by the erase signal shown in FIG. 32 generated from the erase signal generator 85. will be deleted. Further, by turning on the all-track erase standby switch 79 and then turning on the erase switch 78, all tracks are automatically erased.

Next, the operation of the embodiment of the present invention will be explained using flowcharts shown in FIGS. 5 to 20, 23, and 25 to 27.

First, when the power switch 41 shown in FIG. 3 is pushed in, the power of the device shown in FIG. 1 is turned on, power is supplied to each part of the circuit, and operation is started.

#l: Then, in FIG. 5, the register S described later becomes “0”.
", the PB mode flag is set, the track feed speed is initially set to 2 screens per second, and the interval time is set to 3 seconds. Therefore, when the power is turned on, continuous playback mode is automatically set in advance. Ru.

#2: Detect whether a jacket having a magnetic sheet 1 is pushed in or not. When the jacket is pushed in, the flow branches to #3, and when it is not pushed in, the flow skips #3 and branches to #4.

#3: When the jacket having the magnetic sheet 1 is being pushed in in #2, the DC motor 3 is driven.

#4: Detect whether the head 3-1 is accessing the 501-rack by detecting whether the switch 5 shown in FIG. When the head 3-1 is not accessing the 50th track, the flow branches to #5, and the step motor 24 shown in FIG. 1 is driven. Then, the loop of #4 and #5 is repeated so that the head 3-1 accesses the 50th track.

#6: When the head 3-11 accesses the 50th track, the flow reaches this step, and in this step, the register N for accessing the memory (RAM 27) is set to 50.

#7: In this step, it is detected whether the DC motor 2 is being driven. When the jacket having the aforementioned magnetic sheet 1 is inserted, the DC motor 2 is being driven by executing #3, so the flow advances to step #8 and the field flag is set. When the jacket is not inserted, the flow proceeds without passing through #3, so the DC motor 2 is not driven. Therefore, the flow returns to #2 to detect whether a jacket is inserted or not.

#8: When the DC motor 4 is being driven in #7, a field flag is set. Therefore, the LED 44A indicating the field mode shown in FIG. 3 lights up, and a display indicating the field mode is performed. That is, in this embodiment, when the power is turned on and the jacket is inserted, the field mode is automatically set.

#9: Detect the output of the level detection circuit 7 shown in FIG. 1 to determine whether the track being accessed by the head 3-1 is a recorded track or not.

Here, since the track that the head 3-1 is accessing has already been recorded, when the output of the level detection circuit 7 becomes H level, the flow advances to #lO, and the output of the level detection circuit 7 becomes L level. If so, the flow advances to #16.

Here, #16 will be explained first.

#16: Set “0000” to address N in memory. Here, "oooo" indicates that the track corresponding to the memory address is unrecorded.

Next, the flow from #IO onwards will be explained.

#10: In #9, when the output of the level detection circuit 7 is at H level, reproduces the signal recorded on the track,
The ID signal is taken in from the data demodulator 12.

#ll: Detects the content of the ID signal to determine whether the video signal recorded on the track is a field video signal or a frame video signal. If it is a field video signal, the flow advances to #15, and if it is a frame video signal, the flow advances to #12.

#12: In this step, it is determined whether the video signal of the track that the head 3-1 is accessing is an inside track or an outside track of the frame video signal. If it is the inside track, the flow advances to #14. If it is an outside track, the flow advances to #13.

#13: If the video signal of the track that the head 3-1 is accessing is a track outside the frame video signal, set the memory address N to "0011". Note #l
When proceeding to this step for the first time, N is set to 50 in #6.

#14: In the case of a frame video transmission video inner track, set the memory address N to "001O".

#17: When the head 3-1 is shifted to the first track and it is detected that N=1, the flow is #2.
If N=1, the flow advances to #18.

#18: When it is detected in #17 that N=1 is not true, the head 3-1 is shifted by one track toward the outer circumferential side.

#I9: When the head 3-1 is shifted toward the outer circumferential side in #18, it is subtracted from N to obtain N.

#20: When N=1 is detected in #17, that is, when the head 3-1 accesses the first track provided on the outermost circumference and the presence or absence of recording is set in the memory, the memory is set here. If you read the data at address N, that is, the first address of the memory, and it is "0011", specifically, if the first track is the outer track of the two tracks that make up the frame video signal, it will flow to #21. If not, the flow advances to #23.

#21: If it is detected in #20 that the first track is a track outside the tracks constituting the frame video signal, the flow advances to this step. In this step, if the data at the N+1 address of the memory, that is, the second address of the memory, is read and it is "0010", specifically, if the second track is the inner track of the two tracks constituting the frame video signal. for#
Proceed to 22.

#22: When frame video signals are recorded on two tracks, the first track and the second track, the flow moves to this step. Therefore, the field flag set in #8 is cleared and the field mode is changed to frame mode. Therefore, the field frame display LED 48 shown in FIG. 3 lights up to indicate the frame mode.

#23. #24: The register N indicating the address of the memory mentioned above is connected to the 2-digit 7-segment LED shown in Figures 1 and 3.
25.

This display allows the user to recognize the track number that the head 3-1 is accessing.

When this flow ends, the process jumps to the next flow shown in A. The flowchart shown in FIG. 6 will be explained below.

#A-1: Detects whether the REC mode setting switch 51 is turned on, and when the switch 51 is turned on, the flow calls subroutine ■ to set the recording mode, and when it is not turned on, the flow calls #A-1. Proceed to A-2.

#A-2: It is detected whether the REC switch 57 is turned on, and when the switch 52 is turned on, subroutine (2) is called, and when it is not turned on, the process proceeds to #A-3.

#Δ-3: Detect whether the PB mode setting switch 53 is turned on, and when the switch 53 is turned on, subroutine O is called, and when it is not turned on, the process proceeds to #A-4.

#A-4:) When the rack UP switch 54 is turned on, the flow calls subroutine O, and when it is not turned on, the flow advances to #A-5.

#A-5 When the Nidorak DOWN switch 55 is turned on, the flow calls subroutine (2), and when it is not turned on, the flow advances to #A-6.

#A-6: When the track feed speed setting switch 56 is turned on, the flow calls subroutine [F], and when it is not turned on, the flow advances to #A-7.

#A-7: When the interval time setting switch 57 is turned on, the subroutine ◎ is called, and when it is not turned on, the process proceeds to #A-8.

#A-8 When the nib program setting switch 58 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-9.

#A-9 When the nib program track setting switch 62 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-10.

#A-10: When the field frame setting switch 59 is turned on, subroutine (2) is called; when it is not turned on, the process proceeds to #A-11.

#A-11 When the start switch 60 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-12.

#A-12 When the stop switch 61 is not turned on, the subroutine [phase] is called, and when it is not turned on, the process advances to #A-13.

#A-13: When the jacket detection switch (corresponding to the detection circuit 80 in Fig. 1) is turned on, jump to subroutine ■, and when it is not turned on, jump to #A-14.
Proceed to.

#A-14 Clear the Niprogram playback mode flag and the program playback execution flag.

#A-15: When any of the 10 key switches 63 to 72 is turned on, subroutine (2) is called, and when it is turned on, the process proceeds to #A-16.

#A-16: When the ID switch 73 is on, call the subroutine ◎, and when it is on, call the subroutine ◎.
Proceed to A-17.

#A-17: When the year setting switch 74 is on, call subroutine ■; when it is on, call #
Proceed to A-18.

#Δ−! 8 When February setting column setting 75 is on, subroutine ■ is called; when it is on, subroutine # is called.
Proceed to A-19.

#A-19: When the date setting switch 76 is turned on, subroutine ■ is called, and when it is turned on, #
Proceed to A-20.

#A-20: When the erase standby switch 77 is turned on, subroutine (2) is called, and when it is turned on, the process advances to #A-21.

#A-21: When the all-track erase standby switch 79 is on, subroutine (2) is called, and when it is on, the process advances to #A-13.

As explained above, after the head 3-1 has accessed the first track of the magnetic sheet by executing the flow shown in FIG. 5, the flow jumps to the flow shown in ■ in FIG. While detecting the state of each switch shown in Figures 3 and 4, the flow shown in Figure 4 until the state of each switch changes is executed repeatedly, and a subroutine corresponding to the operated switch is called. .

Here, the subroutine [F] called when the track setting feed speed switch 56 is turned on will be explained using FIG.

FIG. 7 is a flowchart showing a subroutine executed when the switch 56 for changing the track setting feed speed is turned on.

#F-1. #F-2: The set value of the track feed speed is read from the memory, and the set value is set in a track number display buffer (not shown).

Therefore, the two-digit 7-segment LE shown in Figure 3
The track feed speed is displayed on D25. If the flow comes to this step for the first time, the flow rate is 2 per second at #l.
Since the track advance speed on the screen is set, select “2”.
” is displayed.

9F-37 When the track feed speed setting switch 56 is on, the flow repeats #F-3, and when the switch 56 is turned off, the flow moves to #F-4.

As mentioned above, once the track feed speed setting switch 56 is turned on, the two-digit 7-segment LED 25 shown in FIG. 3 switches from displaying the track number to displaying the track feed speed.
Next, the track feeding speed is changed by turning on the switch 56 again.

#F-3 is provided so that the track feed speed is switched only when the switch 56 is turned on, once turned off, and then turned on again as described above.

#F-4. #F-5. #F-6. #F-7: In these steps, the track feed speed setting switch 56 is turned on, and the 2-digit 7-segment LED 25 shown in FIG.
If the switch 56 or the pond switch is not turned on within a predetermined period of time (2 seconds) after the display changes from the track number display to the track feed speed display, the setting of the track feed speed is canceled. These steps are designed to help you.

Predetermined time (2 seconds) after timer l starts counting
When the track feed speed setting switch 56 is turned on during this period, the flow progresses from #F-7 to #F-10, and when timer 1 completes timing, or when another switch is turned on, the flow advances from #F-7 to #F-10. The flow advances from -6 to #F-8.

#Clear the count value of F-8+timer 1.

#F-9: Contrary to #F-1, the display of the two-digit 7-segment LED 25 shown in FIG. 3 is returned to displaying the track number.

#F-10: Clear the count value of timer l.

3F-11: Detects whether the set value of the track feed speed is single (once recorded or played back, the head is shifted by one track in field mode, and the head is shifted by two tracks in frame mode and then stopped). , in the case of single, the flow advances to #F-12, and in the case of non-single, the flow advances to #F-13.

Note that, as described above, when the flow reaches this step after the power switch 41 is turned on, the track feed speed is previously set at 2 screens per second in #l.

#F-12 If the track feed speed setting value is single, change the setting value to 2 screens per second, return to #F-1, display the changed track feed speed, and return to # above.
Execute F-3 to #F-7.

#F-13:) Detects whether the rack feed speed setting value is 2 screens per second, and if it is 2 screens per second, the flow goes to #F-14, and if it is not 2 screens per second, the flow goes to #F-15. .

#F-14 Change the track feed speed setting value to 5 screens per second, return to #F-1, display the changed track feed speed, and execute the above-mentioned steps #F-3 to #F-7.

$F-15 + Track feed speed setting value is 5' per second
Detect whether it is a screen, and if there are 5 screens per second, #F-1
If the screen rate is not 5 screens per second, that is, if 10 screens per second is set, the flow advances to #F-17.

#F-16: Determine whether the PB mode flag is set. If the PB mode flag is set, that is, if the playback mode is set, #F-18
If the PB mode flag is reset, that is, if the recording mode is set, the flow advances to #F-19.

#F-17: Change the track feed speed setting value to single, return to #F-1, display the changed track feed speed, and execute the above-mentioned steps #F-3 to #F-7.

#F-18: In the playback mode, regardless of whether the video signal recorded on the track of the magnetic sheet l is a field video signal or a frame video signal, field playback is performed during continuous track feeding. Therefore, in such a case, change the track feed speed setting value to 10 screens per second and the flow will be #
Return to F-1.

#F-19: Detects whether or not the field flag is set, and if the field flag is set, that is, if track advance is set at 5 screens per second in recording mode and in field mode, #F is detected. The flow branches to -18.

Also, if the field flag is not set, that is, the track feed speed setting value of 5 screens per second is set in recording mode, and in frame mode, #F-17
The flow advances to change the track feed speed setting to single.

Therefore, in the above-mentioned subroutine [F], when the track feed speed setting switch 56 is turned on, the track feed speed is displayed on the two-digit 7-segment LED 25 shown in FIG. 3 for a predetermined period of time (2 seconds). The track advance speed is changed by turning on the switch 56 again within the time.

In addition, the range of changes is single, 2 screens per second, and 5 screens per second when in frame recording mode, and single, 2 screens per second, and 5 screens per second when in other than frame recording mode.
There are 4 types of screens, 10 screens per second.

The scope of this change is head 3-1.3-2 shown in FIG.
This is related to the track shifting ability of the moving mechanism, etc., and is set in advance to an appropriate range depending on the track shifting ability.

Next, using FIG. 8, while executing the subroutine shown in FIG. 6, the track UP switch 54. TRACK DOWN
Subroutines ① and [F] that are called when the switch 55 is turned on will be explained. First, a flow called when the track UP switch 54 is turned on will be described.

#D-1: When the flow reaches this step, detect whether the track being accessed by the head 3-1 is the innermost track or not and whether the register N is 50. Determine by.

As a result, if N is not 50, go to #D-2;
If it is 0, the flow advances to #D-34, which will be described later.

#D-2: Determine whether the PB mode flag is set. When the PB mode flag is set, that is, in playback mode, #D-8; when the PB mode flag is not set, that is, in recording mode, #D-8
The flow advances to 3.

#D-3: Detect whether the N+1 address of the memory is "0000", that is, the N+2th track is unrecorded. If it is unrecorded, it is set to #D-4. If it is already recorded, it is #D-7. Flow branches.

@D-4: No. N+1) - If it is determined in #D-3 that the rack has not been recorded, it is determined in this step whether or not the field flag is set, and if it is set, If it is not set, the flow advances to #D-5.

#D-5: When it is determined in #D-4 that the field flag is not set and the mode is frame mode, this step is reached. In this step, it is detected whether or not the N+2 content of the memory is "0000", and if it is "0000", that is, the N+
If 2 tracks are unrecorded, go to #D-6, “o
ooo", that is, if the N+2 track has already been recorded, the flow advances to #D-7.

By executing Steplap from #D-3 to #D-5, if both consecutive two tracks are unrecorded in frame mode, the step will be changed to #D-6, and the step number ( If both have already been recorded, #D-
The flow advances to 7.

#D-6: In the field mode, the track accessed by the head 3-1; in the frame mode, the track accessed by the head 3-1, and the track on the inner circumference side of the track If the track being accessed by the head 3-2 is unrecorded, that is, if it is recordable, the flow reaches this step, and the RECLED shown in FIG.
44B lights up.

$D-7: Head 3-1.3-2 opposite to #D-6
If the track to be accessed and recorded has already been recorded, a warning is displayed by blinking the RECLED 44B shown in Figure 3 to make the user aware that recording is not possible. I do.

@D-8: If the PI3 mode flag is set in #D-2, the flow reaches this step and the field flag is set.

For the meaning of this step, #D-9゜#D-1o,
#D=13 will be explained.

#D-9: Memory address N is “0011”, i.e. #13
As explained above, it is detected whether or not the track being accessed by the head 3-1 is the outermost track of the two tracks constituting the frame video signal, and it is determined whether the track is the outermost track of the two tracks. If so, the flow proceeds to #D-10, and if the track is not on the outer circumferential side, the flow proceeds to #D-13.

#D-10: Detects whether address N+1 of the memory is "0010", that is, whether the track being accessed by the head 3-2 is the inner track of the two tracks constituting the frame video signal; If the track is on the inner side of the two tracks, the flow proceeds to #D-11, and if it is not on the outer side, the flow proceeds to #D-13.

That is, if the inner track of the two tracks making up the frame video signal is erased or a new video signal is recorded after erasing, the track accessed by the head 3-1 will make up the frame video signal. Even if it is the outer track of the two tracks, the head 3
It happens that the track being accessed by -2 is not the inner track of the two tracks. Therefore, in this case, when shifting the head 3-1, 3-2 to the inner circumferential side, it is necessary to shift only one track and reproduce the erased or track on which the video signal is newly recorded after the erased.

However, in such a case, the head 3-1°3-2 is
When only the track is shifted to the inner circumferential side, the head 3
-1.3-2 does not necessarily have a frame video signal recorded on the track that is being accessed, and may also have a whole (different field video signal) recorded on it. In this case, the field flag is reset. If this happens, a problem arises in that two separate field video signals are reproduced as a frame video signal.
In this embodiment, by providing 8 steps, when the head is shifted to the inner circumferential side, a field flag is set in advance in this step to set the field mode, and even in the above case, a completely different field video signal is generated. It is possible to solve the problem that the video signal is reproduced as a frame video signal.

$D-11; In this step, it is detected whether register N is 49 or not, and if N is 49, #
If N is not 49, the flow branches to $D-12.

#D-12; The flow reaches this step when frame video signals are being recorded on the two tracks accessed by heads 3-1 and 3-2. If such a recording is made, track U
When the P switch is turned on, the driver 23 is driven to shift the heads 3-1, 3-2 by 2 troughs in this step, and then in #D-13, the driver 23 is driven to shift the heads 3-1, 3-2 by 2 troughs. Shift 3-2. Further, as described above, N is updated by l each time the heads 3-1, 3-2 are shifted.

#D-13; Similar to #D-12, head 3-1.3
-2 is shifted by one track.

Similarly to #D-14 and #23, N is displayed on the 2-digit 7-segment LED 25 shown in FIG.

In this embodiment, these steps are #D-12 and #D-13.
Heads 3-1 and 3-
When a frame video signal is recorded on the accessed track 2, the track number displayed on the LED 25 is updated by 2, and when a field video signal is recorded, the track number displayed on the LED 25 is updated. The number is updated by l, and it is possible to display whether a field video signal or a frame video signal is recorded on the magnetic sheet l.

Additionally, if this step is also provided between #D-12 and #D-13, if frame video signals are recorded on the two tracks accessed by heads 3-1 and 3-2, Even if there is, when the track UP switch 54 is turned on, the track number displayed on the LED 25 will be updated one by one.

#D-15; Determine whether the PB mode flag is set. #D-16 if set
If it is not set, the flow branches to #D-19.

If set, branch to @D-15-1.

#D-15-1; Here, the CPU 40 stores the reproduced ID signal output from the data demodulator 12 in FIG.
Incorporate into 27. The flow advances to #D-15-2.

#D-15-2; Here, it is determined whether the mode is one in which the ID is superimposed on the video signal and monitored. Details of this mode will be explained using Section 201g. If it is in this mode, proceed to #D-15-3; otherwise, proceed to #D-15-4.

#D-15-3 When the flow reaches this step, the mode is in which the ID is superimposed on the video signal and monitored, so the CPU reads out the reproduced ID signal from the RAM 27 and controls the character generator 40 to generate the character pattern. is generated and superimposed on the playback video signal on the monitor. The flow advances to #D-15-4. That is, at this point, the ID DATA signal recorded in the currently accessed track is displayed on the monitor.

#D-15-4; If the automatic track feed flag is not set, the flow branches to #D-20, and if it is, the flow branches to #D-16.

#D-+6; Memory address N is "0011" It is determined whether the track being accessed by the head 3-1 is one of the tracks on the outer circumferential side where the frame video signal is recorded. Here, N corresponds to the number of the track that the head 3-1 is accessing after the heads 3-1 and 3-2 have already been moved, as repeated above. Here, the content at address N of the memory is “00”.
11”, the flow is “0011” to @D-17.
”, the flow branches to #D-19.

#D-t7; Memo IJ-(D N+1 address) Content power '0010'.

That is, it is determined whether the track being accessed by head-3-1 is the inner track of the two tracks on which frame video signals are recorded.

Here, if the memory address N+1 is "0010", the flow branches to #D-18, and if it is not "0010", the flow branches to #D-19.

#D-18; If the flow reaches this step via #D-'16 and #D-17, head 3-1.3-
Since frame video signals are recorded in the two tracks accessed after the movement of #2, the field flag set in #D-8 is cleared and the frame playback mode is set. Note that this step is executed only if the automatic track advance flag is set.

(If the automatic track advance flag is not set, the flow branches from #D-15-4 to #D-20, so the field flag remains set in #D-8, so field playback is performed. ) #I)-+9; In this step, it is determined whether or not the automatic track feed flag is set. Return (R”r S).

The automatic track advance flag is a flag that is set in subroutine ■, which will be described later. A drain is provided for extracting air from O1■.

#D-20; Import the track feed speed setting value from memory.

#D-21: ) Determine whether the rack feed speed setting value is single or not, and if it is single, check #D-
34, if it is not single, the flow branches to #D-22.

#D-22: )-Determine whether or not the rack feed speed setting value is 2 screens per second, and if it is 2 screens per second, use #l)-23, and if it is not 2 screens per second, use #D-
24, the flow branches.

#D-23; WAIT TI in CPU 40
Set the MER register to 28.

#D-24; l-Determine whether the rack feed speed setting value is 5 screens per second, and if it is 5 screens per second,
If there are not 5 screens per second, the flow branches to #D-26.

#D-25: WAIT TIMER register to 1
Set to 0.

#D-26; If 10 screens per second is set as the track feed speed setting value, the flow reaches this step and the WAIT TIMER register is set to 4.

Note that the WAIT TIMER registers set in #D-23, #D-25, and #D-26 are used to control the track feed speed, and are set in #D-3, which will be described later.
1° #D-32 is subtracted every time the magnetic sheet l is rotated once by the DC motor 2.

#D-27; Determine whether or not the REC execution flag is set, and if it is set, #D-28;
If not set, the flow branches to #D-31. Here, the REC execution flag is a flag that is set in subroutine ■, and is a WAIT flag that is set when subroutine ■ is called during the execution of a program that repeats recording while automatically sending tracks.
This is provided to obtain the time equivalent to the time required for recording by subtracting 2 or 5 from the TIMER register in #D-29 and #D-30. That is, in the recording mode, the rotational state of the magnetic sheet l is controlled by the PC coil 2! It is provided to determine the timing for recording a signal to be detected and recorded from a predetermined position on the magnetic sheet, and to record the signal on the magnetic sheet 1.

Subtract 2 from the TIMER register, and if not set, subtract 5 from the WAIT TIMER register. Here, if 10 screens per second is set as the track feed speed, the WAIT TIMER register is set to 4, but such a setting is possible only in field mode, so in this case, the WAIT TIMER register is set to 4.
TIMEI? Five is never subtracted from the register.

#D-31; Detects whether or not there is a pulse from the reference signal generator I9 shown in Figure 1. If there is a pulse, go to #D-32; if not, go to #D-31. Repeat the flow.

#D-32; Subtract 1 from the contents of the WAIT TIMER register.

#D-33; Determine whether the content of the WAIT TIMER register has become 0, and if it is 0, #D-3
4, if not O, branches to #D-31.

In steps #D-32 and #D-33, the timer for controlling the track feed speed is set to WAITTI.
A MER register and a reference signal generator 19 were used. Therefore, compared to the method of configuring a timer by subtracting the contents of the WA4T TIMER register according to the output of the waveform shaping circuit 22 that shapes the waveform of the output of the PC coil 21, stable and more accurate clock operation can be performed. I can do it. That is, the output of the PG coil 21 may contain errors due to causes such as uneven rotation of the magnetic sheet l, but the output of the reference signal generator 19
The output of is substantially free of such errors. Further, when performing interval recording, it is desirable to stop the rotation of the DC motor 2 during the interval time in order to save power consumption.

When performing such an operation, the method of subtracting the WAIT TIMER register according to the output of the waveform shaping circuit 22 is as follows.
Although it is not possible to measure the interval time over time, the method of this embodiment makes it possible to perform a stable timekeeping operation even when such an operation is performed.

#D-34; Determine whether or not the REC execution flag is set, and if it is set, return (RTS) to the original program that called the subroutine O. If it is not set, # Branch to D-35.

#D-35; Determine whether or not the track UP switch f-54 is on, and if it is on, further move the track accessed by the heads 3-1 and 3-2 from the inner circumference. The flow branches to #D-1 to shift to the side, and to #D-36 when it is off.

#D-36;) Determine whether or not the rack DOWN switch 55 is on, and if it is on, shift the track accessed by the heads 3-1 and 3-2 to the outer circumferential side. Therefore, the process branches to #E-1 of subroutine (2), and when it is off, the process branches to #D-37.

@D-37; If the PB mode flag is set, go to #D-38; otherwise, go back to the program that called the subroutine (2).

Clear. Then the subroutine Return to the bologram that called O.

In the above example, #D-23 is passed regardless of whether it passes through #D-12 in Pa mode or not.
, 25, and 26, if the value set in WAIT TIMER is not changed, and #D-12 is passed by the time required to perform l-track feeding, the track feeding speed will be delayed. However, in order to match this, in #D-27, #D-12
If the time required to advance the head for one track is subtracted from WATE TIMER, the total (problematic) track advance speed can be adjusted.

Next, subroutine (2) executed when the track down switch 55 is turned on will be explained.

Each step @E-1 to #E-13 of subroutine (2) is the same as each step #D-1 to #D-13 of subroutine (2), so a detailed explanation will be omitted.

However, subroutine ■ is track DOWN switch 55.
For example, #E- is used to shift the track accessed by head 3-1, 3-2 to the outer circumferential side when is turned on.
1, it is detected whether N=1, and in #E-9, the memory (N-1) battery is “ooto”, that is, the (Nth
-1)) Detects whether the rack is the inner track of the two tracks constituting the frame video signal, and #E-10
In this case, the memory address (N-2) is "001 bit", that is, the (N-2)th track constitutes the frame video signal.
It detects whether the track is outside the tracks, and also detects whether N=2 in #E-11, and @E-11 detects whether N=2.
12. In #E-13, l trough 2 minute head 3-1, 3-
2 to the outer circumference.

Next, with reference to FIG. 9, subroutine (2) which is called when the field/frame changeover switch 59 and the REC mode setting switch 51 are turned on will be explained.

#J-1: When it is detected in #A-10 shown in FIG. 6 that the field/frame changeover switch 59 is turned on, the flow advances to this step, and in this step, the field flag is set. If it is set, go to #J-2, if it is not set, go to #J-4
The flow branches.

#J-2: When the field flag is set in #J-1, the field flag is cleared in this step.

#J-3; Determine whether or not the PB mode flag is set. If it is set, the flow branches to #J-8; if not, the flow branches to #J-5.

#J-4; When it is detected in #J-1 that the field flag is not set, the field flag is set in this step.

If the PB mode is not set, that is, in recording mode, and the field flag is cleared in #J-2, frame recording mode is entered, and as explained in subroutines ■, ■, and [F], every second 10
Continuous recording of the screen is not possible. Therefore, when switching from field mode to frame mode in the subroutine, if the track feed speed is set to 10 screens per second,
Such switching should be prohibited.

Therefore, according to this embodiment, #J-6 and #
When a track feed speed of 10 screens per second is set by J-7, the track feed speed setting value is automatically changed to a track feed of 5 screens per second. -0 #J-5: ) Rack feed speed setting value CPU4
Take it to 0.

#J-(i; If the track feed speed setting value imported in #J-5 is 10 screens per second, go to #J-7, otherwise go to #J-7.
The flow branches to J-8.

#J-7; Change the track feed speed setting value to 5 screens per second.

#J-8: If the field/frame setting switch 5I continues to be turned on, this step is repeated, and the process returns to step #A-1 in FIG. 6 for the first time when it is turned off from on.

Next, subroutine (2) called when the REC mode setting switch 51 is turned on will be explained.

#B-1; R at #A-1 shown in Figure 6
When it is detected that the EC mode setting switch 51 is turned on, the flow branches to this step, the PBS LED 44A shown in FIG. 3 is turned off, and the PB mode flag is cleared.

#13-5-1; This step uses CPU40
controls the character generator 84 to temporarily stop character generation.

#11-5-2: Determine whether or not it is the ID setting mode. If it is the setting mode, proceed to #B-5-3; otherwise, proceed to #B-6'.

#B-5-3; The CPU 40 reads the set ID from the RAM 27 and controls the character generator 84 to generate a character pattern. Therefore, the ID is displayed on the monitor 13 superimposed on the video signal input from the video signal input terminal 18. The flow then proceeds to #B-6'.

#n-6', this step is repeated while the REC mode setting switch 51 continues to be turned on, and when the switch is turned off, the flow branches to #B-7.

#Loaf; REC mode setting switch 5! When the field flag is turned off, it is determined in this step whether the field flag is set, and if the field flag is set, the flow returns to the step shown in #A-1 in Figure 6, and the field flag is set. If it is not set, jump to #J-5 of subroutine ■, and #J
By executing steps -6 to #J-8, when the track feed speed setting value is 10 screens per second, it is automatically corrected to 5 screens per second. Therefore, when the RFC mode is set by the REC mode setting switch 51 and the frame mode is set, the track feed speed setting value is limited to a maximum of 5 screens per second.

Next, using FIG. 1O, the subroutine ◎ called when the n mode setting switch 53 is turned on will be explained.

#C1; #A-: (at l) shown in FIG. 6 When it is detected that the IF mode setting switch 53 is turned on, the flow branches to this step and the RECL
ED is turned OFF and the field flag is temporarily set. That is, separate field video signals are recorded on the two tracks being accessed by heads 3-1 and 3-2, and a frame recording mode is set in which the PB mode flag is cleared and the field flag is reset. In this case, if it is detected that the PBn mode setting switch 53 is turned on and the track being accessed by the head 3-1.3-2 is immediately played back, separate field video signals are prevented from being played back in an interlaced manner. Therefore, a field flag is set once in this step.

#C2; Memory address is “0011”, ie head 3
- Is the track being accessed by 1 the outermost of the two tracks on which the frame video signal is recorded?
is detected, and when it is “0011”, “00” is sent to #C-3.
11'', the flow branches to #C-5.

#C-:1; Memory address N+1 is “0010”
That is, it is detected whether the track being accessed by the head 3-2 is the inner track of the two tracks on which the frame video signal is recorded, and if it is "ooto", #C-
When the flow is not "0010" to #4, the flow branches to #C-5.

#C-4; Head 3- in #C-2 and #C-3
When it is detected that frame video signals are recorded in the two tracks that are being accessed by 113-2, the flow reaches this step and 1. Field flags are cleared and frame mode is set.

#C-5: pHSL1D/11I shown in Figure 3
A lights up, the PB mode flag is set, and the playback operation is started.

#C-5-1; In this step, the CPU 40 controls the character generator 84 to temporarily stop generating characters. Further, the CPU 40 stores the ID DATA demodulated by the data demodulator 12 in the RAM 27.

#B-5-2; Determine whether or not it is in ID display mode, and if it is in display mode, proceed to #C-5-3;
If not, proceed to #C-6'.

#C-5-3; CPU 40 is a data demodulator from RAM 27! The character generator 8 reads out the ID demodulated by the character generator 8.
4 to generate a character pattern. Therefore, the ID is displayed on the monitor 13 superimposed on the video signal reproduced from the magnetic sheet. Then the flow is #C
-Proceed to 6.

#C-6; If the Pn mode setting switch 53 continues to be turned on, repeat this step, and if it is turned off, go to #A-1 through #A-1 shown in FIG.
Return to

Next, using Fig. 11, set the interval time setting switch 5.
Subroutine O that is called when 7 is turned on will be explained. First, in the subroutine 0SC-O, the timer '1' is initialized to 0 and the timer '1' is initialized to 7.
The interval time T i is displayed on the segment LED 25.

#G-1; When it is detected that the interval time setting switch 57 is turned on in #A-7 of FIG. 6, the timer 'r' is initialized to O, and the flow then reaches this step. , plus 10 key switches 63-72
When turned on, go to #G-2, lO key switch 63
72 is not turned on, the flow branches to #G-3.

#G-2; Set the interval time "l?i" to the interval time T set by the 10 key switches 63 to 72.
Change to i.

#C; -3, Determine whether or not the In key switches 63 to 72 are turned on. If they are turned on, go to #G-4. If not, branch to #G-5. do.

#G-4; Detects whether or not the interval time setting switch 57 is turned on, and when it is turned on, #G-4;
When G-1 is not turned on, #A- shown in Figure 6
The flow branches to 1.

#G-5: Increase the aforementioned 'r' by 1. The flow moves to #G-6 every second.

However, T' is a timer that is incremented by l every second, and no addition is made if less than one second has elapsed.

#G-6; Determine whether “f” is IO or not, and
If T' is 10, branch to #A-1 shown in FIG.
1, #G-3, #G-5 and #G-6 are repeated, and when '1' becomes lO, the process returns to #A-1. .

Therefore, in the subroutine (2) described above, if no other switch is turned on within 10 seconds after the interval time setting switch 57 is turned on, the process returns to #-1 shown in FIG. 6 and the interval time setting is canceled. Of course, the interval time while executing the subroutine ■゛i
is displayed in 2-digit 7-segment L E I) 25, but in #G-6, #A-! The display of the interval time 'ri required when returning to is stopped.

Also, in this subroutine ◎, 1j at interval
1ji! When ``i'' is set to ``0'', an external trigger mode is set for performing an operation when connecting to a printer, for example, as described in subroutine (2) as a reproduction operation.

Next, subroutine (2) called when the RFC switch is turned on will be explained using FIG. 12.

#N-1; When it is detected that the summer EC switch 52 is turned on in #A-2 of FIG. 6, the flow reaches this step, and it is checked whether the I'13 mode flag is cleared or not. is detected, and when it is not cleared, the flow returns to #A-14 shown in FIG. 6 (RTS) because it is in the playback mode, and when it is cleared, the flow branches to #N-2.

Therefore, if the REC mode is not set, no recording will be performed even if the REC switch 52 is turned on.

#N-2; It is determined whether the N address of the memory is "oooo", that is, whether the track being accessed by the head 3-1 is unrecorded or not. If it is not unrecorded, the process shown in FIG. 6 is performed. The flow returns to #A-14, and if it is unrecorded, the flow branches to #N-3.

#N-3: It is determined whether the field flag is set, and if it is set, the flow branches to #N-5, and if it is not set, the flow branches to #N-4.

#N-4; This step is performed when frame recording mode is set, but memory N+1
It is determined whether the address is "0000", that is, whether or not the track being accessed by the head 3-2 is unrecorded. If it is not unrecorded, the flow goes to #-14 shown in FIG. return. In such cases, REC, I, E D
4413 is blinking.

This track was also unrecorded. In this case, the flow branches to #N-6.

#N-5: A video signal for one field is recorded on one track on the magnetic sheet I by the head 3-1. At this time, SW6 shown in FIG. 1 is turned off and the output of the character generator 84 is no longer output to the monitor. Also, 0001 is set in the memory address N.

#N-6; When the flow reaches this step, the frame recording mode is set, so write the two tracks on the magnetic sheet l respectively! Video signals for fields are recorded by heads 3-1 and 3-2. 0011 is set to memory address N and 0010 is set to address SN+1 and #N-
Similarly to 5, SW 6 is turned off. Next, the step motor 24 is driven to shift the heads 3-1 and 3-2 inward by l track.

Note that when #N-5 and #N-6 are executed, SW2 to SW5 are driven as explained in FIG. Also #N-6
When recording is executed in the CP [140], the set ID is read from the RAM 27, and by outputting this to the data modulator 14, the ID modulated into a DPSK signal from the data modulator 14 is recorded. Amplifier 1
6, where it is superimposed on the video signal and ID recording is performed. However, the ID display mode is the 20th mode described later.
In the case of Figure C), even if the data is set, the ID
will not be recorded. However, DATA indicating whether it is the inner track, outer track, or field recording of the frame
is simply recorded together with the video signal. Also the second
Even in the display mode of Figure 0 a) b) #N-5. #N
By executing -6, the ID DATA signal will not be displayed on the monitor because SW6 is turned off during recording.

#N-7: The REC execution flag is set and SW6 in FIG. 1 is turned on.

By executing #N-1 to #N-7, when the set ID is generated by the character generator 84, superimposed on the video signal, and output to the monitor, the REC
The character signal that is generated only during execution is SW in Figure 1.
6 will turn it off and the characters will disappear. At #N-7, SW6 is turned on again, so ID DATA is displayed again.

#N-8; Call subroutine O, head 3-
If 1 is accessing a track other than the 50th track, #
D-1. The flow moves from #D-2 to #D-3. Next, steps #D-3 to #D-14 are executed to move the heads 3-1 and 3-2 inward by one track. If you are in frame recording mode, set #N-6 in advance! Since the heads 3-1 and 3-2 have been moved inward by a track, the head 3-1 accesses the track adjacent to the track recorded in #D-14 even in the frame recording mode. Further, when the tracks recorded by the heads 3-1 and 3-2 have been recorded, the REC and LED 44B shown in FIG. 3 blink to warn the user.

The flow then branches from #D-15 to #D-19 and #
The flows shown in #D-20 to #D-34 are executed via D-19.

That is, if the track feed speed setting value is single, the flow branches from #D-21 to #D-34, and returns to #N-9 according to the REC execution flag set in advance in #N-7. .

If 2 screens or 5 screens per second are set, subtract the WAIT TIMER register by the time necessary for recording in #D-28, and then
Count down the TIMER Regis evening and WAI”r
When the TIMER register becomes 0, the flow is #1]
#N according to the REC execution flag set in #N-7 from -33 to #D-34 in the same way as described above.
- Return to 9.

#N-9: Clear the REC execution flag.

#N-10; This step is similar to #D-20, and the set value of the track feed speed is read from the memory.

#N-II; If the set value of the track feed speed is single, go to #N-12; if not, go back to #A-14 shown in FIG. 6.

#N-12;) When the rack feed speed is set to single, this step is repeated as long as the REC switch 52 is on, and subroutine (2) is executed again to control so that no recording is performed.

When the track feed speed is set to other than single and the REC switch 52 is turned on, 5N-
11 calls subroutine 0 from #l\-11#A-2 via #l\-14, and the above flow is executed.
As long as the EC switch 52 is on, recording is performed continuously at the set track feed speed. If the REC switch 52 is turned off, the flow is #A-14, #Δ-1
．． The process advances to #A-2, but the continuous recording ends without calling subroutine (2) in #A-2.

Next, the subroutine (2) called when the program setting switch 58 is turned on will be explained using FIG.

#ll-1; When it is detected that the program setting switch 58 is turned on in #A-8 of FIG. 6, this step is reached, and it is determined whether the PB mode flag is set and the setting When it is set, the process returns to #ll-2, and when it is not set, the process returns to #A-1 shown in FIG. 6 (RTS).

In this step, set the program setting to M! in recording mode. It is provided for the purpose of That is, in this embodiment, when setting a program, a playback mode is selected in advance, so that the program is set while checking the image recorded on the magnetic sheet 1 on a monitor, for example.

Also, automatically when the program setting switch 58 is turned on! ) By setting the B mode flag, the operation to the reproduction mode can be performed automatically.

In this case, a CALLC may be provided to call the subroutine ◎ in place of the step shown in subroutine ◎, that is, in place of the step shown in #II-1.

#ll-2; In the program track memory shown in FIG. 14 in which the program is stored, when the program is being played back, the register (2) indicating the address where the track number to be played next is stored is set to ().

all-a; Set the program playback mode flag indicating that it is in program playback mode and t: A
Return to I.

Next, the 15th subroutine ■ is called when the program track setting switch 62 is turned on after the program playback mode is set by the subroutine ■.
This will be explained using figures.

#l-1: Determine whether the program playback mode flag is set, and if it is set, #■-2
is not set, the flow branches to #A-1.

Therefore, when the program playback mode is not set by the program setting switch 58, no program setting operation is performed even if the program track setting switch 62 is turned on.

#[-2: The same contents as the contents of register S (initially set as 5=() when the power is turned on in #l) indicating the start address where the program of the program track memory is stored are transferred to register M. Write.

#I-3: The data in the program track memory at the address stored in register M is
stored at a larger address. In other words, the data indicating the track number stored in the program track memory is stored at an address larger by l than the address where the data is stored.

#I-4; Write the value obtained by adding 1 to the contents of register M to register l.

#T-5; Subtract 1 from the contents of register M.

#I-6; Determine whether the contents of register M are 0 or not,
If it is 0, the flow branches to #■-7, and if it is not O, the flow branches to #I-3.

Repeat the flow from #I-3 to #I-6, and when the contents of register M become 0, all data stored at each address in the program track memory is transferred to an address that is 1 larger. Therefore, when this flow is repeatedly executed and the flow branches from #!-6 to #l-7, no data is stored at address l of the program track memory.

@1-7: The number of the track that the head 3-1 is accessing is stored at address l of the program track memory. Therefore, by turning on the program track setting switch 62, the number of the track where the video being accessed by the head 3-1 and being reproduced is recorded is programmed.

#I-8: Add 1 to the contents of register S. By executing this step, register S always has #I
-3~#! The start address (largest address) where the data of the program track memory moved by executing the flow of -6 is stored.

#I-9; If the program track setting switch 62 is turned on, repeat this step, and if it is turned off, return to #A-1.

If the user wants to continue setting the program, turn on the track UP switch 54 or the track DOWN switch 55 to set the head 3-1.3-.
Program settings can be made by changing the track being accessed in No. 2 and turning on the program setting switch 62 while checking the reproduced video when the desired track has been reproduced.

Note that each time the program setting switch 62 is turned on, the 14th
The data stored at each address of the program track memory shown in the figure is stored at an address larger by l. Also, during program setting, register S register (2) and register (all have the same contents).

Next, program playback is performed to play back the program set by turning on the program setting switch 58 and the program track setting switch 62, and the head 3-1
The first part about the program executed when performing interval playback, which plays recorded tracks sequentially at a set interval time, starting from the track being accessed.
This will be explained using FIGS. 6 to 18.

First, the subroutine (2) called when the start switch 60 is turned on will be explained with reference to FIG.

#-i; When it is detected that the start switch 60 is turned on in #A-11 of FIG. 6, the flow reaches this step, and it is detected whether the PB mode flag is set and the PB mode flag is set. When the mode flag is not set, the flow branches to #A-1, and when the PB mode flag is set, the flow branches to #-2. Therefore, in this embodiment, if the playback mode is not set in advance, interval playback and program playback cannot be performed, so even if the start switch 60 is turned on by mistake during the recording mode, interval playback and program playback will start. It is possible to prevent this from happening.

Also, by providing a step similar to the step shown in subroutine ◎ instead of -1 in #, it is possible to immediately start playing the interval playback program by simply turning on the start switch 60 without having to set the playback mode in advance. .

-2 to #: It is determined whether or not the program reproduction mode flag is set, and if it is set, the flow branches to #-13. If it is not set, the flow branches to #-4.

Here, the flow will be described when the program playback mode flag is not set, that is, when interval playback is performed.

-4 to #: Determine whether or not the memory address N is "oooo", that is, the track accessed by head -1 is unrecorded, and if it is unrecorded, it must be unrecorded at #16. The flow branches to -5 at #. First, the flow from #K-6 will be explained assuming that the track being accessed by the head 3-1 is unrecorded.

According to this embodiment described below, when the track being accessed by the head 3-1 is other than the 49th or 50th track, the interval playback is performed from the track to the track being accessed by the head 3-1. If the track is the 49th or 50th rack, only the recorded tracks will be played back sequentially from the 1st track, but if the head 3-1 is set between #-2 and #-4, If a step of driving the step motor 24 is inserted to access one track, only the tracks that have been recorded sequentially from the first track are always reproduced.

Therefore, when the head 3-1 is not accessing the first track but is accessing another track, it is extremely effective for automatically performing interval playback sequentially from the first track and performing a search. .

-6 to 9; Sets the automatic track advance flag indicating that interval playback is in progress.

9 to -7; It is determined whether or not the field flag is set, and if it is set, the flow branches to # to 8. If it is set, the flow branches to # to -9.

#-8; It is determined whether the track that the head 3-1 is accessing is the innermost track by detecting whether N is 50, and it is detected that N is 50. In this case, the flow branches to #-1o, and when 50 is not detected, the flow branches to #-11.

-9 to #; Indicates whether the track that the head 3-1 is accessing is one track outside the innermost circumference.
The determination is made by detecting whether or not 49.
When 9 is detected, the flow branches to #-10 and when 48 is not detected, the flow branches to #-11.

-10 to #; In this step, the interval time T set by executing subroutine ■
It is determined whether or not i is "0". As will be described later, when the interval time Ti is 0'', it is a mode in which the head 3-1 is shifted according to a preset program according to an external trigger signal, and for this mode, the interval time Ti is 0''. When set to ON, the flow branches to #A-1, and when not set to "0", the flow branches to #-12.

-11 to #; Call subroutine O, #D-1
The flow shown in ~#D-18 is executed.

When subroutine ◎ is called in subroutine ■, the PB mode flag is set, so the flow branches from #D-2 to #D-9, and the track accessed by head 3-1 at #-4 is It is determined that the track on the outer circumference of the frame and on the inner circumference of this track is the inner track of the two tracks on which the frame video signal is recorded, and that the head 3-1 is not accessing the 49th track. In this case, head 3-1.3-2 is #
When the head 3-1, 3-2 is shifted inward by two tracks by D-12 and #D-13 and no discrimination is made, the head 3-1, 3-2 is shifted inward by one track by #D-13.

Further, if a frame video signal is recorded in the track being accessed by the head 3-1, 3-2, the field flag is cleared and the flow moves from #D-19 to #D-14.

#-12; Call subroutine ■#E-1~
The flows shown in #E-13 and #D-14 to #D-19 are executed, and the tracks on the outer circumference side adjacent to the track accessed by the head 3-1 at -4 in # and the outer circumference side by one more track are executed. If frame video signals are recorded on two of the tracks, head 3-1.3-2 is #E-
12, #E-13 shifts the track by two tracks toward the outer circumference; otherwise, #E-13 shifts the track by one track toward the outer circumference.

Also, the same as -11 in # (3-IS:? If a frame video signal is recorded in the track accessed by -2, the field flag is cleared and the flow moves from #D-19 to -13 in #) .

-13 for #, and the contents of register N indicate whether the track being accessed by head 3-1 is the outermost track.
When it is detected that it is 1, the flow goes to -14, and when it is not detected that it is l, the flow goes to #I (-12). Branch. Therefore, at #-8 or #-9, #-
If the flow branches to No. 12, that is, head 3-1 is in the 49th
When accessing the track or the 50th track, the head 3-1 is controlled to access the first track by repeating steps -12 to # and -13 to #.

-14 to #; Clear the automatic track feed flag.

As explained above, when the flow from #-14 to #-14 is executed, and the flow branches from #-4 to #-5, the head 3-1 tracks the track where the video signal is recorded. Tracks on which no video signals are recorded are essentially skipped without being played back.

Furthermore, by executing the flow from #K-4 to #K-14, when the flow branches from #K-4 to #K-5, the two tracks being accessed by heads 3-1 and 3-2 are @D if a frame video signal is recorded
Since the field flag is cleared at -18, the frame playback mode is automatically set. Further, when a field video signal is recorded on the track being accessed by the head 3-1, 3-2, the field playback mode is automatically set. Therefore, during interval playback, the most appropriate playback mode is automatically set according to the recording method of the video signal.

-5 to #: The interval time Ti set in the subroutine ◎ is fetched from the memory into the register T' of the CPU 40.

#I(-15, same as -10 for #, interval time T
Detect whether i is "0" and if it is 0, go to #K-17, otherwise go to #-
The flow branches to 16. Here, the following explanation will be given on the assumption that the external trigger mode is not set.

# -16; Timer 1 starts timing operation and proceeds to # -18.

-18 to #; It is detected whether the timer 1 has clocked for 1 second or not. If the timer 1 is being counted, the flow branches to #K-19, and if it is in the middle of counting, the flow branches to #-20.

-20 to #; It is detected whether the stop switch 61 is turned on, and if it is turned on, the flow branches to #A-1; if it is not turned on, the flow branches to #A-21. Here, when the flow branches to #A-1, steps #A-1 to #A-12 are executed again, so when the stop switch 61 is turned on in the normal state, the flow is @A-
The subroutine [phase] will be called from step 12.

The subroutine [phase] will be explained below using FIG. 17.

#M-1; Detects whether the program playback mode flag is set and returns #A if it is not set.
-14, and if set, the flow branches to 1M-2.

1M-2; It is detected whether or not the program playback execution flag is set. If it is set, the flow branches to #M-3; if it is not set, the flow branches to #M-4.

#M-3; Make the contents of register ■ the same as the contents of register S.

#M-4; Set register S to 0 and then execute #M-3.

This subroutine [phase] will be described in more detail in the program playback mode. The following will be described in detail in #121 and subsequent sections.

-21 to #; Detects whether the track UP switch 54 is on, and when it is detected that it is on, calls subroutine ■ and shifts the heads 3-1 and 3-2 to the inner circumferential side and turns it on. If it is not detected, the flow branches to #-22.

-22 to #: Detects whether the track DOWN switch 55 is on, and when it is detected that it is on, calls subroutine ■, shifts the heads 3-1 and 3-2 to the outer circumferential side, and turns it on. If it is not detected, the flow branches to #-18.

-19 to #; subtract 1 from T'.

-23 to #; -24 to # when T' is "O", T'
When is not “On”, the flow branches to #-16.

Therefore, by executing the above-mentioned steps #15 to @23, turning on the track UP switch 54 and track DOWN switch 55 during interval playback will record data on the track adjacent to the track being played. You can play back the videos that are on the screen. In that case, by keeping switch 54 or switch 55 on, the tracks being played can be automatically updated sequentially according to the track feed speed set in subroutine [F], and the number of tracks during interval playback can be updated automatically. It is also possible to easily play back the video that is in front of you.

Furthermore, in this embodiment, before turning on the switches 54 and 55, when playing back a video recorded on a track adjacent to the track being played back by turning on the track UP switch 54 and the track DOWN switch 55, When the remaining time of the interval time Ti of the track being played in is played back, the flow moves from # -23 to # -24 and is updated to play a new track. As shown by the dotted line,
By jumping the flow to -5 at #, it is possible to reset the interval time T' so that the image updated by the switches 54 and 55 can be reliably observed for a certain period of time.

-24 to #; When updating the track to be played after the interval time T' ends, it is detected whether or not the program playback mode is set, and if it is set, it changes to -3 to #. If not, the flow branches to #-6.

Next, about the routine ◎ that branches when the program playback mode flag is set at -2 in #, the 18th
This will be explained using figures.

#O-1; Detects whether the contents of register S is 0" and when "O" is detected, transfers "0'" to #A-1.
When it is detected that this is not the case, the flow branches to #0-2.

As mentioned above, register S stores the start address of the program in program track memory, and the content of register S is "0" if no program is stored in program track memory. Since this indicates the current state, when the value is "0", the process returns to 8 in FIG.

#O-2; Detects whether the contents of register I are “0” and when “O” is detected, transfers to #0-3;
'', the flow branches to #0-3.

As mentioned above, register I stores the address of the track memory where the track number to be played next is stored when program playback is executed.
When executing program playback, as shown in #0-14 below, 1 is subtracted every time one step program playback is executed.

Therefore, the reason why the flow branches to #O-2 and register ■ is detected as "0" is because the program has been set and register S is not "0", and the steps of program playback have been executed. It shows that In other words, when the program playback is executed in - way, #O
-3, the flow branches to #0-5 while the program playback is executed one way.

#O-3, take the interval time Ti set in subroutine ■, detect whether the interval time Ti is “0”, and if it is “0”, the flow starts from routine 0 #
Returning to A-1, the program playback operation ends.

Therefore, in the external trigger mode set by setting the interval time to "0", the program playback operation is stopped after the program playback has been executed twice.

Also, during normal program playback when the interval time Ti is set to a value other than 10'', #
The flow moves to 0-4.

#O-4; Write the contents of register S to register ■.

Program operation is started again.

#O-5, the data (■) at the address of the program track memory set in register ■ (the data written to the address set in register I of the program track memory is shown with parentheses around 1). read out.

#O-6; If data (I) is subtracted from N indicating the track number currently being accessed by the head 3-1 and is less than "O", then #0-7
If it is smaller, the flow branches to #0-8.

#O-7; Set field flag. This set is for prohibiting head feeding in the frame mode like #D-8.

#O-8; Shift the heads 3-1 and 3-2 by one track in the outer circumferential direction.

#O-9; Detects whether the data (1) is equal to N indicating the track number that the head 3-1 is accessing. If they are equal, the data is changed to #0-10. If not, the data is smaller than N indicating the track number. (If ri is larger, the flow branches to #0-11.

#0-10; Move heads 3-1 and 3-2 toward the inner circumference.
Frame playback and field playback are automatically performed depending on whether the video signal recorded from the start is a frame video signal or a field video signal.

Furthermore, by repeating #O-6 to #0-10, Herad 3
-1 is controlled to access the l rack programmed in the program track memory.

#0-14; Subtract 1 from register ■.

#0-15. The program playback execution flag is set. With this step, the flow can be branched by determining whether the program reproduction mode flag is set at -24 in #.

The flow then jumps to #15.

Therefore, when branching to routine O at -3 in #, it is first determined whether or not a playback program is actually set, and then it is determined whether or not the external trigger mode is set, and the external trigger mode is set. When this is the case, the program is executed only one way; otherwise, the program is played repeatedly.

Next, a flow when the external trigger mode is set will be explained. When the external trigger mode is set, the flow branches from #-15 to #-17.

#117'; Detects whether the printer connected as an external device is in the bin mode (executing a print operation), and if it is busy, #A-1; if not busy, #K The flow branches at -18'.

#K-18'; Sends a print start signal to the printer as an external device. The print start signal is executed by setting the signal level of a terminal connected to the printer to H level.

#19'; 150m5ec wait #120
If the printer is busy, the flow branches to #-21', and if the printer is not busy, the flow branches to #-24.

#K-21'; It is detected whether the stop switch 61 is turned on or not. If it is not turned on, the flow goes to #-20', and when it is turned on, the flow returns to #A-1.

When executing the above @K-17' to #K-21', if the printer connected as an external device is busy, the flow returns to #A-1 as described above and another switch is executed again. The flow shown in FIG. 16 is repeated until the switch is turned on. If the start switch 60 is turned on again while repeating the flow shown in FIG. 16, the above-described flow will be repeated and step 17' will be executed again.

Also, if a printer is not connected as an external device, the printer +
The terminal into which the signal from the busy signal output terminal 3' is input becomes an oven and becomes H level. Therefore, if a device such as a printer is not connected even though the external trigger mode is set, the head 3-1.3-
The track being accessed by No. 2 continues to be played, and the track being played is not updated.

Also, if a printer is connected as an external device and the printer is not busy (, #K-17' to #K
If the flow advances to -18', the printer operation is started after the print start signal is sent to the printer and the printer waits for 150 msec as shown in #K-19, and the printer becomes busy. repeats #120' and #121' until the printer operation ends or the stop switch 60 is turned on, and when the printer operation ends, the flow returns to #
20' branches to #K-24, and it is determined whether program playback is set by detecting whether the program playback mode flag is set. Here, if program playback is set, the flow branches to the above-mentioned #K-3, and if program playback is not set, the flow branches to #K-6. Further, when the stop switch 60 is turned on, the flow is as described above.

Further, if the external trigger mode is selected when program playback is set, the program playback operation is stopped after the program playback has been executed one time as described in #0-3.

Further, according to this embodiment, even if the external trigger mode is selected and program playback is not set, since -10 is set in #, the head 3 -
1. When the playback is performed in sequence from the accessed track in 3-2 to the last track, the playback operation is stopped.

Therefore, in external trigger mode, regardless of whether programmed playback is set or not, the printer will be used as a device that performs external triggers because the playback operation will stop after the normal playback is performed. If used, only one-way printing will occur.

On the other hand, in modes other than external trigger mode, even if program playback is set or not, playback starts again from the beginning after playback is performed in a predetermined order. will be held. Therefore, when such a playback device is used in a mode other than the external trigger mode, so-called endless playback can be performed because playback is performed repeatedly in a predetermined order.

Furthermore, although the external device in this embodiment is a printer, it may be a device having an electric transmission function, or any other device as long as it processes a reproduced signal. good.

Next, the case of setting an ID will be explained.

When the IO main key switches 63 to 72 are turned on in the flow (2), the flow branches to the subroutine (2) shown in FIG.

#R-1; #R if the PB mode flag is set
The process branches to -10 and returns to the flowchart (2). Therefore, in a mode other than the recording mode, even if the 10 key is turned on, virtually nothing is executed in this subroutine. If the PB mode flag is not set, that is, if it is in recording mode, the flow branches from #R-1 to #R-2.

#R-2: Here, it is determined whether the ID setting mode is selected, that is, the ID is superimposed on the video signal to monitor the mode. The method for setting this mode will be described in detail with reference to FIG. 20. If this mode is not selected, the process branches to #R-10 and returns to #A-1 in the flowchart shown in FIG. If this mode is selected, the process branches to #R-3.

#R-3; The CPU 40 retrieves the set position from the register P of the RAM 27 for storing the set position indicating where on the monitor the ID set here is to be displayed.
is read, and data corresponding to the switch turned on among the 10 key switches 63 to 72 is written to an address in the RAM 27 corresponding to the set position. Then the CPU
40 controls the character generator 84 to display the data on the monitor B according to the read set position.

#R-4; Here, wait until the 10 key switches 63 to 72 are turned off once. If the switches that were turned on are turned off, the flow advances to #R-5.

#R-5; Here, the setting positions of data other than the date in the ID are 11 points from 0 to 10 as shown in Figure 21, so if register P is equal to IO, then Branch to #R-6, otherwise branch to #R-7.

#R-6; Here, register P is set to O, and D
The setting position of ATA is initialized.

@R-7; Here, 1 is added to the value of register P and D
The ATA setting position moves to the next setting position.

#R-7-1; Data at the position stored in register P blinks (blinks).

#R-8; In this step, it is determined whether the IO main keys 63 to 72 are turned on, and if they are turned on, the process branches to #R-3 and the 10 key switches are activated according to the flow described above. set I
D is displayed on the motor 13.

If it is not turned on, the process branches to #R-9.

#R-9; Here, it is determined whether any switches other than the 10 key switches 63 to 72 are turned on, and if they are not turned on, the process branches to R-8. If it is turned on, it branches to #R-11.

#R-9-1; Stop blinking the ID displayed on the monitor. Flow proceeds to #R-10.

#R-11; Here, register P at setting position 10
Set O to initialize the ID setting position and select #R-9-1.
Proceed to.

#R-10;・Return to the flow of ■.

As explained above, when the PB mode flag is not set and the I[setting mode, that is, the mode in which the set ID can be monitored, the 10 key switch 6
Each time a switch 3 to 72 is turned on, data corresponding to that switch is generated at a position determined by register P by controlling character generator 84 by CF'U 40.

Next, the ID switch 73 will be explained.

When the switch 73 is turned on, the subroutine ◎ shown in FIG. 20 is called from the flow shown in . Here, subroutine ◎ will be explained.

#Q-1, here it is determined whether or not the PB mode flag is set, and if it is set, #Q-2;
Otherwise, the process branches to #Q-7.

#Q-2; Here, check whether it is in ID display mode or not.
That is, it is determined whether the ID is a mode in which the image signal is superimposed and output on the monitor. If the mode is ID display mode, the process branches to #Q-4; otherwise, the process branches to #Q-3.

#Q-3; Here, the CPU 40 controls the character generator 84 to stop displaying the number 10 output from the generator 84. From here, the flow advances to #Q-6.

#Q-4; Here, the CPU 40 reads from the RAM 27,
The reproduced ID is taken into the CPU 40 and the flow is #Q
-Proceed to 5.

#Q-5; Here, the CPU 40 controls the character generator 84 based on the reproduced ID, and causes the character generator 84 to output the reproduced ID as a character pattern as shown in FIG. 21(a). The flow then proceeds to #Q-6.

#Q-6; Here, if the switch 73 is turned on, the process waits; if it is turned off, the flow proceeds to the next step and returns to the flow of (2).

#Q-7; PB mode flag is not set.
First, when in recording mode, it is determined whether or not it is in ID setting mode. That is, if the ID is in a mode in which the character generator 84 outputs a character pattern superimposed on the video signal, the flow advances to #Q-9. Otherwise, the flow advances to #Q-8.

#Q-8; Here, if it is likely to be determined whether or not the mode in which the character "ID" is being output by the character generator 84 is set, it is set to #Q-1o, otherwise, it is set to #Q-
The flow advances to step 11.

#Q-9, in this step, the CPU 40 uses the character generator 8
4 to stop displaying the ID, and the character generator 8 generates a two-character pattern "ID" as shown in FIG. 21(b).
4 to set the "ID" character display mode. The flow then proceeds to #Q-6. That is, when the ID switch 73 is turned on in the ID setting mode, the "ID" character display mode is set.

#Q-10; In this step, the CPU 40 controls the character generator 84 to stop displaying all character patterns as shown in FIG. 21(c). Then the flow is #Q-
Proceed to step 6.

#Q-11; If the flow reaches this step, I
Since the CPU 40 is neither in the D setting mode nor in the "ID" character display mode, that is, in the mode that stops displaying the ID on the monitor, the CPU 40 uses RAM 2.7 to display the set I.
D is taken in, the character generator 84 is controlled, and the set ID
is output as a character pattern from the character generator 84 as shown in FIG. 21(a). That is, by this step I
D setting mode is set. The flow then proceeds to #Q-6.

As explained above, each time the ID switch 73 is turned on, the I
The display format of D will be rewritten.

In other words, in the playback mode, the ID switch 73
ID display mode in which the playback ID DATA is superimposed on the video signal and monitored every time the playback ID DATA is turned on, and the playback ID
The ID non-display mode in which no data is output will be repeated. Specifically, the ID non-display mode shown in the 10 display mode (C) shown in FIG. 21(a) is repeated. In addition, when in recording mode, there is an ID setting mode that displays all IDs to be set, and an “I
The ID switch 73 has an "ID" character display mode in which only the "D" character is displayed and a mode in which the ID is not displayed on the monitor.
It will switch repeatedly every time you turn it on. That is, specifically, FIG. 21(a).

The modes shown in (b) and (C) will be switched repeatedly. The ID display in the recording mode will be further described below. FIG. 21 (a) in the recording mode.

When recording a video signal in the mode shown in (b), the ID is modulated with the video signal in #N-5 and #N-6 in FIG. 12, is modulated into DPS, and is further frequency-multiplexed with the video signal and recorded. It turns out. Also, Figure 20 (C)
When recording video signals in this mode!
D data is not recorded. However, DATA indicating whether it is inside or outside the frame or field recording is always deleted along with the video signal.

That is, in this embodiment, depending on the number of times the ID switch is pressed, the monitor 1 is
It is possible to switch the display related to ID 3.

In addition, in this embodiment, in the recording mode in which the ID is recorded together with the video signal, there is an ID setting mode in which the display shown in FIG. 21(a) is performed, and in the ID setting mode in which the display shown in FIG.
The reason for providing these two display modes will be explained below.
It is possible to set the year, month, date and 11-digit number, but if you try to display all of the ID information as shown in Figure 21(a), it will occupy a considerable area on the screen of the monitor 13. In particular, there is a problem in that it may interfere with the observation of the image, so a display mode as shown in FIG. 21(b) is provided to solve this problem.

Next, a method of displaying the reproduced ID in the reproduction mode will be explained. That is, in the recording mode, the image shown in FIG. 21 (
A display method for reproducing the ID recorded together with the video signal when the modes shown in a) and (b) are set by the ID switch 73 will be described. In the playback mode, when the head is moved to a new track, the ID recorded on that track will be played back on the monitor 13. This is done by demodulating [) reproduced by the data demodulator 12 shown in FIG. 1, reading this output by the CPU 40, and further driving the character generator 84. The ID read by the CPU 40 is held in the RAM 27 by the CPU 40. The display of such an ID has been explained with reference to FIG. There is.

I) A first display mode that is displayed when an ID recorded in which only the year, month, and date are set as ID data and no other data is set is played back.

II) A second display mode when playing back an ID in which the year, month, date and other numerical data are both set as ID DATA.

FIG. 22(a) shows the ID display in (2).

FIG. 22(b) shows the ID display in (2).

That is, for I), only the year, month, and day are displayed on the lower right side of the monitor, and for (2), the year, month, date and other data are displayed on the lower right side of the monitor. Therefore, the ID information is always displayed in the lower right corner of the monitor screen, so that it can be prevented from interfering with the video signal as much as possible. Further, in this embodiment, the display is displayed in the lower right corner of the screen, but it may be displayed anywhere as long as it is in the corner of the screen.

In order to execute this operation, after reading the output signal of the data demodulator 12 shown in FIG.
All you have to do is generate the characters after confirming that all data other than daily income has not been set. That is, the CPU 40 controls the character generator 84 so that the character generation position is different depending on cases B and n) above.

Also, if it is determined that data other than the date is not the DATA recorded by this device, the 22nd
The display shown in Figure (b) is performed.

This is a well-known check code for ID DATA
It is also possible to distinguish by recording it as ``.

Next, a case will be described in which the year, month, and day are set as the ID. In the flow (2), when the year setting switch 74 is turned on, the flow jumps to the subroutine (2) shown in FIG.

#S-1; If the PB mode flag is set here, the flow advances to #5-14 and returns to the flow of (2). If not set, proceed to #S-2.

#S-2; Here, determine whether the mode is ID setting mode, that is, the mode in which ID data is superimposed on the video signal and output to the monitor or blink link.If it is not in this mode, #S-2; Proceed to 5-14 and return to the flow of ■.If you are in this mode, proceed to #S-3
Proceed to.

#S-3; Here, the year setting position 1 on the monitor 13
Blinking of the number in the 10th digit of the year setting position means that the character in the position shown in ■ in Figure 24 (a) blinks. This means that the CPU 4
This is accomplished by 0 controlling the character generator 84 to generate or not generate a character at this position. This is done by well-known interrupt processing. The flow then proceeds to #S-4.

#S-4; At this point, wait until the switch 74 is turned off. When switch 74 is turned off, the flow is #S-
Proceed to step 5.

#S-5: Here, it is determined whether the 10 key switches 63 to 72 are turned on. If the 10 key switch is on, the flow advances to #S-6. If not, proceed to #5-12.

#S-6, here, the CPU 40 writes the input data from the 10 key switch to the RAM 27, and sets the character generator 84 to the year setting position shown as ■ in FIG. 24(a).
Generate character patterns by controlling . The flow then proceeds to #S-7.

#S-7; Blink the first digit of the year setting position. This means that the characters at the position shown in Figure 24 (■) blink.

Blinking is performed by CPU 40 controlling character generator 84. The flow proceeds to #S-8.

#S-8; At this point, wait until the 10 key switch is turned off. When the 10 key switch is turned off, the flow advances to #S-9.

#S-9: It is determined whether the 10 key switch is turned on or not. If turned on, the flow is #5
-10, otherwise go to #5-13.

#5-10: C if the 10 key switch is turned on
The PU 40 writes the data input by the IO key switch to the RAM 27, and controls the character generator 84 to generate a character pattern at the position shown in ■ in FIG. 24(a), which is the first digit of the year setting position. generate. Then the flow is #
Proceed to 5-11.

#5-11; The CPU 40 controls the character generator 84 to stop the character from blinking at the year setting position. This allows the user to know that the year setting has been completed. Flow proceeds to #5-14.

#5-12; If the IO main key switch is not turned on in #S-5, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, the flag σ- branches to #S-5 and #S-5
゜Repeat steps #5-12, and if a switch other than the lO primary key is turned on, proceed to #5-11.

#5-13; Here, it is determined whether a switch other than the lO primary key is turned on. If it is not turned on, the flow branches to #S-9, and if it is turned on, the flow branches to #5-11. Therefore, until the switch outside the primary key is turned on, #S-9. By repeating steps #5-13, the characters at the year setting position continue to blink, prompting the user to set the year using the 10-key switch.

#5-14; If the PB mode flag is set, if the mode is ID setting mode, and if the blinking is stopped by #5-11, the flow returns to step (2) through this step.

As explained above, when the year setting switch 74 is turned on, the number in the 10th digit of the year setting position starts blinking, thereby informing the operator of the position where data is set. Here, by inputting a number using the IO key switch, the data input to the blinking position is generated as a character pattern by the character generator 84, and the CPU holds the data in the RAM 27.

When the setting of the 10th digit is completed, the number in the 1st digit position will start blinking, and the DAT will be placed at this position in the same way.
Settings for A are performed. Here, when the setting of the first digit is completed, the year setting mode ends and the process returns to the flow shown in ■, but it is also possible to proceed to the flow shown in ■ and enter the month setting mode.

Next, the setting of the month's DATA will be described in detail with reference to subroutine (2) shown in FIG.

In this flow, when the switch 75 is turned on, subroutine (2) is called and the month DATA setting mode is entered.

#T-1; If the PB mode flag is set here, the flow advances to #T-16 and returns to the previous flow.

If the PB mode flag is not set, the flow advances to #T-2.

#T-2; Here, it is determined whether the mode is an ID setting mode, that is, a mode in which ID data is superimposed on a video signal and output to a monitor or printer. If it is not in this mode, proceed to #T-16 and return to the flow of (2). If this mode is selected, proceed to #T-3.

#T-3; Here, blink the 10th digit number at the column setting position on the monitor. The blinking of the 10th digit number at the column setting position means that the character at the position shown by ■ in FIG. 24(a) blinks. This is CPU40
is performed by controlling the character generator 84 to generate or not generate characters. The flow then proceeds to #T-4.

@T-4; Here, wait until the column setting switch 75 is turned off. When the switch 75 is turned off, the flow advances to #T-5.

#T-5; Here, it is determined whether the lO key switches 63 to 72 are turned on. If the 10 key switch is on, the flow proceeds to #T-6; otherwise, the flow proceeds to #T-13.

#T-6; Here, it is determined whether the data input by the lO key switch is 2 or more. If the number is 2 or more, the flow proceeds to #T-14, otherwise the flow proceeds to #T-7. In other words, in the case of column settings, the flow is branched according to the number set in this step in order to accept the first digit number only when the first number input is "l" or "0'". .

#T-7; Here, the CPU 40 stores the input data in the RAM.
27 and controls the character generator 84 to write the character pattern to the position shown in ■ in FIG. 24(a), that is, #.
It is generated at the position blinked at T-3. Flow proceeds to #T-8.

#T-8; Here, blink the first digit number at the column setting position. This means that the character at the position indicated by ■ in FIG. 24(a) blinks. The flow is #T-
Proceed to step 9.

#T-9, wait until the IO key switch is turned off. When the 10 key switch is turned off, the flow is #T
Proceed to -1o.

#T-10: Here, it is determined whether the 10 key switch is turned on. If it is turned on, the flow advances to #T-11; otherwise, the flow advances to #T-15.

#T-11; Here, the CPU 40 writes the data inputted by the 10 key switch in #T-5 or #T-10 to the RAM 27, and
The character generator 84 is controlled to generate a character pattern at the position shown in FIG.
Go to 12. In addition, when branching to this step from @T-14, by executing #T-14゜#T-11, the data entered by the 10 key switch in #T-5 will be displayed in the 1st digit, and the 10th place will be displayed. O" is displayed in the digit.

#T-12; Stops blinking of the data at the column setting position and displays that month setting is completed.

Flow proceeds to #T-16.

#T-13; This step includes 1 in #T-5.
Branches if the 0 key switch is not turned on. Here, it is determined whether any switches other than the IO key are turned on. If it is not turned on, it branches to #T-5, and if it is turned on, it branches to @T-12. That is, lO
#T-5 until the key switch or other switch is turned on. #T
-13 is repeated, and if the 10th key switch is turned on, the flow branches to #T-6, and if any other than the 10th key switch is turned on, the flow branches to #T-12.

#T-14; The process branches to this step when it is determined in #T-6 that the input data is "2" or more. Here, the CPU 40 stores data “0” in the RAM 27.
” and set the character generator 8 to the 10th digit of the column setting position.
4 to generate a character pattern "0". The flow advances to #T-11.

#"F-15, here it is determined whether any switches other than the 10 key are turned on. If they are not turned on, branch to #T-10, and if they are turned on, go to #T-1.
Branches into 2.

$T-t6; Return to the flow of ■.

As explained above, when the switch 75 is turned on, the 10th digit at the month setting position first blinks, thereby first indicating the position at which data to be input using the 10 key switch is to be set. If two or more pieces of data are input here, "0" is automatically set in the 10th digit and the input data is automatically set in the 1st digit. Of course, if there is an input of 1 or less, 10
Needless to say, the next blinking position that is input in the 1st digit moves to the 1st digit, and the next data input using the 1O key is set to the 1st digit. Therefore, according to this embodiment, when setting the month, it is possible to easily set the month by taking advantage of the fact that 2 or more is never set in the 10th digit.

Further, in #T-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

Furthermore, when the setting of the next first digit is completed, the process returns to the flow shown in (2) in this example, but it is also possible to proceed directly to subroutine O shown in FIG. 26 and enter the day setting mode.

Next, the day data setting will be described in detail with reference to FIG. When the switch 76 is turned on in the flow (2), the day data setting mode is called and the flow jumps to (2).

#U-1; If the PB mode flag is set here, the flow advances to #U-16 and returns to the flow of (2). #U if the PB mode flag is not set
Proceed to -2.

#U-2; Here, it is determined whether the mode is the ID data SET mode, that is, the mode in which the ID data is superimposed on the video signal and output to the monitor or printer.

If you are not in this mode, proceed to @U-16.
Return to the flow of ■. If you are in this mode,
#Proceed to U-3.

#U-3; Here, blink the 10th digit number at the fixed sunset position on the monitor. 4. Blinking the 10th digit number at the setting position is the character at the position shown in ■ in Figure 24 (a). means blinking. This is CPU40
is executed by controlling the character generator 84 to generate or not generate characters.

The flow then proceeds to #U-4.

#U-4H At this point, the process waits until the date setting switch 76 is turned off. When switch 76 is turned off, the flow is #
Proceed to U-5.

#U-5; Here, it is determined whether the lO key switches 63 to 72 are turned on. If the 10 key switch is on, the flow advances to #U-6; otherwise, the flow advances to #U-13.

#U-6; Here, it is determined whether the input data is 4 or more using the lO main key switch. If it is 4 or more, the flow goes to #U-14, otherwise it goes to #U-14.
Proceed to U-7. In other words, in the case of column settings, the numbers set in this step are used to add the first digit number only when the first number entered is 3", "2", "l", or "0". Branch the flow accordingly.

#U-7; Here, the CPU 40 sends the input data to RA
M27 and controls the character generator 84 to generate a character pattern at the position shown by ■ in FIG.

The flow proceeds to #U-8.

#U-8; Here, blink the first digit of the sunset position. This means that the characters at the positions indicated by ■ in FIG. 24(a) blink. Flow is #U-9
Proceed to.

#U-9; At this point, wait until the IO key switch is turned off. When the IO primary key switch is turned off, the flow advances to #U-10.

@U-10; Here, it is determined whether the lO main key switch is turned on. If it is turned on, the flow advances to #U-11; otherwise, the flow advances to #U-15.

#U-11; Here, the CPU 40 writes the data inputted by the lO main key switch in #U-5 or #-10 to the RAM 27, and writes a character at the position shown in Figure 24 ■, which is the first digit of the sunset position. Generator 84 is controlled to generate a character pattern, and the flow then proceeds to #U-12. In addition, when branching to this step from #U-14, by executing #U-14゜#U-11,
At #U-5, the data input by the 10 key switch is displayed in the first digit, and "0" is displayed in the tenth digit.

#U-12; Stops blinking of the sunset fixed position data and displays that the date setting is completed.

Flow proceeds to #U-16.

#U-13; This step includes 1 in #U-5.
Branches if the 0 key switch is not turned on. Here, it is determined whether any switches other than the IO key are turned on.

If it is not turned on, it branches to #U-5, and if it is turned on, it branches to #U-12. That is, # until the IO main key switch or other switch is turned on.
U-5. Repeat the flow of #U-13, and if the lO main key switch is turned on, the flow goes to @ 'r -6,
If anything other than the 10 key switch is turned on, the flow will be #
Branch to U-12.

#U-14;--The process branches to this step when it is determined in #U-6 that the input data is "4" or more. Here, the CPU 40 stores data “0” in the RAM 27.
” and controls the character generator 84 to generate a character pattern “0” in the 10th digit of the column setting position.The flow advances to #U-11.

#U-15; Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, branch to #U-10; if it is turned on, it branches to #U-10.
Branches into 12.

#U-16; Return to the flow of ■.

As explained above, when the switch 76 is turned on, the 10th digit at the date setting position first blinks, thereby first indicating the position where the data to be input using the 10 key switch is to be set. If 4 or more data is entered here, "0" will be automatically set in the 10th digit and the input data will be set in the 1st digit. Of course, if 3 or less is entered 10 for
Needless to say, the next blinking position that is input in the 1st digit moves to the 1st digit, and the next data input using the 1O key is set to the 1st digit. Therefore, according to this embodiment, when setting the day, it is possible to easily set the day by taking advantage of the fact that 4 or more is never set in the 10th digit.

Further, in #U-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

In the embodiment described above, the display is blinked to indicate the setting position, but the setting position may be indicated by other methods such as changing the brightness or changing the color.

Next, the erase sequence will be explained. When erasing data, the erase execution switch 78 and erase standby switch 77 shown in FIG. 1 are used. That is, when erasing is to be executed, the switch 77 is used to put the data into an erase standby state in advance, and then the erasure is executed only when the erase execution switch 78 is turned on. Furthermore, there are two modes for erasing: a mode in which a plurality of tracks are continuously erased, and a mode in which only a single track is erased. Hereinafter, the above operation will be described in detail based on the flowchart (2) shown in FIG. In the flowchart A in FIG. 1, when the switch 77 is turned on, the flow calls subroutine (2) and proceeds to #V-1. At this point, the erase standby state is set, but at this time, the buffer memory E for storing the number of erased tracks contains “
FF" is set. Also, the track number accessed by the head 3-1 on the two-digit 7-segment LED 25 that displays the track number is approximately 2.
It performs a blinking operation that repeatedly turns on and off at a frequency of Hz. In other words, the track number display LED blinks (2
Hz period) allows the operator to confirm that the erase standby mode has been set.

That is, compared to a method that uses a dedicated display element to indicate that the erase standby state is in effect, the method of this embodiment not only does not require the use of such a dedicated display element, but also displays the track number. By changing the display format of the display, the standby state for erasing is displayed, making it easier to recognize the track number that is about to be erased. In addition, in this embodiment, the 7 segment LE
Although the standby state for erasing is indicated by blinking the display of D25, it goes without saying that other liquid crystals may be used as the display element, and other than blinking, the display color,
Various methods are possible, such as changing the brightness or changing the form of displayed characters.

In addition, if there is a display that displays other information than the track number, such as the number of free tracks, the display format of the display can be changed as described above to enable the erase standby state. It may be possible to display a certain thing.

The flow then proceeds to #v-2.

#V-2; Here, it is determined whether or not the PB mode flag is set, and if it is set, the flow advances to #v-4; otherwise, it is determined that the switch 77 is turned off. After confirmation, the flow proceeds to #v-3.

#V-3; Here, the subroutine ◎ for setting the playback mode described above is called, the playback mode is set, and the flow advances to #v-4. Therefore, when the erase standby switch 77 is turned on, #V- 2. By executing #V-3, the playback mode is set and the erase standby state is set.

#V-4; Here, it is determined whether the switch 78, that is, the erase execution switch is turned on. If it is on, #V-4-1; if not, @V-1
The flow advances to step 5.

#V-4-1; Here, the branch destination of this step is determined by a switch that is prepared in advance in the case (not shown) of the magnetic sheet 1 and that determines the presence or absence of a claw. In other words, this claw has the function of preventing accidental erasure, and if it is broken off, it is promised in advance not to erase the data. Therefore, if the accidental erasure prevention is set, the flow advances to #V-18. If not set, the flow advances to #v-5.

#V-5; In this step, it is determined whether the value set in the buffer memory E (hereinafter referred to as E) for storing the number of erased tracks is "0". The buffer memory E is previously set to "FF" in #V-1, but the setting value can be changed in #V-15, which will be described later. Here, if the value set in buffer memory E is "O", the flow is #V-1
If not, the flow proceeds to #V-5-1. Next, #v-5-1 will be explained.

#V-5-1; In this step, it is determined whether the value set in the buffer memory E is "FF". If it is "FF", the flow advances to #v-6, and if it is not "FF", the flow advances to #V-5-2.

#V-5-2; Set the field flag and set the field playback mode.

The flow proceeds to #U-6.

#V-6; Here, display the track number 7
Segment LED 25 (7) Blinking power # Switches from 2 Hz set in V-1 to a fast cycle of 5 Hz. In addition, when performing continuous track erasing, use #V-1 described below.
In step 7, the set track number is displayed on the 7-segment LED 25 instead of the track number that the head 3-1 is accessing, but even in such a case, #v-6 should be executed. The track number is automatically switched to be displayed on the 7-segment LED 25. Therefore, the user can confirm which track is currently being erased during continuous track erasing.

#V-7; At ::, the cPU 40 controls the erase signal generator 85 to generate an erase signal, and erase is executed. In addition, when performing erasing, switch 2 shown in Fig. 1 is pressed.
, the switch 3 is controlled to connect at least one of the heads 3-1, 3-2 to a recording amplifier. Here, if the field flag is set, that is, in the field playback mode, the erase current flows only to the head 3-1 shown in FIG. 1 that is playing, and l tracks are erased. When the field flag is cleared, that is, when frame playback is selected, an erase current flows simultaneously to both heads 3-1 and 3-2 shown in FIG.
Erasing of video signals for a frame's worth of tracks, in other words, for two adjacent tracks, is executed.

In addition, in this embodiment, erasure in frame mode is executed only when the flow advances from #V-5-1 to #v-6 without passing through @V-5-2. There is. In other words, in #V-5-1, the value of buffer memory E is “FF”.
”, that is, when the continuous erase mode, which will be described later, is not selected.

#V-8; Wait until erasing is completed.

When erasing is completed, the flow advances to #V-8-1.

#V-8-1; Here, it is determined whether E is equal to "FF". If it is equal to “FF”, it is single erase mode, so the flow goes to #V-ta, otherwise, continuous track erase is set, so the flow goes to #V-9
Proceed to.

#V-9; Here, the value of buffer memory E is subtracted by 1. Flow proceeds to #V-10.

#V-10; In this step, it is determined whether the value of buffer memory E is greater than O.

That is, the number of tracks to be erased when continuous track erasure is set is detected, and if it is greater than 0, the flow proceeds to #V-11; otherwise, it is assumed that continuous track erasure has ended. Proceed to #V-18.

#V-11; In this step, it is determined whether the stop switch 61 is turned on. If it is turned on, the flow branches to #V-18, and if it is not turned on, the flow proceeds to #V-12. That is, the continuous erasing mode, which will be described later, is selected, and if the stop switch 61 is operated while this mode is being executed, the continuous erasing can be interrupted. Flow then proceeds to @V-12.

#V-12; In this step, it is determined whether N of the track number buffer memory is 50 or more, that is, whether the track being accessed by the head 3-1 is the final track. If so, the flow proceeds to @V-18 and ends the erase operation, otherwise proceeds to #V-13.

#V-13; By executing this step, the track position accessed by the heads 3-1, 3-2 moves one track toward the inner circumference. Also head 3-
1. With the movement of 3-2, N+1 is set to N in the track number memory. Then the flow is #V-5-
Branches into 2.

Therefore, when continuously erasing tracks, #V-5-2 to #V-1 are used until the stop switch 61 is turned on or until the innermost track is erased.
The flow of step 3 is repeated until the value of the buffer memory E becomes O, that is, until the set number of tracks has been erased.

Next, the flow after #V-15 for setting the continuous erase mode executed as described above will be explained.

#V-15, determine whether any of the 10 key switches shown in 63 to 72 in FIG. 1 is turned on;
If it is turned on, the flow advances to #V-16; if it is not turned on, the flow advances to #V-15-1.

@V-16; In this step, the continuous track erase mode will be set. In other words, the number input using the 10 key switches 63 to 72 becomes the number of tracks on which continuous erasure is to be performed. In the erase track number buffer E, the numerical value of the turned-on 10 key is set in the 1's digit. Flow then proceeds to #V-17.

#V-17; 7 segment L in this step
The value of E is displayed on ED25. This situation will be explained with reference to FIG. 28. In #V-15, the value of the first 10 key switch turned on is set to the 1 digit of E (#V-15).
16) and is displayed at the 1's digit of the LED 25 in this step, as shown in FIG. 25(a). Here, before reaching the display shown in FIG. 22(a), the track number is displayed on the display and is blinking.

Also, F set to E is displayed as 0''.The numerical value displayed on the display is that the 2Hz blinking operation is still being performed repeatedly in #v-1, so
The display "8t" shown in FIG. 5(a) will blink. The flow then proceeds to #V-17-1.

#V-17-1; At this point, wait until the lO key switch is turned off. When turned off, the flow is @V-15
Proceed to -1.

#V-15-1; Here, it is determined whether the erase standby switch 77 is turned on. If it is turned on, the flow proceeds to #V-18, and if it is not turned on, the flow proceeds to @V-15-2.

That is, by turning on the erase standby switch 77, the erase standby state set in #V-1 is automatically canceled by turning on the switch 77 again and in the steps after @V-18. Therefore, there is no need to provide a dedicated release switch.

#V-15-2; Determine whether or not the switch 78 and the switches other than the IO primary key are turned on. If it is turned on, the flow branches to @V-18, and if it is not turned on, the flow branches to #v-4.

In other words, the erase standby state is automatically canceled by turning on any switch other than the 10 key in steps #V-18 and subsequent steps. Therefore, there is no need to provide a dedicated release switch. Therefore, there is no need to go out of your way to provide a separate switch. Above (7)
#V-15-1. If you pass step #V-15-2 with NO, you will have to repeat the steps described above from #v-4, but the 7-segment LED 25 has already been set to the 25th
The operation when executing steps #v-4 and subsequent steps when "87" shown in the figure is displayed will be described.

@When the lO key switch is turned on in V-15, the number input by the switch in #V-16 is set to the 1st place in the buffer memory E, and the number that was previously set in the 1st place is stored in the buffer memory E. The number set in the 10th place disappears.

For example, if the "5" key of the IO key switch is turned on, #V-16. #V
-17, the display shown in FIG. 28(b) is displayed on the 7-segment LED 25. Of course, the value set in the buffer memory E in the case of 9 is 15.

Next, when a good number "2" is input to the 10-key switch, the display shown in FIG. 25(c) is displayed. On the above front side, in the erase standby state, 1, 5.2 of the 10 main key switches are turned ON in order.

The display shown by the LED 25 in the case of Furthermore, the displayed numerical value matches the value set in E as it is. That is, when a value of "2" or more is set by the IO main key switch, this is equivalent to selection of the continuous erase mode, and the set value becomes the number of tracks on which continuous erase is executed. This situation can be seen in the flow description above if the value of buffer memory E is greater than 0 at #V-10, the flow is #V-1
1, otherwise branch to #V-18, and if track number N is less than 50, UPL the track at #V-13, #V-5-24: Branch,
Continuous erasure is performed by executing steps after #V-6. In other words, in #V-11,
If the stop switch 61 is not turned on, the value of E is 0.
Erasing will continue until the number becomes equal to , or until track No. 50, which is the innermost track, is erased.

Then after performing the steps described above run #
V-18 to #V-204, 1-) will be explained.

#V-18; , ::, :, "c', 7 segment L
ED25 (7) Stop blinking and track No.
is displayed on the display. The flow then reaches #V-19. In other words, this step erase standby state is released.

$V-19: If the switch 77 is turned on, it waits; if it is turned off, it proceeds to #V-20.

#V-20; At this point, the flow returns to the flow shown in A of FIG.

As explained above, when performing erasing, in this embodiment there are two modes: a mode in which erasing is performed only once, a mode in which it is performed continuously, and a mode in which erasing is performed after specifying the number of tracks to be erased consecutively in advance. However, for erasing when the number of erase tracks is not set using the 10-key switch, the value of E in #V-5-1 is set to "
FF", the process moves to #v-6 without passing through #V-5-2. Therefore, if the field flag is cleared in the standby state for erasure, in frame mode In other words, if the field flag is set, erasure of 1 track will be performed in field mode.In other words, if the field flag is set, erasure of 1 track will be performed. In this case, if two tracks used for playback were played in field mode, one track of the playback track will be erased.However, the number of erased tracks is set by the lO main key switch. If "O" is set from the lO main key switch, erasure in field mode is always executed via #V-5-2. Erasing is not executed because the program branches to 18. Also, if "1" is set, the field flag is set in #v-5-2, so even if frames were being played up to that point, Also, of the two tracks that make up the frame image, only the outer track is erased by one track.

Therefore, it is possible to erase only the signal recorded on one of the two tracks constituting a frame image.

Furthermore, when performing continuous track erasing, it is generally assumed in many cases that new information, such as a video signal, is recorded on the erased track. In the embodiment described above, when continuous track erasing is completed, the head 3-1 is located on the last erased track, so when recording new information, the user must press the track UP switch 54 and the track DOWN switch. It is necessary to operate the switch 55 so that the head 3-1 accesses the track on which erasing has started.

Therefore, the next step is to execute continuous track erasing, and when this is completed, the flow for realizing a function that is extremely effective in terms of operability is to have the head 3-1 automatically access the track where continuous erasing has started. is shown in FIG. The flow shown in FIG. 29 is similar to #V-18 shown in FIG.
#V-19(7) This is a flow inserted between each step.

First, when subroutine V is executed, the track number N that is being accessed at that time in #V-1 is stored in memory N'. After the erasure is executed according to the flow described above and reaches #V-18, the flow shown in FIG. 29 is executed. That is, in #V-18-1, it is determined whether the number of the track that the head 3-1 is accessing at that time matches the number of the track stored in the memory N' in #V-1, and if they match. If not, #V-18-2. #V18-3 is executed, the head 3-1 is controlled to access one track on the outer periphery, N-1 is set for N, and memory N is displayed in 7 segment I and ED25. . The flow then returns to #V-18-1 and #V-18-2 . until the number of the track being accessed by the head 3-1 matches the number of the track stored in the memory N'. #V-18-3 is repeated and when the track on which head 3-1 has started erasing is accessed, #V
The flow branches from 18-1 to #V-19, and the above-mentioned #
Steps after V-19 are executed. Therefore, the second
By executing the flow shown in Figure 9, the head 3-1 automatically accesses the track from which erasing started when erasing is completed, so that the operation of manually searching for the position from which erasing started is omitted in the next recording. I can do it.

Furthermore, when performing continuous erasing, the video to be erased is played back for a certain period of time, the operator is made to confirm this, and after determining whether or not the stop switch 61 is turned on, the erasing operation for that track is started. is extremely effective in preventing accidental erasure.

To realize this function, one track is UP in @V-13 of subroutine V shown in FIG.

After executing N+1 for N until executing #v-7, a step for a delay of about 1 second is preferably provided in the step immediately after #v-6, and furthermore, during this delay, the stop switch 61 is Determine whether or not is turned on,
If it is not turned on, go to #v-7, if it is turned on, go to #V-
What is necessary is to provide a step that branches to 18.

By providing such a step, it is possible to confirm the video signal to be erased, so that if a video that is not desired to be erased is played back, continuous erasing can be interrupted by turning on the stop switch 61. Therefore, the probability of erroneous erasing is dramatically reduced.

In addition, when performing continuous erasing, in the above-mentioned embodiment, the flow branches from #V5-1 to #V5-2 in subroutine ①, and by executing #V5-2, all tracks are erased one track at a time in field mode. However, in order to shorten the execution time of continuous erasing, it is necessary to erase two tracks at least once during continuous track erasing by sending an erasing signal to two heads simultaneously in frame mode. is valid. An example in this case will be described below.

First, in FIG. 30, the flow shown in FIG. 30(a) is changed to #V-6 shown in FIG. This step is inserted between the step #V-7, and the flow shown in FIG. 30(b) is the step #V-11. This step is inserted between steps #V-r2. The following flow will be explained.

After subroutine (2) shown in FIG. 27 is executed up to #v-6, #V-6-1 is executed following #v-6. In this step, it is determined whether the number of erased track buffers E is two or more, that is, whether continuous track erasure is being performed.

If it is 2 or more here, the flow is #V-6-2
If not, proceed to #V-7. #V-6
-2i: Set E i:, E -1 and clear the field flag. The flow reaches #v-7.

Here, an erase signal is generated at #v-7 shown in FIG. If the erase signal is supplied to the head that is performing this and the field flag is cleared, the erase signal will be supplied to both heads 3-1 and 3-2 at the same time. #v-8 after erasure is complete
~ #V-11 is executed as described above, and if the continuous erase operation is not completed, the flow is from #V-11 to #V-11.
-1, and it is determined whether the field flag is set. Continuous track erase is not set,
If the field flag is set, the flow advances to #V-12 and follows the flow described above. Also #V-
Continuous track erasure is set in 11-1,
If the field flag is not set, the flow reaches #V-11-2 because two tracks have been erased in #V-7 as described above.
N is set to N, +1, and head 3- is placed on the inner track side.
1°3-2 moves. After that, the flow reaches #V-13, and the head further moves toward the inner circumferential side of the l track according to the above-described flow.

By doing so, when performing continuous erasing, erasing is performed in frame mode until the number of remaining tracks for continuous erasing becomes 1, so that the execution speed of continuous erasing can be increased. However, in this case, if you want to check the video to be erased before executing the erase, following #v-6,
When the field flag is set, heads 3-1 and 3-2 in FIG. is necessary. Also #V
-2. #Skip step V-3 and switch to PB mode, R
In particular, by switching between the EC mode and the EC mode, it may be possible to select a mode in which the reproduced video to be erased during continuous erasure is confirmed and a mode in which the reproduced video is not confirmed. In other words, if you select a mode in which you do not check the images to be erased when performing continuous erasing, and add the flow shown in Figures 30 (a) and (b) to the flow shown in Figure 27, the continuous The erasing time becomes the shortest, and this is a very effective means when erasing all tracks.

Next, subroutine (2) executed when the all-track erase standby switch 79 is turned on will be explained with reference to FIG.

#W-1 The near segment LED 25 flashes "jzuE" (ALL-ERASE) at 2 Hz, indicating the all-track erase standby state.

#W-2: Determine whether or not the PB mode flag is set, and if it is not set and the flow branches to #W-4 if the flow goes to #W-3.

#W-3-1: Clear the PB mode flag to prohibit reproduction of the magnetic sheet l.

#W-3-2 Detect that the switch 79 is turned off and proceed to #W-4.

$W-4: Determine whether the erase switch 78 is on or not. If it is on, the flow branches to #W-9; if not, the flow branches to #W-5.

#W-5: All track erase standby switch 79
Determine whether or not is turned on. If it is on, #W-7
If it is not on, the flow branches to #W-6.

#W-6: Determine whether any switches other than switch 79 are turned on. If it is on, the flow branches to #W-7, and if it is not on, the flow branches to #W-4.

#W-7: Stop the blinking of LED25, and
5 to display N, that is, the track number accessed by the head 3-1.

#W-8: If the switch 79 is turned off at the same time, the process returns to ■.

@W-9: When the erase switch 78 is turned on in #W-4, the flow branches to this step. In this step, it is determined whether or not there is an erroneous erasure prevention claw (not shown). If there is, the flow branches to #W-10; if not, the flow branches to #W-7.

$W-10: Determine whether N is "1", that is, the track number accessed by head 3-1 is "l", and if "l", go to #W-12 with "l". If not #
The flow branches to W-11.

, #W-11: The head 3-1.3-2 is moved to the outer circumferential side by one track, 1 is further subtracted from N, and the flow returns to #W-10. Therefore #W-10. #W-1
The flow branches to #W-12 only when the number of the track being accessed by the head 3-1 becomes 1 by repeatedly executing 1.

#W-12: Flashing N on LED25 (5Hz)
let This allows the user to know which tracks have been erased when all tracks are erased.

#W-13: Field flag is cleared and frame mode is set. Therefore head 3-1.3-2
The track is erased using both.

#W-14: Both 2 steps of the knee are #V-7. #
Same as V-8#W-15.

#W-16: Since both heads 3-1 and 3-2 are used and two tracks are erased without moving the head, in this step the head is moved two tracks to the outer circumferential side and further N is erased. Add 2 to .

#W-17: Determine whether or not N is 50. If it is 5 degrees, the flow branches to #W-7; if not, the flow branches to #W-12, and erasing of all tracks is completed. #W- until
Steps 12 to #W-17 are repeated.

As explained above, in the all-track erase mode, which is executed by turning on the erase switch after turning on the all-track erase standby switch, the PB mode flag is cleared before erasing, and the video to be erased is not confirmed. Furthermore, since erasing is performed two tracks at a time using both magnetic heads 3-1 and 3-2, the time required to erase all tracks is extremely short compared to the method of erasing one track at a time. It's over. Furthermore, when erasing all tracks, the head is moved to the end of the track (in this example, the outermost circumference) and then all the tracks are sequentially erased toward the opposite end. When attempting to erase all tracks, no matter which position the head 3-1 is accessing, all tracks can be surely erased.

Further, during erasing, the number of the track being accessed by the head 3-1 is displayed on the LED 25, so that the user can recognize how much erasing is being performed.

In the embodiments described above, the magnetic sheet 1 is used as the recording medium, but an optical recording medium may be used. A magneto-optical recording medium or other recording medium may also be used. As the recording means, means depending on the recording medium may be used, for example, in the case of an optical disc, an optical head may be used.

In this embodiment, erasure printing is performed to erase information recorded on a recording medium when a second erasure command input is obtained in a first state where a first erasure command input is obtained. When the erase standby switch 78 is turned on in a state where it is detected that the standby switch 77 is turned on, an erase signal is applied to the head 3-1.3-2 for the first time, and recording is performed on the disk-shaped recording medium. Although the device has been described as erasing information, the first erasing command input and the second erasing command input may be generated by the same switch.

Furthermore, in this embodiment, the control means for canceling the first state in response to a command other than the input of the second erase command is erased in the first state (corresponding to the state in which the flow has proceeded to subroutine ①). When the standby switch 78 is turned on, or when a switch other than the switch 77 or 78 is turned on, after #V-18 is executed, the subroutine ■
#V-1 of subroutine ■ for extracting flow from
5-1. #V-15-2.

In addition, in $V-15-2, when any of the switches other than switches 77 and 78 are turned on, #V-
The system is configured to extract from subroutine ■ after executing step 18, but if a specific switch other than switch 77 or 78, such as a clear switch, is provided, only when the clear switch is turned on. It may be configured so that the subroutine is extracted from subroutine (■).

<Effects of the Invention> As explained above, according to the present invention, since erasing is performed in two steps, it is possible to prevent information recorded on a recording medium from being erroneously erased. Further, in the first state where the first erasure command input is obtained, erasing is performed when a second erasure command input is obtained, and when an input other than the second erasure command input is obtained, Since the first state is released, the erase operation can be canceled without being performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing combinations of switching states of SW2 to SW5 shown in FIG. 1, and FIG. 3 is a front view of the device of this embodiment. 4 are front views of the remote control device used with the device, FIGS. 5 to 20, 23, and 25.
Figures 27 to 27 and 29 to 31 are C shown in Figure 1.
Flowchart of PU40, Fig. 21, Fig. 22, Fig. 2
Figure 4 is a diagram for explaining the ID signal displayed on the monitor, Figure 28 is a diagram for explaining the flow of Figure 27,
FIG. 32 is a diagram for explaining signals generated from the erase signal generator 85 shown in FIG. 1. 1-m-magnetic sheet 3-1.3-2-m-head 40-1-CPU

Claims (2)

[Claims] (1) An erasing device that erases information recorded on a recording medium when a second erasure command input is obtained in a first state where the first erasure command input is obtained, An erasing device characterized by comprising a control means for canceling the first state in response to a command other than inputting a second erasing command. (2) The erasing device according to claim 1, wherein the control means includes a control means for canceling the first state in response to a second input of the first erasure command.